default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID10th ASICON 2013: Shenzhen, China
- IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013. IEEE 2013, ISBN 978-1-4673-6415-7
- Wenhua Qiang, Qi Zhang, Wei Miao, Guohong Li, Hui Wang, Songlin Feng:
A power-constrained contrast enhancement algorithm for AMOLED display using histogram segmentation. 1-4 - Wei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng:
A 2D mesh NoC with self-configurable and shared-FIFOs routers. 1-4 - Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao:
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. 1-4 - You Li, Feng Zhang, Yumei Zhou:
A novel equalizer for the high-loss backplane at Nyquist frequency. 1-4 - Shengyou Zhong, Libin Yao, Jiqing Zhang:
A small-area low-power ADC array for image sensor applications. 1-4 - Peng Chen, Rui Guan, Dongpo Chen:
AVCO with F-V linearization techniques for CNS application. 1-4 - Zhaoyang Pi, Lun Zhu, Jingwei Zhang, Dongping Wu, David Wei Zhang, Zhi-Bin Zhang, Shi-Li Zhang:
Ultra-low frequency P(VDF-TrFE) piezoelectric energy harvester on flexible substrate. 1-4 - Xuelong Zhang, Pengjun Wang, Yuejun Zhang
:
Highly stable data SRAM-PUF in 65nm CMOS process. 1-4 - Zongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A fast multi-core virtual platform and its application on software development. 1-4 - Jian Li, Xiangyu Zeng, Jia Zhou:
Simulation design for continuous separating and 3D focusing of particles based on inertial microfluidics. 1-4 - Yan Zhao, Xiaofang Zhou, Chao Lu:
A new channel emulator for low voltage broadband power line communication. 1-4 - Yuanyuan Li, Ning Xu, Yuchun Ma, Jinian Bian:
Incremental 3D NoC synthesis based on physical-aware router merging algorithm. 1-4 - Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng:
H.264 video parallel decoder on a 24-core processor. 1-4 - Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee:
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. 1-4 - Nan Wang, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura:
Timing and resource constrained leakage power aware scheduling in high-level synthesis. 1-4 - Huatao Zhao, Jiongyao Ye, Yuxin Sun, Takahiro Watanabe:
Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors. 1-4 - Tianlong Ma, Cong Liu, Yibo Fan, Xiaoyang Zeng:
A fast 8×8 IDCT algorithm for HEVC. 1-4 - Xiaozong Huang, Luncai Liu, Liu Fan, Jing Zhang, Wengang Huang, Yanlin Zhang, Lei Yu:
A proposed data converter for current signal with temperature-compensated sample resistor. 1-3 - Jixuan Xiang, Jian Mei, Hao Chang, Fan Ye:
A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC. 1-4 - Xinsheng Wang, Mingyang Hu, Mingyan Yu:
Robust current-mode on-chip interconnect signaling scheme in deep submicron. 1-4 - Xiaohao Gao, Takeshi Yoshimura:
Genetic Algorithm based pipeline scheduling in high-level synthesis. 1-4 - Dexue Zhang, Xiaoyang Zeng, Zongyan Wang, Weike Wang, Xinhua Chen:
MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support. 1-4 - Hong-Wun Gao, Te-Kuang Chiang:
A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs. 1-3 - Fei Sun, Pengjun Wang, Haizhen Yu:
Best polarity searching for ternary FPRM logic circuit area based on whole annealing genetic algorithm. 1-4 - Yong Xu, Fei Zhao, Chen Hu, Zheng Sun, Yuanliang Wu, Jianwen Lu:
Design of frequency synthesizer in frequency-hopping transceiver. 1-4 - Jian Lv, Simon S. Ang:
Design philosophy of hysteretic controller for DC-DC switching converters. 1-4 - Shengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao:
A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly. 1-4 - Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren:
Low-complexity synchronizer used in DC-OFDM UWB system. 1-4 - Renfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng:
Design of a high throughput configurable variable-length FFT processor based on switch network architecture. 1-4 - Maoqiang Duan, Xiaoli Huang, Zhijia Yang:
A GFSK transceiver for IEEE Std. 802.15.4g used in China. 1-4 - Jiajia Shao, Liji Wu, Xiangmin Zhang:
Design and implementation of RSA for dual interface bank IC card. 1-4 - Daying Sun, Weifeng Sun, Qing Wang, Shen Xu, Shengli Lu:
A novel digital controller for boost PFC converter with high power factor and fast dynamic response. 1-4 - Makoto Ikeda:
Self-synchronous circuit designs, SSFPGA and SSRSA for low voltage autonomous control and tamper resistivity. 1-4 - Yang Zhao, Bill Yang Liu, Zhiliang Hong:
Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier. 1-4 - Haofan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
Efficient implementation of 3780-point FFT on a 16-core processor. 1-4 - Zhe Chen, Jie Yang, Cong Shi, Nanjian Wu:
A novel architecture of local memory for programmable SIMD vision chip. 1-4 - Yingrui Chen, Teng Wang, Xin'an Wang, Ziyi Hu:
Implementation of an embedded dual-core processor for portable medical electronics applications. 1-4 - Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren:
A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC. 1-4 - Minoru Fujishima:
Low-power high-speed communication with short-millimeter-wave CMOS transceivers. 1-4 - Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi:
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. 1-4 - Kaidi Zhang, Guowei Tao, Xiangyu Zeng, Wenjie Sheng, Jia Zhou:
Compact and portable chemiluminescence detector for glucose. 1-4 - He Tang, Yong Peng, Xiang Lu, Hai Wang, Albert Z. Wang:
Quantitative analysis for high speed interpolated/averaging ADC. 1-4 - Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Variation-aware subthreshold logic circuit design. 1-4 - Qi Wang, Quanquan Li, Shi Chen, Tiejun Zhang, Chaohuan Hou:
An optimized hardware architecture for intra prediction in H.264 decoder. 1-4 - Zhengxiong Hou, Yipeng Wang, Quan Pan, C. Patrick Yue:
A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers. 1-4 - Xiantuo Rao, Teng Wang, Xin'an Wang, Yinhui Wang:
A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors. 1-4 - Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang:
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. 1-4 - Masataka Miyake, Kai Matsuura, Akifumi Ueno:
Compact modeling of the diode reverse recovery effect for leading developments of power electronic applications. 1-4 - Zitao Shi, Xin Wang, Albert Z. Wang, Yuhua Cheng:
A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique. 1-4 - Rui He, Jianfei Xu, Na Yan, Min Hao:
A 20 Gb/s Limiting Amplifier in 65nm CMOS technology. 1-4 - Siqiang Fan, Albert Z. Wang, Bin Zhao:
Folding and interpolation ADC design methodology. 1-4 - Di Wu, Yun Chen, Yuebin Huang, Yeong-Luh Ueng, Li-Rong Zheng, Xiaoyang Zeng:
A high-throughput LDPC decoder for optical communication. 1-4 - Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang:
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. 1-4 - Nagarajan Mahalingam, Yisheng Wang, Kaixue Ma, Shouxian Mou, Kiat Seng Yeo:
A 24 GHz reconfigurable frequency synthesizer for 60 GHz WPAN. 1-4 - Ze-kun Zhou, Haiwu Xie, Yue Shi, Chuankui Wu, Jiangang Huang, Xin Ming, Bo Zhang:
A high-performance current sensing circuit with full-phase sampling capability. 1-4 - Sen Li, Jinguang Jiang, Xifeng Zhou, Zeyu Zhang:
Current-mode square-wave converter with current-rectifying function employing MOCCII. 1-4 - Jianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin:
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. 1-4 - Shuang Yu, Fen Ge, Gui Feng, Ning Wu:
A two-phase floorplanning approach for Application-specific Network-on-Chip. 1-4 - Shili Wu, Xiaowei He, Yuwei Liu, Guoan Chen:
Polarity dependent of gate oxide breakdown from measurements. 1-2 - Chaojie Fan, Wenjie Pan, Ke Wang, Jianjun Zhou:
Digital calibration techniques for interstage gain nonlinearity in pipelined ADCs. 1-4 - Jiajia Jiao, Yuzhuo Fu:
A cost-effective method for masking transient errors in NoC flit type. 1-4 - Meng-Chou Chang, Shih-Ju Tsai:
A low-power ternary content-addressable memory using pulse current based match-line sense amplifiers. 1-4 - Frank Schwierz:
Transition metal dichalcogenides - A new material class for semiconductor electronics? 1-4 - Gui Feng, Fen Ge, Shuang Yu, Ning Wu:
A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture. 1-4 - Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan:
A reconfigurable floating-point FFT architecture. 1-4 - Sujuan Liu, Meihui Zhang, Wenshu Jiang, Junshan Wang, Peipei Qi:
Theory and hardware implementation of an analog-to-Information Converter based on Compressive Sensing. 1-4 - Alvin Joseph, Randy Wolf:
Integrated silicon RF front-end solutions for mobile communications. 1-4 - Wenjian Yu:
RWCap2: Advanced floating random walk solver for the capacitance extraction of VLSI interconnects. 1-4 - Dian Zhou, Guanming Huang:
Design automation of analog circuit considering the process variations. 1-4 - Jifa Hao, T. E. Kopley:
Building-in reliability in BCD (Bipolar-CMOS-DMOS) technologies. 1-4 - Wenjian Yu, Siyu Yang, Qingqing Zhang:
Analytical model of the coupling capacitance between cylindrical through silicon via and horizontal interconnect in 3D IC. 1-4 - Liwei Gong, Yuan Xu, Zhi Zhang, Weiwei Shi, Robert K. F. Teng:
An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technology. 1-4 - Baoguang Liu, Yuan Wang, Guangliang Guo, Song Jia, Xing Zhang:
A novel dynamic element match technique in current-steering DAC. 1-4 - Yanzhao Ma, Shaoxi Wang, Shengbing Zhang, Xiaoya Fan:
An automatic peak-valley current mode step-up/step-down DC-DC converter with smooth transition. 1-4 - Jung-Hun Seo, Weidong Zhou, Zhenqiang Ma:
Toward microwave integrated circuits on flexible substrates (invited). 1-4 - Yunpu Hu, Songping Mai, Yixin Zhao, Chun Zhang:
Low-resistance wide-voltage-range analog switch for implantable neural stimulators. 1-4 - Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung Len Lee:
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. 1-4 - Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng:
Power grid simulation using matrix exponential method with rational Krylov subspaces. 1-4 - Nan-Xiong Huang, Hsi Rong Han, Wen Tui Liao, Chih-Hung Huang, Wen Chun Wang, Miin-Shyue Shiau, Ching-Hwa Cheng, Hong-Chong Wu, Heng-Shou Hsu, Juin J. Liou, Shry-Sann Liao, Ruei-Cheng Sun, Guang-Bao Lu, Don-Gey Liu:
Integrated amorphous-Si TFT circuits for gate drivers on LCD panels. 1-4 - Wenqing Lu, Gerald E. Sobelman, Xiaofang Zhou, Junyan Ren:
FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture. 1-4 - Liuxi Qian, Dian Zhou, Xuan Zeng, Fan Yang, Shengguo Wang:
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement. 1-4 - Ting Li, Dongbing Fu, Yong Zhang, Yan Wang, Lu Liu, Xu Wang:
A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC. 1-4 - Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou:
Analog routing considering min-area constraint. 1-4 - Yuan Xu, Jinsong Liu, Liwei Gong, Zhi Zhang, Robert K. F. Teng:
A high performance VLSI architecture for integer motion estimation in HEVC. 1-4 - Hengzhou Yuan, Zhuo Ma, Yang Guo:
An adaptive multi-modulus frequency divider. 1-4 - Lele Jiang, Song Wen, Wei Tai, Wang Lei, Lifu Chang, Yuhua Cheng:
Device parameter variations of n-MOSFETS with dog-bone layouts in 65nm and 40nm technologies. 1-3 - Takashi Sato:
Statistical simulation methods for circuit performance analysis. 1-4 - Jianfeng Chen, Yuhua Yu, Xiangyu Zeng, Jian Li, Jia Zhou:
Evaluation of Cyanoethyl Pullulan material as the dielectric layer for EWOD devices. 1-4 - Tao Cheng, Tao Yang, Xin Wang, Zhangwen Tang:
A wideband CMOS variable-gain low noise amplifier with novel attenuator. 1-4 - Chong Huang, Xiaochen Gu, Lei Cai, Cong Li, Dun Yan, Bingbing Zhang, Qin Qin, Hongyi Wang, Jiancheng Li:
A high conversion coefficient RF front end of ultra-low power RFID tag. 1-4 - Zuochang Ye:
Pmm: A Matlab toolbox for passive macromodeling in RF/mm-wave circuit design. 1-4 - Zhiyuan Xue, Huan Ying, Yingke Gao, Tiejun Zhang, Donghui Wang, Chaohuan Hou:
A design of configurable image enhancement unit. 1-4 - Tongning Hu, Bo Wang, Ke Lin, Yi Peng, Xin'an Wang:
A three-stage LDO with active feedback frequency compensation and slew-rate enhancement. 1-4 - Leiou Wang:
A new fast median filtering algorithm based on FPGA. 1-4 - Hui Li, Wei Zhu, Ningxi Liu, Cunlin Dong, Chao Meng, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM. 1-3 - Yingke Gao, Diancheng Wu, Quanquan Li, Tiejun Zhang, Chaohuan Hou:
Design and implementation of transaction level processor based on UVM. 1-4 - Huagang Li, Jian Wang, Jinmei Lai:
Weight-based FPGA placement algorithm with wire effect considered. 1-4 - Richard Wong, Rita Fung, Shi-Jie Wen:
Networking industry trends in ESD protection for high speed IOs. 1-4 - Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng:
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. 1-4 - Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao:
TSVs-aware floorplanning for 3D integrated circuit. 1-4 - Peng-Fei Nan, Xu Wang, Xin-Ping Qu:
Ag dendrite formed on the Cu pyramids as SERS substrate. 1-3 - Haoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura:
Power and resource aware scheduling with multiple voltages. 1-4 - Lingzhi Fu, Xiao Yan, Junyu Wang:
A collision and tag number detector for UHF RFID reader conforming to EPC Gen2 protocol. 1-4 - Xiaofei Chen, Yading Shen, Xuecheng Zou, Shuang-Xi Lin, Wanghui Zou:
A new high performance RF LDMOS with vertical n+n-p-p+ drain structure. 1-4 - Qing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. 1-4 - Wenzhe Zhao, Minjie Lv, Hongbin Sun, Nanning Zheng, Tong Zhang:
VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder. 1-4 - Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin:
New DfT architectures for 3D-SICs with a wireless test port. 1-4 - Ran Zhang, Xue Wei, Takahiro Watanabe:
A sorting-based IO connection assignment for flip-chip designs. 1-4 - Yangyang Guo, Liji Wu, Tengfei Zhai, Xiao Yu, Xiangmin Zhang:
Mixed-signal SoC design and low power research for tire pressure monitoring systems. 1-4 - Anwen Huang, Chao Song, Wei Guo, Peng Li, Minxuan Zhang:
An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors. 1-4 - Shanshan Yong, Xin'an Wang, Ying Cao, Yawei Lu, Zheng Xie:
An integrated development environment for reconfigurable operators array. 1-4 - Xingpeng Pan, Rui Guan, Dongpo Chen:
A CMOS PGA with DCOC and I/Q mismatch calibration. 1-4 - D. Y. Lu, X. A. Tran, H. Y. Yu, D. M. Huang, Yung-Yang Lin, S. J. Ding, P. F. Wang, Ming-Fu Li:
Conduction mechanism of self-rectifying n+Si-HfO2-Ni RRAM. 1-4 - Chun-Min Zhang, Qing-Qing Sun, Peng-Fei Wang, David Wei Zhang:
PEALD Ru/RuOx films for ULSI applications and its transition control between metal and metal oxide. 1-4 - Jinmei Lai, Yanquan Luo, Qi Shao, Lichun Bao, Xueling Liu:
A high-resolution TDC implemented in a 90nm process FPGA. 1-3 - Si Chen, Xiaole Cui, Chung Len Lee:
A novel test scheme for NAND flash memory based on built-in oscillator ring. 1-4 - Thomas Wong, Tao Shen:
Network functions for characterization of elementary semiconductor nanostructures. 1-4 - Xiao Yan, Lingzhi Fu, Junyu Wang:
An 8-bit 100KS/s low power successive approximation register ADC for biomedical applications. 1-4 - Hongwei Li, Guang Chen, Huijuan Cheng:
Gate oxide enhancement for whole chip ESD design between different power domains. 1-4 - Xiaofei Chen, Fanhong Liu, Xuecheng Zou, Shuangxi Lin:
A linearized VBE bandgap voltage reference with wide temperature range. 1-4 - Zhige Zou, Wuyue Wang, Jianming Lei, Guoyi Yu, Xuecheng Zou:
A CMOS low-noise amplifier for BCC applications. 1-4 - Wei Zhong, Song Chen, Yang Geng, Takeshi Yoshimura:
Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. 1-4 - Siliang Hua, Donghui Wang, Yan Liu:
A CMOS synchronous time amplifier. 1-4 - Jinming Zhao, Hailong Yao, Yici Cai, Qiang Zhou:
A new splitting graph construction algorithm for SIAR router. 1-4 - Zheng Xie, Xin'an Wang, Zhibin Lian, Qiuping Li, Shanshan Yong:
A universal framework of dual-use model for both performance and functionality based on the abstract state machine. 1-4 - Tony Low:
Graphene electronics and photonics (Invited). 1-2 - Jiangpeng Wang, Jinguang Jiang:
Ultra-low noise and high PSR LDO design. 1-4 - Weijia Ma, Xiaole Cui, Chung Len Lee:
Enhanced error correction against multiple-bit-upset based on BCH code for SRAM. 1-4 - Wenbin Liu, Jinhui Wang, Ligang Hou, Hongyan Yang, Jianbo Kang:
Design and test of an SRAM chip. 1-4 - Yi Peng, Bo Wang, Tongning Hu, Jinhai Zhang, Xin'an Wang:
A 2.4 mW, 11.7±0.4dB, 3 to 5 GHz wide-band LNA for super-regenerative IR-UWB receiver. 1-4 - Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang:
A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph. 1-5 - Masanori Hashimoto:
Soft error immunity of subthreshold SRAM. 1-4 - Yong-xu Zhu, Bin Wu, Yumei Zhou, Kaifeng Xia, Lu Sun:
A configurable distributed systolic array for QR decomposition in MIMO-OFDM systems. 1-5 - Zijia Guo, Teng Wang, Xin'an Wang, Ziyi Hu:
Design of an optimized low-latency interrupt controller for IMS-DPU. 1-4 - Xiaoxu Kang, Chao Yuan, Qingyun Zuo, Changwa Yao, Shoumian Chen, Yuhang Zhao, Yilin Yan, Yuanjun Xu, Weiping Zhou:
Fabrication of silicon-based MEMS capacitive microphone structure with thin starting wafer. 1-3 - Cong Liu, Weiwei Shen, Tianlong Ma, Yibo Fan, Xiaoyang Zeng:
A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder. 1-4 - Jie Cheng, Yun Chen, Wenxu Bao, Yuanzhou Hu, Na Ding, Xiaoyang Zeng:
Positionable wearable fall detection system for elderly assisted living applications. 1-4 - Yu-Chung Hsiao, Luca Daniel:
Sparse basis pursuit on automatic nonlinear circuit modeling. 1-4 - Weiwei Shi, Oliver Chiu-sing Choy, Robert K. F. Teng:
Key component designs of subthreshold baseband processors in passive RF device. 1-4 - Quanquan Li, Qi Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou:
Low power instruction cache design based on branch execution tracks. 1-4 - Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura, Min-You Wu:
Interconnection allocation between functional units and registers in High-Level Synthesis. 1-4 - Hantian Xu, Longxiang Zhang, Xi Tan, Hao Min:
An integrated stacked transformer with large inductance at 900MHz. 1-4 - Jiasen Huang, Hao Chen, Junyan Ren, Fan Ye:
A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system. 1-4 - Yiling Ding, Qi Zhang, Ning Wang, Dunshan Yuan, Guohong Li, Hui Wang, Songlin Feng:
A 10-bit pipelined ADC with improved S/H circuit for CMOS image sensor. 1-4 - Lei Cai, Xiaocheng Gu, Jiancheng Li, Chong Huang, Cong Li, Qin Qin, Junping Guo:
A single branch charge pump without overstress for RFID tag. 1-4 - Wanghui Zou, Xiaofei Chen, Xuecheng Zou:
An improved analytical series resistance model for on-chip stacked inductors. 1-4 - Chu-Hsiang Chia, Pui-Sun Lei, Robert Chen-Hao Chang, Wei-Chih Wang:
A nonlinear weighted PID controlled 12V to 1V DC-DC converter with transient suppression. 1-4 - Guoyue Jiang, Fang Wang, Zhaolin Li, Shaojun Wei:
A power-efficient network-on-chip for multi-core stream processors. 1-4 - Ningxi Liu, Yu Jiang, Qing Dong, Hui Li, Xinyi Hu, Yinyin Lin:
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing. 1-4 - Dun Yan, Jiancheng Li, Songting Li, Xiaochen Gu, Chong Huang:
A fast and accurate automatic frequency calibration scheme for frequency synthesizer. 1-4 - Goro Suzuki, Ryo Yamanaka:
Interconnect waveform calculation method with parameter variation. 1-4 - Long He, Zhihui Chen, Anquan Jiang:
Piezoelectric force microscopy study of local bipolar diode current dependence of preferential domain orientation in BiFeO3 thin films with different thicknesses. 1-4 - Yun Chen, Chaojie Fan, Jianjun Zhou:
Low jitter clock driver for high-performance pipeline ADC. 1-4 - Longcheng Que, Yiying Du, Jian Lv, Yadong Jiang:
Background calibration techniques for multistage pipelined ADCs with dynamic element matching and pseudorandom noise. 1-4 - Yueguo Hao, Qiao Zhang, Xiaopeng Bai, Zitao Shi, Huainan Ma, Yuhua Cheng:
Co-design of ESD protection and LNA in RFIC. 1-4 - Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren:
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. 1-4 - Zhuo Wang, Yuan Dong, Xia Wang, Zekun Zhou, Xin Ming, Bo Zhang:
A high-efficiency high-power BUCK converter based on fully N-type power transistors. 1-4 - Tianchan Guan, Jun Han, Xiaoyang Zeng:
Highly flexible WBAN transmit-receive system based on USRP. 1-4 - Zao Liu, Xin Huang, Sheldon X.-D. Tan, Hai Wang, He Tang:
Distributed task migration for thermal hot spot reduction in many-core microprocessors. 1-4 - Ling Du, Ning Ning, Kejun Wu, Yang Liu, Qi Yu:
A process variation insensitive bandgap reference with self-calibration technique. 1-4 - Jixin Zhang, Ning Xu, Yuchun Ma, Yu Wang, Jinian Bian:
Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs. 1-4 - Zhiqing Chen, Qi Zhang, Ning Wang, Dunshan Yuan, Guohong Li, Hui Wang, Songlin Feng:
A low spur CMOS phase-locked loop with wide tuning range for CMOS Image Sensor. 1-4 - Qi Wang, Yingke Gao, Donghui Wang, Tiejun Zhang, Chaohuan Hou:
Design and implementation of a dynamic loop buffer by reusing the instruction buffer. 1-4 - Massimo Gimignani, Mario Paparo, Domenico Rossi, Salvatore Scaccianoce:
RF design and technology supporting Active Safety in automotive applications. 1-4 - Hanbin Hu, Guoyong Shi, Yan Zhu:
Incremental symbolic construction for topological modeling of analog circuits. 1-4 - Zhiheng Lin, Xi Tan, Hao Min:
A CMOS passive mixer-first receiver front-end for UHF RFID Reader. 1-4 - Ningyuan Yin, Liji Wu, Tengfei Zhai, Xiangmin Zhang, Rui Zhu:
A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC. 1-4 - Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren:
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. 1-4 - Feng Liang, Si-Qi Zhao, Aobo Chen, Gaofeng Wang:
Three-dimensional on-chip inductor design based on through-silicon vias. 1-3 - Jie Lin, Wei Zhou, Zhiyi Yu, Xiaoyang Zeng:
A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks. 1-4 - Tianyi Hu:
A semi-auto interactive 2D-to-3D video conversion technique based on edge detection. 1-4 - Dan Liu, Chuan Jin:
Low noise design and measurement of 32-channel X-ray ROIC. 1-4 - Hanyu Wang, Jinxiang Wang, Yu Lu, Fangfa Fu:
An efficient low-cost fixed-point digital down converter with modified filter bank. 1-4 - Meng-Ting Hsu, Po-Yu Lee, Yu-Zhang Huang:
Design of dual-wideband low noise amplifier base on common gate topology. 1-4 - Biao Wang, Meng Zhang, Xu Cheng, Qi Feng, Xiaoyang Zeng:
A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor. 1-4 - Yuan Xu, Haodong Yao, Liwei Gong, Mingcheng Zhu, Robert K. F. Teng:
A FPGA real-time stereo vision system with luminance control and projected pattern. 1-4 - Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
FFTPL: An analytic placement algorithm using fast fourier transform for density equalization. 1-4 - Yuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren:
A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. 1-4 - Zhe Du, Yu Jin, Shinji Kimura:
Controlling-value-based power gating considering controllability propagation and power-off probability. 1-4 - Geng Zhong, Jian Zhou, Bei Xia:
Parameter and UVM, making a layered testbench powerful. 1-4 - Fan Liu, Junfeng Zhu, Xiaozong Huang, Xun Xiang:
A novel inverse quantization algorithm based on Taylor series for digital audio codecs. 1-3 - Jinguang Jiang, Sen Li:
An equalization system for 2 series-connected Li-ion batteries. 1-3 - Chong Huang, Xiaochen Gu, Lei Cai, Cong Li, Dun Yan, Bingbing Zhang, Qin Qin, Hongyi Wang, Jiancheng Li:
An adaptive Q factor tuning and input impedance matching method for ultra-low power front end of UHF RFID tag. 1-4 - Mika Fujishiro, Masao Yanagisawa, Nozomu Togawa:
Scan-based attack against Trivium stream cipher independent of scan structure. 1-4 - Linghan Wu, Ziqiang Wang, Ke Huang, Shuai Yuan, Xuqiang Zheng, Chun Zhang, Zhihua Wang:
A 10Gb/s analog equalizer in 0.18um CMOS. 1-4 - Lei Li, Jian Wang, Jinmei Lai:
Improved unified interconnect unit for high speed and scalable FPGA. 1-4 - Yuanzhong Paul Zhou, Alan W. Righter, Jean-Jacques Hajjar:
Investigation on effectiveness of series gate resistor in CDM ESD protection designs. 1-4 - Minghua Li, Dian Zhou, Sheng-Guo Wang, Xuan Zeng:
FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp. 1-4 - Hanyang Xu, Jinmei Lai:
A high throughput FPGA embedded DSP architecture design. 1-4 - Xiang Wang, Su Zhang, Wei Ni, Yukun Song, Yanhui Yang, Jichun Bu:
Design of a hybrid reconfigurable coprocessor. 1-4 - Jingbo Xu, Feng Hui, Wen-Zhong Xu, Xu Wang, Peng-Fei Nan, Yu-Ling Liu, Xin-Ping Qu:
Barrier and low k polish with a novel alkaline barrier slurry combining with FA/O chelating agent. 1-4 - Yann Deval, Francois Rivet, Yoan Veyrac, Nicolas Regimbal, Patrick Garrec, Richard Montigny, Didier Belot, Thierry Taris:
Full Software Radio transceivers. 1-4 - Yang Zhang, Quan Chen, Ngai Wong:
Fast transistor-level circuit simulation and variational analysis via the ultra-compact virtual source model. 1-4 - Zhe Li, Yuxiao Lu, Tingting Mo:
Calibration for split capacitor DAC in SAR ADC. 1-4 - Chaojiang Li, Dawn Wang, Myra Boenke, Ted Letavic, John Cohn:
An integrated zigbee transmitter and DC-DC converter on 0.18μm HV RF CMOS technology. 1-4 - Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Patrick Yue:
A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical. 1-4 - Xinrui Zhang, Jian Wang, Dan Chen, Jinmei Lai, Lichun Bao, Xueling Liu:
The timing control design of 65nm block RAM in FPGA. 1-4 - Zheng Sun, Yong Xu, Chen Hu, Guangyan Ma, Yuanliang Wu, Ying Huang:
Design of novel high speed dual-modulus prescaler based on new optimized structure. 1-4 - Bin Liang, Yankang Du:
Two sides of pulse quenching effect on the single-event transient pulse width at circuit-level. 1-4 - Yongsheng Wang, Fang Li, Hualing Yang, Yonglai Zhang, Yanhui Ren:
3D hybrid modeling of substrate coupling noise in lightly doped mixed-signal ICs. 1-4 - Xiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui:
AHardware implementation of DES with combined countermeasure against DPA. 1-4 - Yiwu Yao, Kailiang Zhang, Hongming Chen, Yuhua Cheng:
The decimator with multiplier-free realizations for high precision ADC applications. 1-4 - Bo Wang, Jinhai Zhang, Edouard Ngoya:
A reference spur estimation method for integer-N PLLs. 1-4 - Bing Jing, Yuankun Xue, Fan Ye, Ning Li, Junyan Ren:
Automatic gain control algorithm with high-speed and double closed-loop in UWB system. 1-4 - Xiaoxue Yu, Hong Liu, Hao Min:
Frame synchronization for a narrow-band power line OFDM communication system. 1-4 - Meng-Ting Hsu, Jie-An Huang, Yao-Yan Lee:
Design of drain-gate transformer feedback VCO with body-biasing. 1-4 - Y. L. Shen, P. Zhou, L. H. Wang, Q. Q. Sun, Q. Q. Tao, P. F. Wang, S. J. Ding, D. W. Zhang:
The annealing effect of chemical vapor deposited graphene. 1-4 - Lu Sun, Yuxiao Lu, Tingting Mo:
A 300MHz 10b time-interleaved pipelined-SAR ADC. 1-4 - Zheng Tang, Jing Xie, Zhigang Mao:
A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design. 1-4 - D. M. Huang, C. J. Yao, D. H. Shi, M. F. Li:
An empirical model for static I-V characteristics of double gate tunneling field effect transistor. 1-4 - Fangfa Fu, Liang Wang, Yu Lu, Jinxiang Wang:
Low overhead task migration mechanism in NoC-based MPSoC. 1-4 - Qiuli Li, Yao Qian, Danzhu Lu, Zhiliang Hong:
VCCS controlled LDO with small on-chip capacitor. 1-4 - Gaowei Xu, Yao Zou, Jun Han, Xiaoyang Zeng:
Low power design for FIR filter. 1-4 - Sen Li, Jinguang Jiang, Xifeng Zhou, Zeyu Zhang:
A novel current-mode versatile filter employing CCCDCC and MO-OTA. 1-5 - Jun Dong, Hengliang Zhu, Min Xie, Xuan Zeng:
Graph Steiner tree construction and its routing applications. 1-4 - Yusen Xu, Wei Hu, Fengying Huang, Jiwei Huang:
Design of a novel all-CMOS low power voltage reference circuit. 1-4 - Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan:
Lithography hotspot detection and mitigation in nanometer VLSI. 1-4 - Guoqiang Hang, Yang Yang, Peiyi Zhao, Xiaohui Hu, Xiaohu You:
A clocked differential switch logic using floating-gate MOS transistors. 1-4 - Longxiang Zhang, Hantian Xu, Yingbo Dai, Hao Min:
An NFC system with high sensitivity based on SDR. 1-4 - Jianing Su, Zhenghao Lu:
Reduced complexity implementation of quasi-cyclic LDPC decoders by parity-check matrix reordering. 1-4 - Zhixiang Chen, Yi Fang, Fang Wang, Zhaolin Li:
Implementation of H.264 intra-frame encoding on clustered stream architectures. 1-4 - Jing Li, Xingang Wang:
Developing a design system to help reduce design cycle time. 1-4 - BaoCun Wang, Guoyi Yu, Xiaofei Chen, Li Zhang, Xavier Zou:
Analysis inductively coupling wireless connection in 3D package. 1-5 - Heqing Xu, Song Jia, Jiyu Chen, Yuan Wang, Gang Du:
A current mode sense amplifier with self-compensation circuit for SRAM application. 1-4 - Chao Liang:
Mixed-signal verification methods for multi-power mixed-signal System-on-Chip (SoC) design. 1-4 - Gang He, Dajiang Zhou, Satoshi Goto:
Transform-based fast mode and depth decision algorithm for HEVC intra prediction. 1-4 - Jing Zhu, Yunwu Zhang, Weifeng Sun, Shengli Lu:
A novel Operational Transconductance Amplifier with high Gm using improved differential current redistribution technique (DCRT). 1-4 - Zhaori Bi, Wei Li, Dian Zhou, Xuan Zeng, Sheng-Guo Wang:
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design. 1-4 - Ping Xiang, Zhihao Ding, Guangxi Hu, Hui Chol Ri, Ran Liu, Lingli Wang, Xing Zhou:
Analytic models for electric potential and subthreshold swing of the dual-material double-gate MOSFET. 1-4 - Wei Tai, Lele Jiang, Wang Lei, Song Wen, Lifu Chang, Yuhua Cheng:
Characteristics of n-MOSFETs with stress effects from neighborhood devices. 1-3 - Dexin Kong, Ting Yu, Fengqi Yu:
A temperature sensing front-end using CMOS substrate PNP transistors. 1-4 - Fan Meng, Rui Guan, Dongpo Chen:
Dual control mode AGC for wireless communication system. 1-4 - Meng-Ting Hsu, Yu-Chang Hsieh, An-Cheng Ou:
Design of low power UWB CMOS LNA using RC feedback and body-bias technology. 1-4 - Qi Yang, Xiaoting Hu, Zhongping Qin:
Secure systolic architecture for montgomery modular multiplication algorithm. 1-4 - Chao Feng, Jinhui Wang, Wei Wu, Ligang Hou, Jianbo Kang:
CMOS 1.2V bandgap voltage reference design. 1-4 - Jong-Ho Lee, Kyu-Bong Choi, Jongmin Shin:
Design and analysis of nano-scale bulk FinFETs. 1-3 - Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima:
An acceleration method by GPGPU for analytical placement using quasi-Newton method. 1-4 - Liuxi Qian, Dian Zhou, Xuan Zeng, Shengguo Wang:
Oscillator phase noise verification accounting for process variations. 1-4 - Jinhai Zhang, Bo Wang, Yi Peng, Tongning Hu, Xin'an Wang:
A 800nW high-accuracy RC oscillator with resistor calibration for RFID. 1-4 - Yuwen Wang, Fan Ye, Junyan Ren:
A DLL based low-phase-noise clock multiplier with offset-tolerant PFD. 1-4 - Chenxi Deng:
An area-efficient implementation of ΣΔ ADC multistage decimation filter. 1-5 - Guanming Huang, Dian Zhou, Xuan Zeng, Shengguo Wang:
A practical method for auto-design and optimization of DC-DC buck converter. 1-4 - Yang Li, Liji Wu, Xiangmin Zhang:
Design of 13.56MHz power recovery circuit with signal transmission for contactless bank IC card. 1-4 - Jieqiong Cheng, Junsong Zheng, Xiaofang Zhou, Linshan Zhang:
Implementation of a configurable MIMO detector with complex K-best algorithm. 1-4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-02-14 22:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
