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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 17
Volume 17, Number 1, January 2012
- Freek Verbeek, Julien Schmaltz:
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures. 1:1-1:28 - Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
:
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow. 2:1-2:24 - Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Optimization Algorithms for the Multiplierless Realization of Linear Transforms. 3:1-3:27 - Mario K. Y. Leung, Eric K. I. Chio, Evangeline F. Y. Young:
Postplacement Voltage Island Generation. 4:1-4:15 - Hai Wang, Sheldon X.-D. Tan, Ryan Rakib:
Compact Modeling of Interconnect Circuits over Wide Frequency Band by Adaptive Complex-Valued Sampling Method. 5:1-5:22 - Jing-Wei Lin, Tsung-Yi Ho, Iris Hui-Ru Jiang:
Reliability-Driven Power/Ground Routing for Analog ICs. 6:1-6:26 - Charalambos Ioannides, Kerstin Eder:
Coverage-Directed Test Generation Automated by Machine Learning - A Review. 7:1-7:21 - Zhaoliang Pan, Melvin A. Breuer:
Error Rate Estimation for Defective Circuits via Ones Counting. 8:1-8:14 - Huan-Kai Peng, Hsuan-Ming Huang, Yu-Hsin Kuo, Charles H.-P. Wen:
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs. 9:1-9:24 - Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He:
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. 10:1-10:23
Volume 17, Number 2, April 2012
- Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay:
An Extended SystemC Framework for Efficient HW/SW Co-Simulation. 11:1-11:16 - Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar:
Optimized 3D Network-on-Chip Design Using Simulated Allocation. 12:1-12:19 - Guangyu Sun, Huazhong Yang, Yuan Xie:
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs. 13:1-13:20 - Chin-Hsien Wu, Hsin-Hung Lin:
Timing Analysis of System Initialization and Crash Recovery for a Segment-Based Flash Translation Layer. 14:1-14:21 - Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel:
Computer Generation of Hardware for Linear Digital Signal Processing Transforms. 15:1-15:33 - Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang:
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic. 16:1-16:15 - Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui, Michio Komoda, Nobuhiro Tsuda:
A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule. 17:1-17:22 - Dong Xiang, Zhen Chen, Laung-Terng Wang:
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing. 18:1-18:24
Volume 17, Number 3, June 2012
- Sandip Ray, Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Aarti Gupta:
Introduction to special section on verification challenges in the concurrent world. 19:1-19:3 - Freek Verbeek, Julien Schmaltz:
Towards the formal verification of cache coherency at the architectural level. 20:1-20:16 - Jim Holt, Jaideep Dastidar, David Lindberg, John Pape, Peng Yang:
A full lifecycle performance verification methodology for multicore systems-on-chip. 21:1-21:18 - Mohamed Elwakil, Zijiang Yang:
Deterministic replay for message-passing-based concurrent programs. 22:1-22:30 - Etem Deniz, Alper Sen, Jim Holt:
Verification and coverage of message passing multicore applications. 23:1-23:31 - Xiaoke Qin, Prabhat Mishra:
Directed test generation for validation of multicore architectures. 24:1-24:21 - Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis:
Targeted random test generation for power-aware multicore designs. 25:1-25:19 - Wooyoung Jang, David Z. Pan:
A3MAP: Architecture-aware analytic mapping for networks-on-chip. 26:1-26:22 - Mohammad H. Foroozannejad, Trevor L. Hodges, Matin Hashemi, Soheil Ghiasi:
Postscheduling buffer management trade-offs in streaming software synthesis. 27:1-27:31 - Hassan A. Salamy, J. Ramanujam:
An ILP solution to address code generation for embedded applications on digital signal processors. 28:1-28:23 - Benjamin Carrión Schäfer, Kazutoshi Wakabayashi:
Divide and conquer high-level synthesis design space exploration. 29:1-29:19 - Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar:
Formal verification of code motion techniques using data-flow-driven equivalence checking. 30:1-30:37 - Éamonn Linehan, Eamonn O'Toole, Siobhán Clarke:
Model-driven automation for simulation-based functional verification. 31:1-31:25 - Haifeng Qian, Sachin S. Sapatnekar, Eren Kursun:
Fast poisson solvers for thermal analysis. 32:1-32:23 - Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis:
High-performance clock mesh optimization. 33:1-33:17 - Kuan-Yu Lin, Hong-Ting Lin, Tsung-Yi Ho, Chia-Chun Tsai:
Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs. 34:1-34:22 - Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai:
A fast heuristic approach for parametric yield enhancement of analog designs. 35:1-35:20
Volume 17, Number 4, October 2012
- Chia-Heng Tu, Shih-Hao Hung, Tung-Chieh Tsai:
MCEmu: A Framework for Software Development and Performance Analysis of Multicore Systems. 36:1-36:25 - Bijan Alizadeh:
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors. 37:1-37:8 - Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay, Scott Little, John Havlicek, Srikanth Chandrasekaran:
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice. 38:1-38:25 - Hai Lin, Yunsi Fei:
Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design. 39:1-39:20 - Hai Lin, Tiansi Hu, Yunsi Fei:
A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors. 40:1-40:19 - An-Ping Wang, Jiwon Hahn, Mahshid Roumi, Pai H. Chou:
Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral Transparency. 41:1-41:26 - Matthew B. Gately, Mark B. Yeary, Choon Yik Tang:
An Algorithm for Jointly Optimizing Quantization and Multiple Constant Multiplication. 42:1-42:24 - YongHwan Kim, Sanghoon Kwak, Taewhan Kim:
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint. 43:1-43:29 - John D. Backes, Marc D. Riedel:
The Synthesis of Cyclic Dependencies with Boolean Satisfiability. 44:1-44:24 - David R. Bild, Robert P. Dick, Gregory E. Bok:
Static NBTI Reduction Using Internal Node Control. 45:1-45:30 - Nai-Wen Chang, Tzu-Yin Lin, Sun-Yuan Hsieh:
Conditional Diagnosability of k-Ary n-Cubes under the PMC Model. 46:1-46:14 - Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta:
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults. 47:1-47:20 - Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang:
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. 48:1-48:16 - Mohammed G. Khatib:
Migration-Resistant Policies for Probe-Wear Leveling in MEMS Storage Devices. 49:1-49:27 - Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu:
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme. 50:1-50:21 - Ruijing Shen, Sheldon X.-D. Tan, Hai Wang, Jinjun Xiong:
Fast Statistical Full-Chip Leakage Analysis for Nanometer VLSI Systems. 51:1-51:19
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