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ORCIDLei He 0001
Person information
- affiliation: University of California, Los Angeles, Department of Electrical Engineering, CA, USA
- affiliation (1999 - 2002): University of Wisconsin, Madison, WI, USA
Other persons with the same name
- Lei He — disambiguation page
- Lei He 0002
![[0000-0002-7433-499X]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-7433-499X")
— Hefei University of Technology, School of Computer and Information, China - Lei He 0003 — Central South University, School of Business, Changsha, China
- Lei He 0004 — Chinese Academy of Sciences, National Laboratory of Pattern Recognition, Beijing, China
- Lei He 0005 — Microsoft China, Speech and Language Group, Beijing, China
- Lei He 0006 — Chengdu University of Information Technology, School of Software Engineering, Chengdu, China (and 1 more)
- Lei He 0007 — Library of Congress, Washington, DC, USA (and 3 more)
- Lei He 0008 — China National Digital Switching System Engineering and Technology Research Center (NDSC), Zhengzhou, China
- Lei He 0009 — National University of Defense Technology, College of Information System and Management, Changsha, China
- Lei He 0010 — Hunan University of Science and Technology, School of Information and Electrical Engineering, Xiangtan, China (and 1 more)
- Lei He 0011 — Tongji University School of Medicine, Tongji Hospital, Department of Spine Surgery, Shanghai, China (and 1 more)
- Lei He 0012 — Xidian University, School of Computer Science and Technology, Xi'an, China (and 1 more)
- Lei He 0013 — Sichuan University, School of Mechanical Engineering, Chengdu, China
- Lei He 0014 — Southeast University, School of Civil Engineering, Nanjing, China (and 1 more)
- Lei He 0015 — Northwestern Polytechnical University, School of Marine Science and Technology, Xi'an, China
- Lei He 0016 — Chinese Academy of Science, Institute of Computing Technology, State Key Laboratory of Computer Architecture, Beijing, China
- Lei He 0017 — Jilin University, State Key Laboratory of Automotive Simulation and Control, Changchun, China (and 1 more)
- Lei He 0018 — China University of Petroleum -Beijing, National Engineering Laboratory for Pipeline Safety, Beijing, China
- Lei He 0019 — Shanghai Jiao Tong University, Department of Automation, Key Laboratory of System Control and Information Processing, Shanghai, China
- Lei He 0020 — Toshiba (China) Research and Development Center, Beijing China
- Lei He 0021 — University of Zurich, Department of Comparative Linguistics, Phonetics Laboratory, Zurich, Switzerland
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2020 – today
- 2025
[c186]Junzhuo Zhou, Haoxuan Xia, Wei W. Xing, Ting-Jung Lin, Li Huang, Lei He:
LVFGen: Efficient Liberty Variation Format (LVF) Generation Using Variational Analysis and Active Learning. ISPD 2025: 182-190- [c185]Tianjia Zhou, Cheng Chang, Li Huang, Jingyun Gu, Zexin Ji, Xiangyang Liu, Hailang Liang, Zhanfei Chen, Ting-Jung Lin, Song Wang, Na Bai, Zhengping Li, Lei He:
Abuttable Analog Cell Library and Automatic AMS Layout. ISPD 2025: 191-199 - 2024
- [c184]Junzhuo Zhou, Li Huang, Haoxuan Xia, Yihui Cai, Leilei Jin, Xiao Shi, Wei W. Xing, Ting-Jung Lin, Lei He:
LVF2: A Statistical Timing Model based on Gaussian Mixture for Yield Estimation and Speed Binning. DAC 2024: 46:1-46:6 - [c183]Wei W. Xing, Yanfang Liu, Weijian Fan, Lei He:
Every Failure Is A Lesson: Utilizing All Failure Samples To Deliver Tuning-Free Efficient Yield Evaluation. DAC 2024: 166:1-166:6 - [c182]Yanfang Liu, Lei He, Wei W. Xing:
Beyond the Yield Barrier: Variational Importance Sampling Yield Analysis. ICCAD 2024: 36:1-36:9 - [c181]Tiandong Zhao, Shaoqiang Lu, Chen Wu, Lei He:
ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity. ICCAD 2024: 203:1-203:9 - [c180]Xuliang Yu, Tianwei Ni, Xinsong Sheng, Yun Pan, Lei He, Liang Zhao:
AESHA: Accelerating Eigen-decomposition-based Sparse Transformer with Hybrid RRAM-SRAM Architecture. ICCAD 2024: 211:1-211:9 - [i22]Yanfang Liu, Lei He, Wei W. Xing:
Beyond the Yield Barrier: Variational Importance Sampling Yield Analysis. CoRR abs/2407.00711 (2024) - 2023
- [j95]Zhuofu Tao, Chen Wu, Yuan Liang, Kun Wang, Lei He:
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator. ACM Trans. Reconfigurable Technol. Syst. 16(1): 10:1-10:19 (2023) - [c179]Tiandong Zhao, Siyuan Miao, Shaoqiang Lu, Jialin Cao, Jun Qiu, Xiao Shi, Kun Wang, Lei He:
Token Packing for Transformers with Variable-Length Inputs. FPL 2023: 49-56 - [c178]Weinan Song, Gaurav Fotedar, Nima Tajbakhsh, Ziheng Zhou, Lei He, Xiaowei Ding:
MDT-Net: Multi-Domain Transfer by Perceptual Supervision for Unpaired Images in OCT Scan. ISBI 2023: 1-5 - [i21]Weinan Song, Haoxin Zheng, Jiawei Yang, Chengwen Liang, Lei He:
Oral-NeXF: 3D Oral Reconstruction with Neural X-ray Field from Panoramic Imaging. CoRR abs/2303.12123 (2023) - [i20]Weinan Song, Yaxuan Zhu, Lei He, Yingnian Wu, Jianwen Xie:
Progressive Energy-Based Cooperative Learning for Multi-Domain Image-to-Image Translation. CoRR abs/2306.14448 (2023) - 2022
- [j94]Yinqiu Liu, Kai Qian, Kun Wang, Lei He:
BCmaster: A Compatible Framework for Comprehensively Analyzing and Monitoring Blockchain Systems in IoT. IEEE Internet Things J. 9(22): 22529-22546 (2022) - [j93]Li Gong, Jinlong Yan, Yiqiao Chen, Jinjing An, Lei He, Lirong Zheng, Zhuo Zou:
An IoT-based intelligent irrigation system with data fusion and a self-powered wide-area network. J. Ind. Inf. Integr. 29: 100367 (2022) - [j92]Yinqiu Liu, Kai Qian, Kun Wang, Lei He:
Effective Scaling of Blockchain Beyond Consensus Innovations and Moore's Law: Challenges and Opportunities. IEEE Syst. J. 16(1): 1424-1435 (2022) - [j91]Xiao Shi, Hao Yan, Qiancun Huang, Chengzhen Xuan, Lei He, Longxing Shi:
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation. ACM Trans. Design Autom. Electr. Syst. 27(2): 19:1-19:23 (2022) - [j90]Chen Wu, Mingyu Wang, Xinyuan Chu, Kun Wang, Lei He:
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration. ACM Trans. Reconfigurable Technol. Syst. 15(1): 6:1-6:21 (2022) - [c177]Jiawei Yang, Hanbo Chen, Yuan Liang, Junzhou Huang, Lei He, Jianhua Yao:
ConCL: Concept Contrastive Learning for Dense Prediction Pre-training in Pathology Images. ECCV (21) 2022: 523-539 - [c176]Chen Wu, Zhuofu Tao, Kun Wang, Lei He:
SkeletonGCN: A Simple Yet Effective Accelerator For GCN Training. FPL 2022: 445-451 - [c175]Jiawei Yang, Hanbo Chen, Yu Zhao, Fan Yang, Yao Zhang, Lei He, Jianhua Yao:
ReMix: A General and Efficient Framework for Multiple Instance Learning Based Whole Slide Image Classification. MICCAI (2) 2022: 35-45 - [c174]Hanbo Chen, Jiawei Yang, Daniel Maxim Iascone, Lijuan Liu, Lei He, Hanchuan Peng, Jianhua Yao:
TreeMoCo: Contrastive Neuron Morphology Representation Learning. NeurIPS 2022 - [i19]Jiawei Yang, Hanbo Chen, Yu Zhao, Fan Yang, Yao Zhang, Lei He, Jianhua Yao:
ReMix: A General and Efficient Framework for Multiple Instance Learning based Whole Slide Image Classification. CoRR abs/2207.01805 (2022) - [i18]Jiawei Yang, Hanbo Chen, Yuan Liang, Junzhou Huang, Lei He, Jianhua Yao:
ConCL: Concept Contrastive Learning for Dense Prediction Pre-training in Pathology Images. CoRR abs/2207.06733 (2022) - 2021
- [j89]Yan Zhang, Kun Wang, Lei He:
Editorial for FGCS special issue: Computation Intelligence for Energy Internet. Future Gener. Comput. Syst. 115: 295-297 (2021) - [j88]Shuai Han, Sai Xu, Weixiao Meng, Lei He:
Channel-Correlation-Enabled Transmission Optimization for MISO Wiretap Channels. IEEE Trans. Wirel. Commun. 20(2): 858-870 (2021) - [c173]Weinan Song, Yuan Liang, Jiawei Yang, Kun Wang, Lei He:
Oral-3D: Reconstructing the 3D Structure of Oral Cavity from Panoramic X-ray. AAAI 2021: 566-573 - [c172]Tiandong Zhao, Yunxuan Yu, Kun Wang, Lei He:
Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNs. FCCM 2021: 264 - [c171]Hamza Khan, Asma Khan, Zainab Khan, Lun Bin Huang, Kun Wang, Lei He:
NPE: An FPGA-based Overlay Processor for Natural Language Processing. FPGA 2021: 227 - [c170]Chen Wu, Jinming Zhuang, Kun Wang, Lei He:
MP-OPU: A Mixed Precision FPGA-based Overlay Processor for Convolutional Neural Networks. FPL 2021: 33-37 - [c169]Jiawei Yang, Yuan Liang, Yao Zhang, Weinan Song, Kun Wang, Lei He:
Exploring Instance-Level Uncertainty for Medical Detection. ISBI 2021: 448-452 - [c168]Weinan Song, Yuan Liang, Jiawei Yang, Kun Wang, Lei He:
T-Net: Learning Feature Representation With Task-Specific Supervision For Biomedical Image Analysis. ISBI 2021: 1924-1928 - [c167]Yuan Liang, Liang Qiu, Tiancheng Lu, Zhujun Fang, Dezhan Tu, Jiawei Yang, Yiting Shao, Kun Wang, Xiang 'Anthony' Chen, Lei He:
OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray. IUI 2021: 553-563 - [c166]Jiawei Yang, Yao Zhang, Yuan Liang, Yang Zhang, Lei He, Zhiqiang He:
TumorCP: A Simple but Effective Object-Level Data Augmentation for Tumor Segmentation. MICCAI (1) 2021: 579-588 - [c165]Yuan Liang, Weikun Han, Liang Qiu, Chen Wu, Yiting Shao, Kun Wang, Lei He:
Exploring Forensic Dental Identification with Deep Learning. NeurIPS 2021: 3244-3258 - [i17]Yuan Liang, Liang Qiu, Tiancheng Lu, Zhujun Fang, Dezhan Tu, Jiawei Yang, Tiandong Zhao, Yiting Shao, Kun Wang, Xiang 'Anthony' Chen, Lei He:
OralViewer: 3D Demonstration of Dental Surgeries for Patient Education with Oral Cavity Reconstruction from a 2D Panoramic X-ray. CoRR abs/2101.00098 (2021) - [i16]Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He:
Atlas-aware ConvNetfor Accurate yet Robust Anatomical Segmentation. CoRR abs/2102.01256 (2021) - [i15]Hamza Khan, Asma Khan, Zainab Khan, Lun Bin Huang, Kun Wang, Lei He:
NPE: An FPGA-based Overlay Processor for Natural Language Processing. CoRR abs/2104.06535 (2021) - [i14]Jiawei Yang, Yao Zhang, Yuan Liang, Yang Zhang, Lei He, Zhiqiang He:
TumorCP: A Simple but Effective Object-Level Data Augmentation for Tumor Segmentation. CoRR abs/2107.09843 (2021) - [i13]Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He:
X2Teeth: 3D Teeth Reconstruction from a Single Panoramic Radiograph. CoRR abs/2108.13004 (2021) - [i12]Tiandong Zhao, Yunxuan Yu, Kun Wang, Lei He:
Heterogeneous Dual-Core Overlay Processor for Light-Weight CNNs. CoRR abs/2110.01103 (2021) - [i11]Zhuofu Tao, Chen Wu, Yuan Liang, Lei He:
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator. CoRR abs/2111.03184 (2021) - 2020
- [j87]Sai Xu, Shuai Han, Weixiao Meng, Lei He:
QoS-Based Robust Cooperative-Jamming-Aided Beamforming for Correlated Wiretap Channels. IEEE Signal Process. Lett. 27: 216-220 (2020) - [j86]Xiao Shi, Hao Yan, Jinxin Wang, Jiajia Zhang, Longxing Shi, Lei He:
An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4999-5010 (2020) - [j85]Yunxuan Yu, Chen Wu, Tiandong Zhao, Kun Wang, Lei He:
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 35-47 (2020) - [j84]Yunxuan Yu, Tiandong Zhao, Mingyu Wang, Kun Wang, Lei He:
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1545-1556 (2020) - [j83]Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He:
Correlation-Based Cooperative Jamming to Enhance Secrecy With Receiver-Side Correlation. IEEE Trans. Veh. Technol. 69(2): 1903-1912 (2020) - [j82]Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He:
Correlation-Based Secure Transmission for Correlated MISO Wiretap Channels. IEEE Wirel. Commun. Lett. 9(3): 302-305 (2020) - [j81]Sai Xu, Shuai Han, Weixiao Meng, Shuo Yan, Lei He:
Robust Beamforming Design for Correlated MISO Wiretap Channels Under Channel Uncertainty. IEEE Wirel. Commun. Lett. 9(4): 553-557 (2020) - [c164]Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He:
Atlas-aware ConvNet for Accurate yet Robust Anatomical Segmentation. ACML 2020: 113-128 - [c163]Yuan Liang, Hsuan-Wei Fan, Zhujun Fang, Leiying Miao, Wen Li, Xuan Zhang, Weibin Sun, Kun Wang, Lei He, Xiang Anthony Chen:
OralCam: Enabling Self-Examination and Awareness of Oral Health Using a Smartphone Camera. CHI 2020: 1-13 - [c162]Yunxuan Yu, Tiandong Zhao, Kun Wang, Lei He:
Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks. FPGA 2020: 122-132 - [c161]Chen Wu, Mingyu Wang, Xinyuan Chu, Kun Wang, Lei He:
Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration. FPGA 2020: 318 - [c160]Xiao Shi, Hao Yan, Chuwen Li, Jianli Chen, Longxing Shi, Lei He:
A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield Analysis. ICCAD 2020: 7:1-7:8 - [c159]Yuan Liang, Weinan Song, Jiawei Yang, Liang Qiu, Kun Wang, Lei He:
X2Teeth: 3D Teeth Reconstruction from a Single Panoramic Radiograph. MICCAI (2) 2020: 400-409 - [i10]Yinqiu Liu, Kai Qian, Jinlong Yu, Kun Wang, Lei He:
Effective scaling of blockchain beyond consensus innovations and Moore's law. CoRR abs/2001.01865 (2020) - [i9]Yuan Liang, Hsuan-Wei Fan, Zhujun Fang, Leiying Miao, Wen Li, Xuan Zhang, Weibin Sun, Kun Wang, Lei He, Xiang Anthony Chen:
OralCam: Enabling Self-Examination and Awareness of Oral Health Using a Smartphone Camera. CoRR abs/2001.05621 (2020) - [i8]Weinan Song, Yuan Liang, Kun Wang, Lei He:
T-Net: A Template-Supervised Network for Task-specific Feature Extraction in Biomedical Image Analysis. CoRR abs/2002.08406 (2020) - [i7]Weinan Song, Yuan Liang, Kun Wang, Lei He:
Oral-3D: Reconstructing the 3D Bone Structure of Oral Cavity from 2D Panoramic X-ray. CoRR abs/2003.08413 (2020) - [i6]Shengyun Peng, Yunxuan Yu, Kun Wang, Lei He:
Accurate Anchor Free Tracking. CoRR abs/2006.07560 (2020) - [i5]Jiawei Yang, Yuan Liang, Yao Zhang, Weinan Song, Kun Wang, Lei He:
Exploring Instance-Level Uncertainty for Medical Detection. CoRR abs/2012.12880 (2020)
2010 – 2019
- 2019
- [j80]Sai Xu, Shuai Han, Ya-Nan Du, Weixiao Meng, Lei He, Chengwen Zhang:
AN-Aided Secure Beamforming Design for Correlated MISO Wiretap Channels. IEEE Commun. Lett. 23(4): 628-631 (2019) - [j79]Sai Xu, Shuai Han, Wei-Xiao Meng, Ya-Nan Du, Lei He:
Multiple-Jammer-Aided Secure Transmission With Receiver-Side Correlation. IEEE Trans. Wirel. Commun. 18(6): 3093-3103 (2019) - [c158]Xiao Shi, Jinlong Yan, Hao Yan, Jiajia Zhang, Jinxin Wang, Longxing Shi, Lei He:
Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling. ASICON 2019: 1-4 - [c157]Xiao Shi, Hao Yan, Qiancun Huang, Jiajia Zhang, Longxing Shi, Lei He:
Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor Approximation. DAC 2019: 150 - [c156]Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. ICCAD 2019: 1-8 - [c155]Tingshen Lan, Xingquan Li, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang:
Timing-Aware Fill Insertions with Design-Rule and Density Constraints. ICCAD 2019: 1-8 - [c154]Xiao Shi, Hao Yan, Jiajia Zhang, Qiancun Huang, Longxing Shi, Lei He:
Efficient Yield Analysis for SRAM and Analog Circuits using Meta-Model based Importance Sampling Method. ICCAD 2019: 1-8 - [c153]Xiao Shi, Hao Yan, Jinxin Wang, Xiaofen Xu, Fengyuan Liu, Longxing Shi, Lei He:
Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis. ISPD 2019: 139-146 - [c152]Yuan Liang, Weinan Song, J. P. Dym, Kun Wang, Lei He:
CompareNet: Anatomical Segmentation Network with Deep Non-local Label Fusion. MICCAI (3) 2019: 292-300 - [i4]Shuai Han, Sai Xu, Weixiao Meng, Lei He:
Channel-Correlation-Enabled Transmit Optimization for MISO Wiretap Channels. CoRR abs/1907.01064 (2019) - [i3]Yuan Liang, Weinan Song, J. P. Dym, Kun Wang, Lei He:
CompareNet: Anatomical Segmentation Network with Deep Non-local Label Fusion. CoRR abs/1910.04797 (2019) - 2018
- [j78]Kun Wang, Yan Zhang, Song Guo, Mianxiong Dong, Rose Qingyang Hu, Lei He:
IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications. IEEE Access 6: 79272-79275 (2018) - [j77]Kun Wang, Yan Zhang, Song Guo, Mianxiong Dong, Rose Qingyang Hu, Lei He:
IEEE Access Special Section Editorial: The Internet of Energy: Architectures, Cyber Security, and Applications - Part II. IEEE Access 6: 79276-79279 (2018) - [j76]Chen Chen, Lei He, Hongsheng Li, Junzhou Huang:
Fast iteratively reweighted least squares algorithms for analysis-based sparse reconstruction. Medical Image Anal. 49: 141-152 (2018) - [j75]Min Gao, Kun Wang, Lei He:
Probabilistic Model Checking and Scheduling Implementation of an Energy Router System in Energy Internet for Green Cities. IEEE Trans. Ind. Informatics 14(4): 1501-1510 (2018) - [c151]Xiao Shi, Fengyuan Liu, Jun Yang, Lei He:
A fast and robust failure analysis of memory circuits using adaptive importance sampling method. DAC 2018: 134:1-134:6 - [c150]Juexiao Su, Lei He:
Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only). FPGA 2018: 289 - [i2]Liang Qiu, Yuanyi Ding, Lei He:
Recurrent Neural Networks with Pre-trained Language Model Embedding for Slot Filling Task. CoRR abs/1812.05199 (2018) - 2017
- [j74]Jinlong Yan, Qi Zeng, Yuan Liang, Lei He, Zhengping Li:
Modeling and Implementation of Electroactive Smart Air-Conditioning Vent Register for Personalized HVAC Systems. IEEE Access 5: 1649-1657 (2017) - [j73]Yu Zhao, Xi Zhang, Zhongshun Shi, Lei He:
Grain Price Forecasting Using a Hybrid Stochastic Method. Asia Pac. J. Oper. Res. 34(5): 1750020:1-1750020:24 (2017) - [j72]Linfeng Mo, Chang Wu, Lei He, GengSheng Chen:
Layout driven FPGA packing algorithm for performance optimization. IEICE Electron. Express 14(11): 20170419 (2017) - [c149]Juexiao Su, Lei He:
Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length. DAC 2017: 77:1-77:6 - [c148]Min Gao, Kun Wang, Lei He:
Probabilistic Model Checking for Green Energy Router System in Energy Internet. GLOBECOM 2017: 1-6 - 2016
- [j71]Jun Shi, Xiaoping Liu, Lei He, Mo Han, Qingzhong Li, Naitong Zhang:
Sampling and Reconstruction in Arbitrary Measurement and Approximation Spaces Associated With Linear Canonical Transform. IEEE Trans. Signal Process. 64(24): 6379-6391 (2016) - [c147]Juexiao Su, Tianheng Tu, Lei He:
A quantum annealing approach for boolean satisfiability problem. DAC 2016: 148:1-148:6 - [c146]Yunxuan Yu, Lei He:
FPGA Power Estimation Using Automatic Feature Selection (Abstract Only). FPGA 2016: 282 - [c145]Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He:
Wave digital filter based analog circuit emulation on FPGA. ISCAS 2016: 1286-1289 - [c144]Wei Wu, Srinivas Bodapati, Lei He:
Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage. ISPD 2016: 153-160 - [c143]Min Gao, Lei He, Rupak Majumdar, Zilong Wang:
LLSPLAT: Improving Concolic Testing by Bounded Model Checking. SCAM 2016: 127-136 - 2015
- [j70]Kun Wang, Zhiyou Ouyang, Rahul Krishnan, Lei Shu, Lei He:
A Game Theory-Based Energy Management System Using Price Elasticity for Smart Grids. IEEE Trans. Ind. Informatics 11(6): 1607-1616 (2015) - [c142]Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He:
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. ASP-DAC 2015: 556-561 - [c141]Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He:
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). FPGA 2015: 276 - [c140]Kun Wang, Yun Shao, Lei Shu, Yanfei Sun, Lei He:
An improved spray and wait algorithm based on RVNS in Delay Tolerant Mobile Sensor Networks. ICC 2015: 3552-3556 - [c139]Kun Wang, Guo Huang, Lei Shu, Chunsheng Zhu, Lei He:
A Social Awareness based Feedback Mechanism for delivery reliability in Delay Tolerant Networks. ICC 2015: 7007-7011 - 2014
- [j69]Fang Gong, Hao Yu, Yiyu Shi, Lei He:
Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges. IEEE Des. Test 31(4): 6-15 (2014) - [j68]Lerong Cheng, Wenyao Xu, Fengbo Ren, Fang Gong, Puneet Gupta, Lei He:
Statistical timing and power analysis of VLSI considering non-linear dependence. Integr. 47(4): 487-498 (2014) - [j67]Zhe Feng, Naifeng Jing, Lei He:
IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2225-2228 (2014) - [c138]Wei Wu, Fang Gong, GengSheng Chen, Lei He:
A fast and provably bounded failure analysis of memory circuits in high dimensions. ASP-DAC 2014: 424-429 - [c137]Chen Chen, Junzhou Huang, Lei He, Hongsheng Li:
Preconditioning for Accelerated Iteratively Reweighted Least Squares in Structured Sparsity Reconstruction. CVPR 2014: 2713-2720 - [c136]Wei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He:
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage. DAC 2014: 82:1-82:6 - [c135]Wei Wu, Xiang Li, Lei He, Dongxiao Zhang:
Accelerating the iterative linear solver for reservoir simulation on multicore architectures. ICPADS 2014: 265-272 - [i1]Chen Chen, Junzhou Huang, Lei He, Hongsheng Li:
Fast Iteratively Reweighted Least Squares Algorithms for Analysis-Based Sparsity Reconstruction. CoRR abs/1411.5057 (2014) - 2013
- [j66]Wei Wu, Fang Gong, Rahul Krishnan, Lei He, Hao Yu:
Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms. IEEE Des. Test 30(1): 26-35 (2013) - [j65]Chaofan Yu, Lingli Wang, Chun Zhang, Yu Hu, Lei He:
Fast Filter-Based Boolean Matchers. IEEE Embed. Syst. Lett. 5(4): 65-68 (2013) - [j64]Sina Basir-Kazeruni, Hao Yu, Fang Gong, Yu Hu, Chunchen Liu, Lei He:
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. Integr. 46(1): 22-32 (2013) - [j63]Hongsheng Li, Xiaolei Huang, Lei He:
Object Matching Using a Locally Affine Invariant and Linear Programming Techniques. IEEE Trans. Pattern Anal. Mach. Intell. 35(2): 411-424 (2013) - [j62]Fang Gong, Sina Basir-Kazeruni, Lei He, Hao Yu:
Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 24-33 (2013) - [j61]Wei Yao, Siming Pan, Brice Achkir, Jun Fan, Lei He:
Modeling and Application of Multi-Port TSV Networks in 3-D IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 487-496 (2013) - [c134]Ming-Chun Huang, Wenyao Xu, Jason J. Liu, Yi Su, Lei He, Majid Sarrafzadeh:
Inconspicuous Personal Computer Protection with Touch-Mouse. HCI (27) 2013: 29-38 - [c133]Rahul Krishnan, Wei Wu, Fang Gong, Lei He:
Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropy. ISQED 2013: 572-579 - 2012
- [j60]Fang Gong, Wenyao Xu, Jueh-Yu Lee, Lei He, Majid Sarrafzadeh:
NeuroGlasses: A Neural Sensing Healthcare System for 3-D Vision Technology. IEEE Trans. Inf. Technol. Biomed. 16(2): 198-204 (2012) - [j59]Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He:
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. ACM Trans. Design Autom. Electr. Syst. 17(1): 10:1-10:23 (2012) - [j58]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He:
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. 18(1): 13:1-13:18 (2012) - [j57]Lerong Cheng, Wenyao Xu, Fang Gong, Yan Lin, Ho-Yan Wong, Lei He:
Statistical Timing and Power Optimization of Architecture and Device for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 5(2): 9:1-9:19 (2012) - [j56]Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti:
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 89-97 (2012) - [j55]Lerong Cheng, Fang Gong, Wenyao Xu, Jinjun Xiong, Lei He, Majid Sarrafzadeh:
Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1383-1391 (2012) - [j54]Fang Gong, Hao Yu, Lingli Wang, Lei He:
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1729-1737 (2012) - [c132]Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He:
Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs. FPT 2012: 23-28 - [c131]Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei He:
A fast estimation of SRAM failure rate using probability collectives. ISPD 2012: 41-48 - [c130]Wenyao Xu, Ming-Chun Huang, Navid Amini, Jason J. Liu, Lei He, Majid Sarrafzadeh:
Smart insole: a wearable system for gait analysis. PETRA 2012: 18 - 2011
- [j53]Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao:
System-in-Package: Electrical and Layout Perspectives. Found. Trends Electron. Des. Autom. 4(4): 223-306 (2011) - [j52]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 388-401 (2011) - [j51]Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh:
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(6): 1372-1381 (2011) - [j50]Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He:
Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 508-512 (2011) - [c129]Fang Gong, Hao Yu, Lei He:
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials. DAC 2011: 298-303 - [c128]Naifeng Jing, Ju-Yueh Lee, Chun Zhang, Jiarong Tong, Zhigang Mao, Lei He:
Fault modeling and characteristics of SRAM-based FPGAs (abstract only). FPGA 2011: 279 - [c127]Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He:
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL 2011: 282-285 - [c126]Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He:
Acceleration of Multi-agent Simulation on FPGAs. FPL 2011: 470-473 - [c125]Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He:
IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. FPL 2011: 482-485 - [c124]Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He:
Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD 2011: 582-586 - [c123]Fang Gong, Hao Yu, Lei He:
Stochastic analog circuit behavior modeling by point estimation method. ISPD 2011: 175-182 - 2010
- [j49]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Accelerating Boolean Matching Using Bloom Filter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(10): 1775-1781 (2010) - [j48]Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng:
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1709-1722 (2010) - [j47]Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar:
Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 681-690 (2010) - [j46]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Effective congestion reduction for IC package substrate routing. ACM Trans. Design Autom. Electr. Syst. 15(3): 27:1-27:21 (2010) - [j45]Yiyu Shi, Lei He:
EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 108-118 (2010) - [j44]Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He, Sheldon X.-D. Tan:
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. IEEE Trans. Very Large Scale Integr. Syst. 18(10): 1399-1411 (2010) - [c122]Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li:
Fault-tolerant resynthesis with dual-output LUTs. ASP-DAC 2010: 325-330 - [c121]Lerong Cheng, Puneet Gupta, Lei He:
On confidence in characterization and application of variation models. ASP-DAC 2010: 751-756 - [c120]Hongsheng Li, Edward Kim, Xiaolei Huang, Lei He:
Object matching with a locally affine-invariant constraint. CVPR 2010: 1641-1648 - [c119]Fang Gong, Hao Yu, Yiyu Shi, Daesoo Kim, Junyan Ren, Lei He:
QuickYield: an efficient global-search based parametric yield estimation with performance constraints. DAC 2010: 392-397 - [c118]Manu Jose, Yu Hu, Rupak Majumdar, Lei He:
Rewiring for robustness. DAC 2010: 469-474 - [c117]Bingjun Xiao, Yiyu Shi, Lei He:
A universal state-of-charge algorithm for batteries. DAC 2010: 687-692 - [c116]Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. DATE 2010: 783-788 - [c115]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Building a faster boolean matcher using bloom filter. FPGA 2010: 185-188 - [c114]Ju-Yueh Lee, Zhe Feng, Lei He:
In-place decomposition for robustness in FPGA. ICCAD 2010: 143-148 - [c113]Yiyu Shi, Lei He:
Modeling and design for beyond-the-die power integrity. ICCAD 2010: 411-416 - [c112]Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong:
Engineering a scalable Boolean matching based on EDA SaaS 2.0. ICCAD 2010: 750-755
2000 – 2009
- 2009
- [j43]Hao Yu, Lei He, Mau-Chung Frank Chang:
Robust On-Chip Signaling by Staggered and Twisted Bundle. IEEE Des. Test Comput. 26(5): 92-104 (2009) - [j42]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 130-140 (2009) - [j41]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 207-216 (2009) - [j40]Yu Hu, Satyaki Das, Steven Trimberger, Lei He:
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 591-595 (2009) - [j39]Lerong Cheng, Puneet Gupta, Lei He:
Efficient Additive Statistical Leakage Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1777-1781 (2009) - [j38]Hao Yu, Joanna Ho, Lei He:
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Trans. Design Autom. Electr. Syst. 14(3): 41:1-41:31 (2009) - [c111]Yiyu Shi, Wei Yao, Jinjun Xiong, Lei He:
Incremental and on-demand random walk for iterative power distribution network analysis. ASP-DAC 2009: 185-190 - [c110]Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He:
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction. ASP-DAC 2009: 373-378 - [c109]Lerong Cheng, Puneet Gupta, Lei He:
Accounting for non-linear dependence using function driven component analysis. ASP-DAC 2009: 474-479 - [c108]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC 2009: 104-109 - [c107]Fang Gong, Hao Yu, Lei He:
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation. DAC 2009: 764-769 - [c106]Zhe Feng, Yu Hu, Lei He, Rupak Majumdar:
IPR: In-Place Reconfiguration for FPGA fault tolerance. ICCAD 2009: 105-108 - [c105]Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti:
Joint design-time and post-silicon optimization for digitally tuned analog circuits. ICCAD 2009: 725-730 - [c104]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Robi Dutta, Xianlong Hong:
Diffusion-driven congestion reduction for substrate topological routing. ISPD 2009: 175-180 - [c103]Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti, Yu Hu:
Worst case timing jitter and amplitude noise in differential signaling. ISQED 2009: 40-46 - [c102]Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. ISQED 2009: 702-707 - 2008
- [j37]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng, Lei He, Xianlong Hong:
Fashion: A Fast and Accurate Solution to Global Routing Problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 726-737 (2008) - [j36]Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1253-1263 (2008) - [j35]King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang:
Dual-Vdd Buffer Insertion for Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1498-1502 (2008) - [j34]Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1751-1760 (2008) - [j33]Yu Hu, Yan Lin, Lei He, Tim Tuan:
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ACM Trans. Design Autom. Electr. Syst. 13(2): 30:1-30:29 (2008) - [j32]Yan Lin, Lei He, Mike Hutton:
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 124-133 (2008) - [j31]Hao Yu, Yiyu Shi, Lei He, Tanay Karnik:
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1609-1619 (2008) - [c101]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Gaussian statistical timing analysis using second-order polynomial fitting. ASP-DAC 2008: 298-303 - [c100]Yiyu Shi, Lei He, Chuanjin Richard Shi:
Scalable Symbolic Model Order Reduction. BMAS 2008: 112-117 - [c99]Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
FPGA area reduction by multi-output function based sequential resynthesis. DAC 2008: 24-29 - [c98]Zhen Cao, Brian Foo, Lei He, Mihaela van der Schaar:
Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications. DAC 2008: 179-184 - [c97]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Topological routing to maximize routability for package substrate. DAC 2008: 566-569 - [c96]Lerong Cheng, Yan Lin, Lei He:
Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. FPGA 2008: 159-168 - [c95]Yu Hu, Zhe Feng, Lei He, Rupak Majumdar:
Robust FPGA resynthesis based on fault-tolerant Boolean matching. ICCAD 2008: 706-713 - 2007
- [j30]Yan Lin, Mike Hutton, Lei He:
Statistical placement for FPGAs considering. IET Comput. Digit. Tech. 1(4): 267-275 (2007) - [j29]Jinjun Xiong, Lei He:
Full-chip multilevel routing for power and signal integrity. Integr. 40(3): 226-234 (2007) - [j28]Jinjun Xiong, Vladimir Zolotov, Lei He:
Robust Extraction of Spatial Correlation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 619-631 (2007) - [j27]Jun Chen, Lei He:
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 734-738 (2007) - [j26]Jinjun Xiong, Lei He:
Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 739-742 (2007) - [j25]Fei Li, Yan Lin, Lei He:
Field Programmability of Supply Voltages for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 752-764 (2007) - [j24]Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 845-857 (2007) - [j23]Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1211-1221 (2007) - [j22]Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He:
TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1382-1392 (2007) - [j21]Yiyu Shi, Paul Mesa, Hao Yu, Lei He:
Circuit-simulated obstacle-aware Steiner routing. ACM Trans. Design Autom. Electr. Syst. 12(3): 28:1-28:18 (2007) - [j20]Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He:
Microarchitecture Configurations and Floorplanning Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 830-841 (2007) - [c94]Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong:
DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. ASP-DAC 2007: 256-261 - [c93]Lerong Cheng, Jinjun Xiong, Lei He:
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. DAC 2007: 250-255 - [c92]Hao Yu, Chunta Chu, Lei He:
Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design. DAC 2007: 618-621 - [c91]Yan Lin, Lei He:
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. DATE 2007: 636-641 - [c90]Yan Lin, Lei He:
Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. FPGA 2007: 80-88 - [c89]Yu Hu, Satyaki Das, Steven Trimberger, Lei He:
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. ICCAD 2007: 188-193 - [c88]Yan Lin, Lei He:
Device and architecture concurrent optimization for FPGA transient soft error rate. ICCAD 2007: 194-198 - [c87]Yu Hu, Victor Shih, Rupak Majumdar, Lei He:
Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. ICCAD 2007: 350-353 - [c86]Chunta Chu, Xinyi Zhang, Lei He, Tong Jing:
Temperature aware microprocessor floorplanning considering application dependent power load. ICCAD 2007: 586-589 - [c85]Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He:
Efficient decoupling capacitance budgeting considering operation and process variations. ICCAD 2007: 803-810 - [c84]Yiyu Shi, Lei He:
Empire: an efficient and compact multiple-parameterized model order reduction method. ISPD 2007: 51-58 - [c83]Hao Yu, Yu Hu, Chunchen Liu, Lei He:
Minimal skew clock embedding considering time variant temperature gradient. ISPD 2007: 173-180 - [c82]Yu Hu, King Ho Tam, Tong Jing, Lei He:
Fast dual-vdd buffering based on interconnect prediction and sampling. SLIP 2007: 95-102 - 2006
- [j19]Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He:
Wideband passive multiport model order reduction and realization of RLCM circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1496-1509 (2006) - [j18]Jun Chen, Lei He:
Modeling and synthesis of multiport transmission line for multichannel communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1664-1676 (2006) - [j17]Yan Lin, Lei He:
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2023-2034 (2006) - [c81]Jinjun Xiong, Yiu-Chung Wong, Egino Sarto, Lei He:
Constraint driven I/O planning and placement for chip-package co-design. ASP-DAC 2006: 207-212 - [c80]Yiyu Shi, Tong Jing, Lei He, Zhe Feng, Xianlong Hong:
CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. ASP-DAC 2006: 630-635 - [c79]Hao Yu, Yiyu Shi, Lei He:
Fast analysis of structured power grid by triangularization based structure preserving model order reduction. DAC 2006: 205-210 - [c78]Yiyu Shi, Paul Mesa, Hao Yu, Lei He:
Circuit simulation based obstacle-aware Steiner routing. DAC 2006: 385-388 - [c77]Yu Hu, Yan Lin, Lei He, Tim Tuan:
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. DAC 2006: 478-483 - [c76]Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton:
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. FPL 2006: 1-6 - [c75]Mike Hutton, Yan Lin, Lei He:
Placement and Timing for FPGAs Considering Variations. FPL 2006: 1-7 - [c74]Hao Yu, Yiyu Shi, Lei He, David Smart:
A fast block structure preserving model order reduction for inverse inductance circuits. ICCAD 2006: 7-12 - [c73]Hao Yu, Joanna Ho, Lei He:
Simultaneous power and thermal integrity driven via stapling in 3D ICs. ICCAD 2006: 802-808 - [c72]Hao Yu, Yiyu Shi, Lei He, Tanay Karnik:
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. ISLPED 2006: 156-161 - [c71]Yan Lin, Yu Hu, Lei He, Vijay Raghunat:
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. ISLPED 2006: 168-173 - [c70]Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik:
Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. ISLPED 2006: 326-329 - [c69]Jinjun Xiong, Vladimir Zolotov, Lei He:
Robust extraction of spatial correlation. ISPD 2006: 2-9 - [c68]Yiyu Shi, Hao Yu, Lei He:
SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance. ISPD 2006: 25-32 - [c67]Jun Chen, Lei He:
Noise driven in-package decoupling capacitor optimization for power integrity. ISPD 2006: 94-101 - [c66]Jinjun Xiong, Lei He:
Fast buffer insertion considering process variations. ISPD 2006: 128-135 - 2005
- [j16]Weiping Liao, Lei He:
Microarchitecture Level Interconnect Modeling Considering Layout Optimization. J. Low Power Electron. 1(3): 297-308 (2005) - [j15]Jun Chen, Lei He:
Piecewise linear model for transmission line with capacitive loading and ramp input. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 928-937 (2005) - [j14]Weiping Liao, Lei He, Kevin M. Lepak:
Temperature and supply Voltage aware performance and power modeling at microarchitecture level. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1042-1053 (2005) - [j13]Jun Chen, Lei He:
Worst case crosstalk noise for nonswitching victims in high-speed buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1275-1283 (2005) - [j12]Hao Yu, Lei He:
A provably passive and cost-efficient model for inductive interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1283-1294 (2005) - [j11]Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong:
Power modeling and characteristics of field programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1712-1724 (2005) - [j10]Jinjun Xiong, Lei He:
Extended global routing with RLC crosstalk constraints. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 319-329 (2005) - [j9]Yan Lin, Fei Li, Lei He:
Circuits and architectures for field programmable gate array with configurable supply voltage. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1035-1047 (2005) - [j8]Weiping Liao, Joseph M. Basile, Lei He:
Microarchitecture-level leakage reduction with data retention. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1324-1328 (2005) - [c65]Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan:
A wideband hierarchical circuit reduction for massively coupled interconnects. ASP-DAC 2005: 111-114 - [c64]Tong Jing, Ling Zhang, Jinghong Liang, Jingyu Xu, Xianlong Hong, Jinjun Xiong, Lei He:
A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem. ASP-DAC 2005: 115-120 - [c63]Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He:
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. ASP-DAC 2005: 224-229 - [c62]Yan Lin, Fei Li, Lei He:
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. ASP-DAC 2005: 645-650 - [c61]Jinjun Xiong, Lei He:
Probabilistic congestion model considering shielding for crosstalk reduction. ASP-DAC 2005: 739-742 - [c60]King Ho Tam, Lei He:
Power optimal dual-Vdd buffered tree considering buffer stations and blockages. DAC 2005: 497-502 - [c59]Yan Lin, Lei He:
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. DAC 2005: 720-725 - [c58]Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He:
Device and architecture co-optimization for FPGA power reduction. DAC 2005: 915-920 - [c57]Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak:
Scheduling of Soft Real-Time Systems for Context-Aware Applications. DATE 2005: 318-323 - [c56]Jinjun Xiong, King Ho Tam, Lei He:
Buffer Insertion Considering Process Variation. DATE 2005: 970-975 - [c55]Yan Lin, Fei Li, Lei He:
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. FPGA 2005: 199-207 - [c54]Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He:
FPGA device and architecture evaluation considering process variations. ICCAD 2005: 19-24 - [c53]Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He:
An efficient method for terminal reduction of interconnect circuits considering delay variations. ICCAD 2005: 821-826 - [c52]Hao Yu, Lei He:
A sparsified vector potential equivalent circuit model for massively coupled interconnects. ISCAS (1) 2005: 105-108 - [c51]Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton:
Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED 2005: 90 - [c50]Yu Ching Chang, King Ho Tam, Lei He:
Power-optimal repeater insertion considering Vdd and Vth as design freedoms. ISLPED 2005: 137-142 - [c49]Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation. ISPD 2005: 78-85 - [c48]Anirudh Devgan, Luca Daniel, Byron Krauter, Lei He:
Modeling and Design of Chip-Package Interface. ISQED 2005: 6 - [c47]Hao Yu, Lei He:
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. ISQED 2005: 682-687 - [c46]Lucanus J. Simonson, Lei He:
Micro-architecture Performance Estimation by Formula. SAMOS 2005: 192-201 - 2004
- [j7]Jinjun Xiong, Lei He:
Full-chip routing optimization with RLC crosstalk budgeting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 366-377 (2004) - [j6]Kevin M. Lepak, Min Xu, Jun Chen, Lei He:
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. ACM Trans. Design Autom. Electr. Syst. 9(3): 290-309 (2004) - [j5]Changbo Long, Lei He:
Distributed sleep transistor network for power reduction. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 937-946 (2004) - [c45]Jun Chen, Lei He:
Modeling of coplanar waveguide for buffered clock tree. ASP-DAC 2004: 367-372 - [c44]Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy:
High-level area and power-up current estimation considering rich cell library. ASP-DAC 2004: 899-904 - [c43]Lei He, Weiping Liao, Mircea R. Stan:
System level leakage reduction considering the interdependence of temperature and leakage. DAC 2004: 12-17 - [c42]Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He:
Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects. DAC 2004: 640-645 - [c41]Fei Li, Yan Lin, Lei He:
FPGA power reduction using configurable dual-Vdd. DAC 2004: 735-740 - [c40]Jinjun Xiong, Lei He:
Full-Chip Multilevel Routing for Power and Signal Integrity. DATE 2004: 1116-1123 - [c39]Fei Li, Yan Lin, Lei He, Jason Cong:
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA 2004: 42-50 - [c38]Deming Chen, Jason Cong, Fei Li, Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117 - [c37]Fei Li, Yan Lin, Lei He:
Vdd programmability to reduce FPGA interconnect power. ICCAD 2004: 760-765 - [c36]Ling Zhang, Tong Jing, Xianlong Hong, Jingyu Xu, Jinjun Xiong, Lei He:
Performance and RLC crosstalk driven global routing. ISCAS (5) 2004: 65-68 - [c35]Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong, Lei He, Jinjun Xiong:
Shielding area optimization under the solution of interconnect crosstalk. ISCAS (5) 2004: 297-300 - [c34]Changbo Long, Jinjun Xiong, Lei He:
On optimal physical synthesis of sleep transistors. ISPD 2004: 156-161 - [c33]Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He:
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction. ISQED 2004: 69-74 - 2003
- [c32]Jun Chen, Lei He:
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects. ASP-DAC 2003: 162-167 - [c31]Changbo Long, Lei He:
Distributed sleep transistor network for power reduction. DAC 2003: 181-186 - [c30]Hao Yu, Lei He:
Vector potential equivalent circuit based on PEEC inversion. DAC 2003: 718-723 - [c29]Fei Li, Deming Chen, Lei He, Jason Cong:
Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184 - [c28]Weiping Liao, Lei He:
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion. ICCAD 2003: 574-580 - [c27]Weiping Liao, Fei Li, Lei He:
Microarchitecture level power and thermal simulation considering temperature dependent leakage model. ISLPED 2003: 211-216 - [c26]Weiping Liao, Lei He:
Coupled Power and Thermal Simulation with Active Cooling. PACS 2003: 148-163 - [c25]Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy:
High Level Area and Current Estimation. PATMOS 2003: 259-268 - 2002
- [c24]James D. Z. Ma, Lei He:
Towards global routing with RLC crosstalk constraints. DAC 2002: 669-672 - [c23]Jun Chen, Lei He:
A decoupling method for analysis of coupled RLC interconnects. ACM Great Lakes Symposium on VLSI 2002: 41-46 - [c22]Jinjun Xiong, Jun Chen, James D. Z. Ma, Lei He:
Post global routing RLC crosstalk budgeting. ICCAD 2002: 504-509 - [c21]Weiping Liao, Joseph M. Basile, Lei He:
Leakage power modeling and reduction with data retention. ICCAD 2002: 714-719 - [c20]Jun Chen, Lei He:
Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 92-97 - [c19]Fei Li, Lei He, Kewal K. Saluja:
Estimation of Maximum Power-Up Current. ASP-DAC/VLSI Design 2002: 51- - 2001
- [j4]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1164-1169 (2001) - [c18]Liang Yin, Lei He:
An efficient analytical model of coupled on-chip RLC interconnects. ASP-DAC 2001: 385-390 - [c17]Kevin M. Lepak, Irwan Luwandi, Lei He:
Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint. DAC 2001: 199-202 - [c16]Min Xu, Lei He:
An efficient model for frequency-dependent on-chip inductance. ACM Great Lakes Symposium on VLSI 2001: 115-120 - [c15]James D. Z. Ma, Lei He:
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering. ICCAD 2001: 327-332 - [c14]James D. Z. Ma, Arvind Parihar, Lei He:
Pre-routing Estimation of Shielding for RLC Signal Integrity. ICCD 2001: 553-556 - [c13]Fei Li, Lei He:
Maximum current estimation considering power gating. ISPD 2001: 106-111 - [c12]Zhenyu Tang, Lei He, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa:
Instruction Prediction for Step Power Reduction. ISQED 2001: 211-216 - [c11]James D. Z. Ma, Lei He:
Simultaneous signal and power routing under K model. SLIP 2001: 175-182 - 2000
- [c10]Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He:
Clocktree RLC Extraction with Efficient Inductance Modeling. DATE 2000: 522-526 - [c9]Lei He, Kevin M. Lepak:
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization. ISPD 2000: 55-60 - [c8]Zhenyu Tang, Norman Chang, Shen Lin, Weize Xie, O. Sam Nakagawa, Lei He:
Ramp Up/Down Functional Unit to Reduce Step Power. PACS 2000: 13-24
1990 – 1999
- 1999
- [j3]Jason Cong, Lei He:
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 406-420 (1999) - [c7]Lei He, Norman Chang, Shen Lin, O. Sam Nakagawa:
An efficient inductance modeling for on-chip interconnects. CICC 1999: 457-460 - 1998
- [c6]Jason Cong, Lei He:
An efficient technique for device and interconnect optimization in deep submicron designs. ISPD 1998: 45-51 - 1997
- [c5]Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen:
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC 1997: 627-632 - [c4]Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo:
Interconnect design for deep submicron ICs. ICCAD 1997: 478-485 - [c3]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633 - 1996
- [j2]Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden:
Performance optimization of VLSI interconnect layout. Integr. 21(1-2): 1-94 (1996) - [j1]Jason Cong, Lei He:
Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Autom. Electr. Syst. 1(4): 478-511 (1996) - [c2]Jason Cong, Lei He:
An efficient approach to simultaneous transistor and interconnect sizing. ICCAD 1996: 181-186 - 1995
- [c1]Jason Cong, Lei He:
Optimal wiresizing for interconnects with multiple sources. ICCAD 1995: 568-574
Coauthor Index
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