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ORCIDVTS 2006: Berkeley, CA, USA
- 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA. IEEE Computer Society 2006, ISBN 0-7695-2514-8
Introduction
- Forward.
- Organizing Committee.
- Steering Committee.
- Program Committee.
- Reviewers.
- Acknowledgments.
- Test Technology Technical Council (TTTC).
- Test Technology Educational Program (TTEP) Tutorials.
- Awards.
Session 1A: Delay Testing I
- Xijiang Lin, Janusz Rajski:
The Impacts of Untestable Defects on Transition Fault Testing. 2-7 - Kun Young Chung, Sandeep K. Gupta:
Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. 8-15 - Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty:
Path Delay Fault Simulation on Large Industrial Designs. 16-23
Session 1B: High Speed Interconnect Test
- Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka
, Jacob A. Abraham:
A Scheme for On-Chip Timing Characterization. 24-29 - Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh:
BIST for Network-on-Chip Interconnect Infrastructures. 30-35 - Vishal Suthar, Shantanu Dutt:
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. 36-43
Session 1C - IP Session: Reliability Screening Methods for High-Performance Processors in Advanced Technologies
- Phil Nigh:
Session Abstract. 44
Session 2A: Heat and Power Issues in Test
- Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan:
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. 46-51 - Minsik Cho, David Z. Pan:
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. 52-57 - Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. 58-65
Session 2B: Test Quality
- Ruifeng Guo, Subhasish Mitra, M. Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman:
Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. 66-71 - Avijit Dutta, Nur A. Touba:
Iterative OPDD Based Signal Probability Calculation. 72-77 - Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty:
Silicon Evaluation of Logic Proximity Bridge Patterns. 78-85
Session 2C - IP Session: Scan Compression: Techniques, Tradeoffs and Entitlement
- Rubin A. Parekhji:
Session Abstract. 86-87
Session 3A: IP Protection and Interconnect Testing
- Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram:
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. 88-93 - Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic:
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. 94-99 - Khadija Jirari Stewart, Spyros Tragoudas:
Interconnect Testing for Networks on Chips. 100-107
Session 3B: Flash and Memory Testing
- Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
An Overview of Failure Mechanisms in Embedded Flash Memories. 108-113 - Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu:
A Built-In Self-Repair Scheme for NOR-Type Flash Memory. 114-119 - Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian:
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories. 120-127
Session 3C - IP Session: Nanometer IC Testing: Perspective from Foundries
- Cheng-Wen Wu:
Session Abstract. 128-129
Session 4A: Yield Analysis
- Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
An Error-Oriented Test Methodology to Improve Yield with Error-Tolerance. 130-135 - Rasit Onur Topaloglu:
Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations. 136-142 - Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara:
BIST Pretest of ICs: Risks and Benefits. 142-149
Session 4B - New Topic Session: Emerging Nanoelectronic Devices for High-Speed, Low-Power Applications
- Bernard Courtois:
Session Abstract. 150-151
Session 4C - IP Session: TRP in Action: Embedded Instrumentation in FPGAs
- Ajay Khoche:
Session Abstract. 152-153
Session 5A: - Special Session: The Future of DFT Sector: Point Tools or Integrated Solutions
- Yervant Zorian, Dennis Wassung:
Session Abstract. 154-155
Session 5B - Special Session: Elevator Talks
- Erik Chmelar, Edward J. McCluskey:
Session Abstract. 156-157
Session 5C - Embedded Tutorial: Functional ATPG
- Praveen Parvathala:
Session Abstract. 158-159
Session 6A: Test Generation and Test Flows
- Vlado Vorisek, Bruce Swanson, Kun-Han Tsai, Dhiraj Goswami:
Improved Handling of False and Multicycle Paths in ATPG. 160-165 - Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
On the Automation of the Test Flow of Complex SoCs. 166-171 - Giuseppe Di Guglielmo, Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
Improving Gate-Level ATPG by Traversing Concurrent EFSMs. 172-179
Session 6B: IDDQ, MEMS, and Wireless Testing
- Ashutosh Sharma, Anura P. Jayasumana, Yashwant K. Malaiya:
X-IDDQ: A Novel Defect Detection Technique Using IDDQ Data. 180-185 - Rong Zhang, Zeljko Zilic, Katarzyna Radecka:
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. 186-191 - Vishwanath Natarajan, Soumendu Bhattacharya, Abhijit Chatterjee:
Alternate Electrical Tests for Extracting Mechanical Parameters of MEMS Accelerometer Sensors. 192-199
Session 6C - IP Session: Test Strategies of Leading Edge SoCs
- Kazumi Hatayama:
Session Abstract. 200-201
Session 7A: Designing Robust CMOS and Nanoelectronics
- Quming Zhou, Mihir R. Choudhury, Kartik Mohanram:
Design Optimization for Robustness to Single Event Upsets. 202-207 - Maryam Ashouei, Soumendu Bhattacharya, Abhijit Chatterjee:
Design of Soft Error Resilient Linear Digital Filters Using Checksum-Based Probabilistic Error Correction. 208-213 - Wenjing Rao, Alex Orailoglu, Ramesh Karri:
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance. 214-221
Session 7B: RF Testing
- Ganesh Srinivasan, Abhijit Chatterjee, Friedrich Taenzler:
Alternate Loop-Back Diagnostic Tests for Wafer-Level Diagnosis of Modern Wireless Transceivers using Spectral Signatures. 222-227 - Qi Wang, Mani Soma:
RF Front-end System Gain and Linearity Built-in Test. 228-233 - Hsieh-Hung Hsieh, Liang-Hung Lu:
Integrated CMOS Power Sensors for RF BIST Applications. 234-239
Session 7C - IP Sessin: High Test Parallelism, Throughput and Quality at a Low Cost: Which Test Cells and Which Partitioning of Test Resources Can Enable All This?
- Davide Appello:
Session Abstract. 240-241
Session 8A: Test Size Reductions
- Wojciech Rajski, Janusz Rajski:
Modular Compactor of Test Responses. 242-251 - Jinkyu Lee, Nur A. Touba:
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding. 252-257 - Vishnu C. Vimjam, Michael S. Hsiao:
Efficient Fault Collapsing via Generalized Dominance Relations. 258-265
Session 8B: Transistor Level Diagnosis
- Xinyue Fan, Will R. Moore, Camelia Hora, Mario Konijnenburg, Guido Gronthoud:
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. 266-271 - Fang Liu, Plamen K. Nikolov, Sule Ozev:
Parametric Fault Diagnosis for Analog Circuits Using a Bayesian Framework. 272-277 - Mingjing Chen, Hosam Haggag, Alex Orailoglu:
Decision Tree Based Mismatch Diagnosis in Analog Circuits. 278-285
Session 8C - IP Session: Soft Error Impact on Modern Systems
- Michael Nicolaidis:
Session Abstract. 286-287
Session 9A - Panel Session: Real-Time Volume Diagnostics: Requirements and Challenges
- Ajay Khoche, Peter Muhmenthaler:
Session Abstract. 288-289
Session 9B - Special Sesion: Doctoral Thesis Award
- Andreas G. Veneris, Yiorgos Makris:
Session Abstract. 290-291
Session 9C - Panel Session: Three Questions to Oracle
- Kee Sup Kim, Mohammad Tehranipoor:
Session Abstract. 292-293
Session 10A: Delay Testing II
- Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. 294-299 - Huawei Li, Pei-Fu Shen, Xiaowei Li:
Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. 300-305 - Jais Abraham, Uday Goel, Arun Kumar:
Multi-Cycle Sensitizable Transition Delay Faults. 306-313
Session 10B: Analog Test
- Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro:
A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters. 314-319 - Sai Raghuram Durbha, Amit Laknaur, Haibo Wang:
Investigating the Efficiency of Integrator-Based Capacitor Array Testing Techniques. 320-325 - Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell:
Functional Test of Field Programmable Analog Arrays. 326-333
Session 10C - IP Session: System-in-Package Design and Test Practices
- Yervant Zorian, Bruce C. Kim:
Session Abstract. 334-335
Session 11A: Delay Testing III
- Richard Putman, Rahul Gawde:
Enhanced Timing-Based Transition Delay Testing for Small Delay Defects. 336-342 - Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. 343-348 - Adit D. Singh, Gefu Xu:
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. 349-357
Session 11B: Nanoscale Testing
- Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura:
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. 358-363 - Jason G. Brown, R. D. (Shawn) Blanton:
Exploiting Regularity for Inductive Fault Analysis. 364-369 - Reza M. Rad, Mohammad Tehranipoor:
SCT: An Approach For Testing and Configuring Nanoscale Devices. 370-377
Session 11C - IP Session: Impact of Variations on Designs and Test
- James W. Tschanz:
Session Abstract. 378-379
Session 12A: Scan Based Diagnosis
- Bharath Seshadri, Xiaoming Yu, Srikanth Venkataraman:
Accelerating Diagnostic Fault Simulation Using Z-diagnosis and Concurrent Equivalence Identification. 380-385 - Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. 386-391 - Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy:
Dominance Based Analysis for Large Volume Production Fail Diagnosis. 392-399
Session 12B: Mixed Signal Test
- C.-Y. Kuo, J.-L. Huang:
A Period Tracking Based On-Chip Sinusoidal Jitter Extraction Technique. 400-405 - Haralampos-G. D. Stratigopoulos, Yiorgos Makris:
Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing. 406-411 - Hongjoong Shin, Byoungho Kim, Jacob A. Abraham:
Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. 412-419
Session 12C - IP Session: Making the (Yield) Difference: DFY/DFM
- R. Chandramouli:
Session Abstract. 420-421
Session 13A: Embedded Tutorial: Silicon Debug Challenges for Nanometer Designs
- Rajesh Galivanche, Bob Gottlieb:
Session Abstract. 422-423
Session 13B - Hot Topic Session: Signal Integrity: How Can It be Designed into Multiprocessor Platforms, Systems On-Chip, and Systems in-Package?
- André Ivanov:
Session Abstract. 424-425
Session 13C - Panel Session: Changing Role of Test: Is ATE Ready?
- Ajay Khoche, Mike Rodgers, Pete O'Neil:
Session Abstract. 426
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