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ORCID40th DAC 2003: Anaheim, CA, USA
- Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003. ACM 2003, ISBN 1-58113-688-9
Real challenges and solutions for validating system-on-chip
- Thomas Schubert:
High level formal verification of next-generation microprocessors. 1-6 - Yves Mathys, André Chátelain:
Verification strategy for integration 3G baseband SoC. 7-10 - Klaus-Dieter Schubert:
Improvements in functional simulation addressing challenges in large, distributed industry projects. 11-14
Reshaping EDA for power
- Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang:
Reshaping EDA for power. 15
Design for manufacturability and global routing
- Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. 16-21 - Yu Chen, Puneet Gupta, Andrew B. Kahng:
Performance-impact limited area fill synthesis. 22-27 - Raia Hadsell, Patrick H. Madden:
Improved global routing through congestion estimation. 28-31 - Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis:
Microarchitecture evaluation with physical planning. 32-35
Design analysis techniques
- Luca Benini, Alberto Macii
, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino:
Energy-aware design techniques for differential power analysis protection. 36-41 - Franco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino, Stefano Martini, Fabio Ricciato:
A timing-accurate modeling and simulation environment for networked embedded systems. 42-47 - Robertas Damasevicius, Giedrius Majauskas, Vytautas Stuikys:
Application of design patterns for hardware design. 48-53
Embedded hardware design case studies
- George Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos:
A fully-programmable memory management system optimizing queue handling at multi-gigabit rates. 54-59 - David D. Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede:
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system. 60-65 - Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak:
Design techniques for sensor appliances: foundations and light compass case study. 66-71
Emerging design and tool challenges in RF and wireless applications
- Uri Barkai:
Seamless multi-radio integration challenges. 72 - Pieter W. Hooijmans:
RF front end application and technology trends. 73-78 - Jan Craninckx, Stéphane Donnay:
4G terminals: how are we going to design them? 79-84 - David E. Root, John Wood, Nick Tufillaro:
New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurements. 85-90
COT-customer owned trouble
- Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta:
COT - customer owned trouble. 91-92 - Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar:
Random walks in a supply network. 93-98 - Dionysios Kouroussis, Farid N. Najm:
A static pattern-independent technique for power grid voltage integrity verification. 99-104 - Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng:
Power network analysis using an adaptive algebraic multigrid approach. 105-108 - Haihua Su, Emrah Acar, Sani R. Nassif:
Power grid reduction based on algebraic multigrid principles. 109-112 - Kai Wang, Malgorzata Marek-Sadowska:
On-chip power supply network optimization using multigrid-based technique. 113-118
Low-power embedded system design
- Dexin Li, Qiang Xie, Pai H. Chou:
Scalable modeling and optimization of mode transitions based on decoupled power management architecture. 119-124 - Woo-Cheol Kwon, Taewhan Kim:
Optimal voltage allocation techniques for dynamically variable voltage processors. 125-130 - Shaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya:
Energy reduction techniques for multimedia applications with tolerance to deadline misses. 131-136 - Anand Ramachandran, Margarida F. Jacome:
Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing. 137-142
Cyclic and non-cyclic combinational circuit synthesis
- Alan Mishchenko, Xinning Wang, Timothy Kam:
A new enhanced constructive decomposition and mapping algorithm. 143-148 - Alan Mishchenko, Tsutomu Sasao:
Large-scale SOP minimization using decomposition and functional properties. 149-154 - Yunjian Jiang, Slobodan Matic, Robert K. Brayton:
Generalized cofactoring for logic function evaluation. 155-158 - Stephen A. Edwards:
Making cyclic circuits acyclic. 159-162 - Marc D. Riedel, Jehoshua Bruck:
The synthesis of cyclic combinational circuits. 163-168
Managing leakage power
- Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy:
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. 169-174 - Dongwoo Lee, Wesley Kwong, David T. Blaauw, Dennis Sylvester:
Analysis and minimization techniques for total leakage considering gate oxide leakage. 175-180 - Changbo Long, Lei He:
Distributed sleep transistor network for power reduction. 181-186 - Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
Implications of technology scaling on leakage reduction techniques. 187-190 - Dongwoo Lee, David T. Blaauw:
Static leakage reduction through simultaneous threshold voltage and state assignment. 191-194
Emerging markets: design goes global
- Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei:
Emerging markets: design goes global. 195 - Giancarlo Beraudo, John Lillis:
Timing optimization of FPGA placements by logic replication. 196-201 - Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Delay budgeting in sequential circuit with application on FPGA placement. 202-207 - Jason Cong, Xin Yuan:
Multilevel global placement with retiming. 208-213 - Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin:
Force directed mongrel with physical net constraints. 214-219
Model order reduction
- Zhanhai Qin, Chung-Kuan Cheng:
Realizable parasitic reduction using generalized Y-Delta transformation. 220-225 - Chirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail:
Realizable RLCK circuit crunching. 226-231 - Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail:
Efficient model order reduction including skin effect. 232-237 - Emad Gad, Michel S. Nakhla:
Model order reduction of nonuniform transmission lines using integrated congruence transform. 238-243
Issues in partitioning & design space epolartion for codesign
- Radoslaw Szymanek, Krzysztof Kuchcinski:
Partial task assignment of task graphs under heterogeneous resource constraints. 244-249 - Greg Stitt, Roman L. Lysecky, Frank Vahid:
Dynamic hardware/software partitioning: a first approach. 250-255 - Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic application-specific instruction-set extensions under microarchitectural constraints. 256-261 - Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models. 262-267
Nano technology: design implications and CAD challenges
- Gary H. Bernstein:
Quantum-dot cellular automata: computing by field polarization. 268-273 - Christoph Wasshuber:
Recent advances and future prospects in single-electronics. 274-275 - Islamshah Amlani, Ruth Zhang, John Tresek, Larry Nagahara, Raymond K. Tsui:
Manipulation and characterization of molecular scale components. 276-277
Mixed signals on mixed-signal: the right next technology
- Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Meng, Reza Rofougaran, James Spoto:
Mixed signals on mixed-signal: the right next technology. 278-279
Simulation coverage and generation for verification
- Alon Gluska:
Coverage-oriented verification of banias. 280-285 - Shai Fine, Avi Ziv:
Coverage directed test generation for functional verification using bayesian networks. 286-291 - Nikhil Jayakumar, Mitra Purandare, Fabio Somenzi:
Dos and don'ts of CTL state coverage estimation. 292-295 - Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Constraint synthesis for environment modeling in functional verification. 296-299
Tool support for architectural decisions in embedded systems
- Samar Abdi, Dongwan Shin, Daniel Gajski:
Automatic communication refinement for system level design. 300-305 - Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass:
CoCo: a hardware/software platform for rapid prototyping of code compression technologies. 306-311 - Trevor Meyerowitz, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli:
A tool for describing and evaluating hierarchical real-time bus scheduling policies. 312-317
New topics in logic synthesis
- D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck:
A transformation based algorithm for reversible logic synthesis. 318-323 - Stephen S. Bullock, Igor L. Markov:
An arbitrary twoqubit computation In 23 elementary gates or less. 324-329 - Arash Saifhashemi, Hossein Pedram:
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. 330-333 - Roman L. Lysecky, Frank Vahid:
On-chip logic minimization. 334-337
Coping with variability: the end of deterministic design
- Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De:
Parameter variations and impact on circuits and microarchitecture. 338-342 - Chandu Visweswariah:
Death, taxes and failing chips. 343-347 - Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
Computation and Refinement of Statistical Bounds on Circuit Delay. 348-353
Fast, cheap and under control: the next implementation fabric
- Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi:
Fast, cheap and under control: the next implementation fabric. 354-355
Testbench, verification and debugging: practical considerations
- Serdar Tasiran, Yuan Yu, Brannon Batson:
Using a formal specification and a model checker to monitor and direct simulation. 356-361 - Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai:
Advanced techniques for RTL debugging. 362-367 - Edmund M. Clarke, Daniel Kroening, Karen Yorav:
Behavioral consistency of C and verilog programs using bounded model checking. 368-371 - Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker:
Re-use-centric architecture for a fully accelerated testbench environment. 372-375
Delay and noise modeling in the nanometer regime
- Kanak Agarwal, Dennis Sylvester, David T. Blaauw:
An effective capacitance based driver output model for on-chip RLC interconnects. 376-381 - Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan:
Delay and slew metrics using the lognormal distribution. 382-385 - John F. Croix, D. F. Wong:
Blade and razor: cell and interconnect delay analysis using current-based models. 386-389 - Bhavana Thudi, David T. Blaauw:
Non-iterative switching window computation for delay-noise. 390-395
Modeling issues in the design of embedded systems
- Jeffry T. Russell, Margarida F. Jacome:
Architecture-level performance evaluation of component-based embedded systems. 396-401 - Andy D. Pimentel, Cagkan Erbas:
An IDF-based trace transformation method for communication refinement. 402-407 - JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas:
Schedulers as model-based design elements in programmable heterogeneous multiprocessors. 408-411 - M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy:
A complexity effective communication model for behavioral modeling of signal processing applications. 412-415
How application/technology evolutions will shape classical EDA?
- Gregory S. Spirakis:
Leading-edge and future design challenges - is the classical EDA ready? 416 - Akira Matsuzawa:
How to make efficient communication, collaboration, and optimization from system to chip. 417-418 - Philippe Magarshack, Pierre G. Paulin:
System-on-chip beyond the nanometer wall. 419-424
SAT and BDD algorithms for verification tools
- Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Bryant:
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions. 425-430 - Amit Goel, Gagan Hasteer, Randal E. Bryant:
Symbolic representation with ordered function templates. 431-435 - Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna:
A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. 436-441 - Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain:
Solving the latch mapping problem in an industrial setting. 442-447
Elements of functional and performance analysis
- Giovanni Agosta, Francesco Bruschi, Donatella Sciuto:
Static analysis of transaction-level models. 448-453 - Marek Jersak, Rolf Ernst:
Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervals. 454-459 - Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Automatic trace analysis for logic of constraints. 460-465 - Xianfeng Li, Tulika Mitra, Abhik Roychoudhury:
Accurate timing analysis by modeling caches, speculation and their interaction. 466-471
Nonlinear model order reduction
- Peng Li, Lawrence T. Pileggi:
NORM: compact model order reduction of weakly nonlinear systems. 472-477 - Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi:
Analog and RF circuit macromodels for system-level analysis. 478-483 - Ning Dong, Jaijeet S. Roychowdhury:
Piecewise polynomial nonlinear model reduction. 484-489 - Dmitry Vasilyev, Michal Rewienski, Jacob White:
A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS. 490-495
Novel techniques in high-level synthesis
- Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen:
Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. 496-501 - Manish Amde, Ivan Blunno, Christos P. Sotiriou:
Automating the design of an asynchronous DLX microprocessor. 502-507 - Catherine G. Wong, Alain J. Martin:
High-level synthesis of asynchronous systems by data-driven decomposition. 508-513 - Byoungro So, Pedro C. Diniz, Mary W. Hall:
Using estimates from behavioral synthesis tools in compiler-directed design space exploration. 514-519
Mixed-signal design and simulation
- Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown:
A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. 520-525 - Charlotte Y. Lau, Michael H. Perrott:
Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm. 526-531 - Payam Heydari:
Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators. 532-537 - Vinita Vasudevan, M. Ramakrishna:
Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time technique. 538-541 - Alicia Manthe, Zhao Li, Chuanjin Richard Shi:
Symbolic analysis of analog circuits with hard nonlinearity. 542-545
Nanometer design: place your bets
- Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf:
Nanometer design: place your bets. 546-547
Novel self-test methods
- Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey:
A scalable software-based self-test methodology for programmable processors. 548-553 - Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
A scan BIST generation method using a markov source and partial bit-fixing. 554-559 - Ahmad A. Al-Yamani, Edward J. McCluskey:
Seed encoding with LFSRs and cellular automata. 560-565 - Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin:
Efficient compression and application of deterministic patterns in a logic BIST architecture. 566-569 - Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Ultimate low cost analog BIST. 570-573
Technology mapping, buffering, and bus design
- Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska:
Gain-based technology mapping for discrete-size cell libraries. 574-579 - Weiping Shi, Zhuo Li:
An O(nlogn) time algorithm for optimal buffer insertion. 580-585 - Maged Ghoneima, Yehea I. Ismail:
Optimum positioning of interleaved repeaters In bidirectional buses. 586-591 - Jihong Ren, Mark R. Greenstreet:
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. 592-597
Compilation techniques for reconfigurable devices
- Pongstorn Maidee, Cristinel Ababei, Kia Bazargan:
Fast timing-driven partitioning-based placement for island style FPGAs. 598-603 - Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, Eren Kursun:
Global resource sharing for synthesis of control data flow graphs on FPGAs. 604-609 - Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz:
Compiler-generated communication for pipelined FPGA applications. 610-615 - Adam Kaplan, Philip Brisk, Ryan Kastner:
Data communication estimation and reduction for reconfigurable systems. 616-621
Architectural power estimation and optimization
- Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii:
Clock-tree power optimization based on RTL clock-gating. 622-627