default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDEarl E. Swartzlander Jr.
Person information
- affiliation: University of Texas at Austin, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
[c134]Trenton J. Grale, Earl E. Swartzlander Jr.:
Improved Montgomery Multiplication. ARITH 2023: 60-67- 2022
- [c133]Pragnesh Patel, Aman Arora
, Earl E. Swartzlander Jr., Lizy K. John:
LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning. ISQED 2022: 1-7 - 2020
- [c132]Stafford Hutchins, Earl E. Swartzlander Jr.:
A Bfloat16 Fused Multiplier-Adder. UEMCON 2020: 52-55
2010 – 2019
- 2019
- [j90]Weiqiang Liu, Tian Cao, Peipei Yin, Yuying Zhu, Chenghua Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi:
Design and Analysis of Approximate Redundant Binary Multipliers. IEEE Trans. Computers 68(6): 804-819 (2019) - [c131]Alexander J. Groszewski, Earl E. Swartzlander Jr.:
A Variable-Latency Architecture for Accelerating Deterministic Approaches to Stochastic Computing. ACSSC 2019: 608-613 - [c130]Trenton J. Grale, Earl E. Swartzlander Jr.:
Parallel GF(2n) Modular Squarers. MWSCAS 2019: 872-875 - [p5]K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr.:
Memristor-Based Addition and Multiplication. Handbook of Memristor Networks 2019: 1123-1136 - 2018
- [j89]Lizy K. John, Earl E. Swartzlander Jr.:
Memristor-Based Computing. IEEE Micro 38(5): 5-6 (2018) - [j88]Weiqiang Liu, Faqiang Mei, Chenghua Wang, Máire O'Neill, Earl E. Swartzlander Jr.:
Data Compression Device Based on Modified LZ4 Algorithm. IEEE Trans. Consumer Electron. 64(1): 110-117 (2018) - [j87]Xiao-Ping Cui, Weiqiang Liu, Shumin Wang, Earl E. Swartzlander Jr., Fabrizio Lombardi:
Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders. J. Signal Process. Syst. 90(3): 409-419 (2018) - [j86]Peipei Yin, Chenghua Wang, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi:
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications. J. Signal Process. Syst. 90(4): 641-654 (2018) - [c129]Nagaraja Revanna, Earl E. Swartzlander Jr.:
Memristor Adder Design. MWSCAS 2018: 314-317 - 2017
- [j85]Xiao-Ping Cui, Wenwen Dong, Weiqiang Liu, Earl E. Swartzlander Jr., Fabrizio Lombardi:
High Performance Parallel Decimal Multipliers Using Hybrid BCD Codes. IEEE Trans. Computers 66(12): 1994-2004 (2017) - [j84]Lauren Guckert, Earl E. Swartzlander Jr.:
MAD Gates - Memristor Logic Design Using Driver Circuitry. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 171-175 (2017) - [j83]Lauren Guckert, Earl E. Swartzlander Jr.:
Optimized Memristor-Based Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(2): 373-385 (2017) - [j82]Weiqiang Liu, Earl E. Swartzlander Jr., Máire O'Neill:
Guest Editorial: Introduction to the Special Issue on Emerging Technologies and Designs for Application-Specific Computing. IEEE Trans. Emerg. Top. Comput. 5(2): 148-150 (2017) - [c128]Nagaraja Revanna, Lauren Guckert, Earl E. Swartzlander Jr.:
The future of computing - Arithmetic circuits implemented with memristors. ACSSC 2017: 745-749 - [c127]Trenton J. Grale, Earl E. Swartzlander Jr.:
Parallel GF(2n) multipliers. ACSSC 2017: 1029-1033 - [c126]Lauren Guckert, Earl E. Swartzlander Jr.:
Dadda Multiplier designs using memristors. ICICDT 2017: 1-4 - 2016
- [j81]Xiao-Ping Cui, Weiqiang Liu, Chen Xin, Earl E. Swartzlander Jr., Fabrizio Lombardi:
A Modified Partial Product Generator for Redundant Binary Multipliers. IEEE Trans. Computers 65(4): 1165-1171 (2016) - [j80]Jongwook Sohn, Earl E. Swartzlander Jr.:
A Fused Floating-Point Four-Term Dot Product Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(3): 370-378 (2016) - [c125]Nagaraja Revanna, Earl E. Swartzlander Jr.:
Memristor based adder circuit design. ACSSC 2016: 162-166 - [c124]Lauren Guckert, Earl E. Swartzlander Jr.:
Optimized memristor-based ripple carry adders. ACSSC 2016: 1575-1579 - [c123]Nagaraja Revanna, Earl E. Swartzlander Jr.:
Arithmetic circuit design with memristor based high fan-out logic gates. UEMCON 2016: 1-6 - 2015
- [j79]Weiqiang Liu, Earl E. Swartzlander Jr.:
Design of 3-D quantum-dot cellular automata adders. IEICE Electron. Express 12(6): 20150195 (2015) - [c122]Robert J. Ascott, Earl E. Swartzlander Jr.:
Extreme multi-core, multi-network Java DataFlow Machine (JavaFlow). ACSSC 2015: 182-185 - [c121]Mike O'Connor, Earl E. Swartzlander Jr.:
Exploiting asymmetry in Booth-encoded multipliers for reduced energy multiplication. ACSSC 2015: 722-726 - [c120]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Low-Cost Duplicate Multiplication. ARITH 2015: 2-9 - 2014
- [j78]Inwook Kong, Seong-Wan Kim, Earl E. Swartzlander Jr.:
Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata. IEEE Trans. Computers 63(10): 2620-2625 (2014) - [j77]Jongwook Sohn, Earl E. Swartzlander Jr.:
A Fused Floating-Point Three-Term Adder. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2842-2850 (2014) - [c119]Kihwan Jun, Earl E. Swartzlander Jr.:
Improved non-restoring square root algorithm with dual path calculation. ACSSC 2014: 1243-1246 - [c118]Divya Mahajan, Matheen Musaddiq, Earl E. Swartzlander Jr.:
Memristor based adders. ACSSC 2014: 1256-1260 - [p4]Earl E. Swartzlander Jr.:
High-Speed Computer Arithmetic. Computing Handbook, 3rd ed. (1) 2014: 20: 1-28 - [p3]Weiqiang Liu, Saket Srivastava, Máire O'Neill, Earl E. Swartzlander Jr.:
Security Issues in QCA Circuit Design - Power Analysis Attacks. Field-Coupled Nanocomputing 2014: 194-222 - 2013
- [j76]Earl E. Swartzlander Jr.:
STARS: Electronic Calculators: Desktop to Pocket. Proc. IEEE 101(12): 2558-2562 (2013) - [j75]Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.:
QCA Systolic Array Design. IEEE Trans. Computers 62(3): 548-560 (2013) - [j74]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Structure-Aware Placement Techniques for Designs With Datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 228-241 (2013) - [c117]Wesley Chu, Ali I. Unwala, Pohan Wu, Earl E. Swartzlander Jr.:
Implementation of a high speed multiplier using carry lookahead adders. ACSSC 2013: 400-404 - [c116]Michael B. Sullivan, Earl E. Swartzlander Jr.:
On separable error detection for addition. ACSSC 2013: 2181-2186 - [c115]Jongwook Sohn, Earl E. Swartzlander Jr.:
Improved Architectures for a Floating-Point Fused Dot Product Unit. IEEE Symposium on Computer Arithmetic 2013: 41-48 - [c114]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Truncated Logarithmic Approximation. IEEE Symposium on Computer Arithmetic 2013: 191-198 - [c113]Jae Hong Min, Earl E. Swartzlander Jr.:
Fused floating-point two-term sum-of-squares unit. ASAP 2013: 147-152 - [c112]Hani H. Saleh, Baker S. Mohammad, Earl E. Swartzlander Jr.:
The optimum Booth radix for low power integer multipliers. IDT 2013: 1-4 - [c111]Weiqiang Liu, Saket Srivastava, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
Power analysis attack of QCA circuits: A case study of the Serpent cipher. ISCAS 2013: 2075-2078 - [c110]Kihwan Jun, Earl E. Swartzlander Jr.:
Improved non-restoring division algorithm with dual path calculation. MWSCAS 2013: 1379-1382 - [c109]Jae Hong Min, Earl E. Swartzlander Jr.:
Fused floating-point magnitude unit. MWSCAS 2013: 1383-1386 - 2012
- [j73]Hyesook Lim, Soohyun Lee, Earl E. Swartzlander Jr.:
A new hierarchical packet classification algorithm. Comput. Networks 56(13): 3010-3022 (2012) - [j72]Earl E. Swartzlander Jr., Hani H. Saleh:
FFT Implementation with Fused Floating-Point Operations. IEEE Trans. Computers 61(2): 284-288 (2012) - [j71]Jongwook Sohn, Earl E. Swartzlander Jr.:
Improved Architectures for a Fused Floating-Point Add-Subtract Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2285-2291 (2012) - [c108]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Truncated error correction for flexible approximate multiplication. ACSCC 2012: 355-359 - [c107]Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.:
A review of QCA adders and metrics. ACSCC 2012: 747-751 - [c106]Jae Hong Min, Jongwook Sohn, Earl E. Swartzlander Jr.:
A low-power dual-path floating-point fused add-subtract unit. ACSCC 2012: 998-1002 - [c105]Kihwan Jun, Earl E. Swartzlander Jr.:
Modified non-restoring division algorithm with improved delay profile and error correction. ACSCC 2012: 1460-1464 - [c104]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Long Residue Checking for Adders. ASAP 2012: 177-180 - [c103]Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
Cost-efficient decimal adder design in Quantum-dot cellular automata. ISCAS 2012: 1347-1350 - [c102]Samuel I. Ward, Myung-Chul Kim, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Earl E. Swartzlander Jr., David Z. Pan:
Keep it straight: teaching placement how to better handle designs with datapaths. ISPD 2012: 79-86 - [c101]Sreenivaas Muthyala Sudhakar, Kumar P. Chidambaram, Earl E. Swartzlander Jr.:
Hybrid Han-Carlson adder. MWSCAS 2012: 818-821 - 2011
- [j70]Inwook Kong, Earl E. Swartzlander Jr.:
A Goldschmidt Division Method With Faster Than Quadratic Convergence. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 696-700 (2011) - [j69]Waqas Akram, Earl E. Swartzlander Jr.:
Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters. J. Signal Process. Syst. 65(2): 199-210 (2011) - [c100]Michael B. Sullivan, Earl E. Swartzlander Jr.:
Hybrid residue generators for increased efficiency. ACSCC 2011: 144-148 - [c99]Jae Hong Min, Seong-Wan Kim, Earl E. Swartzlander Jr.:
A floating-point fused FFT butterfly arithmetic unit with Merged Multiple-Constant Multipliers. ACSCC 2011: 520-524 - [c98]Andrew G. Shafer, Lyndsi R. Parker, Earl E. Swartzlander Jr.:
The fully-serial pipelined multiplier. ACSCC 2011: 1817-1822 - [c97]Weiqiang Liu, Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
Design rules for Quantum-dot Cellular Automata. ISCAS 2011: 2361-2364 - [c96]Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. ISPD 2011: 91-98 - [e2]Joseph R. Cavallaro, Milos D. Ercegovac, Frank Hannig, Paolo Ienne, Earl E. Swartzlander Jr., Alexandre F. Tenca:
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1291-3 [contents] - 2010
- [j68]Terence K. Rodrigues, Earl E. Swartzlander Jr.:
Adaptive CORDIC: Using Parallel Angle Recoding to Accelerate Rotations. IEEE Trans. Computers 59(4): 522-531 (2010) - [j67]Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.:
Priority Tries for IP Address Lookup. IEEE Trans. Computers 59(6): 784-794 (2010) - [j66]Ron S. Waters, Earl E. Swartzlander Jr.:
A Reduced Complexity Wallace Multiplier Reduction. IEEE Trans. Computers 59(8): 1134-1137 (2010) - [j65]Inwook Kong, Earl E. Swartzlander Jr.:
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division. IEEE Trans. Computers 59(12): 1703-1708 (2010) - [c95]Waqas Akram, Earl E. Swartzlander Jr.:
A novel technique for tunable mismatch shaping in oversampled digital-to-analog converters. ICASSP 2010: 1534-1537 - [c94]Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.:
QCA Systolic Matrix Multiplier. ISVLSI 2010: 149-154 - [c93]Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham:
High speed recursion-free CORDIC architecture. SoCC 2010: 65-70
2000 – 2009
- 2009
- [j64]Heumpil Cho, Earl E. Swartzlander Jr.:
Adder and Multiplier Design in Quantum-Dot Cellular Automata. IEEE Trans. Computers 58(6): 721-727 (2009) - [c92]Bassam Jamil Mohd, Earl E. Swartzlander Jr.:
A Power-Scalable Switch-Based Multi-processor FFT. ASAP 2009: 114-120 - [c91]Inwook Kong, Earl E. Swartzlander Jr., Seong-Wan Kim:
Design of a Goldschmidt iterative divider for quantum-dot cellular automata. NANOARCH 2009: 47-50 - [c90]Robert J. Ascott, Earl E. Swartzlander Jr.:
JavaFlow - A Java dataflow machine. SoCC 2009: 211-214 - [c89]Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
ASIC evaluation of ECHO hash function. SoCC 2009: 387-390 - 2008
- [j63]Youngmoon Choi, Earl E. Swartzlander Jr.:
Speculative Carry Generation With Prefix Adder. IEEE Trans. Very Large Scale Integr. Syst. 16(3): 321-326 (2008) - [j62]Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds:
Bridge Floating-Point Fused Multiply-Add Design. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1727-1731 (2008) - [j61]Robert T. Grisamore, Earl E. Swartzlander Jr.:
Negative Save Sign Extension for Multi-term Adders and Multipliers. J. Signal Process. Syst. 52(1): 1-11 (2008) - [j60]Earl E. Swartzlander Jr.:
Systolic FFT Processors: A Personal Perspective. J. Signal Process. Syst. 53(1-2): 3-14 (2008) - [c88]Earl E. Swartzlander Jr., Hani H. Saleh:
Fused floating-point arithmetic for DSP. ACSCC 2008: 767-771 - [c87]Inwook Kong, Earl E. Swartzlander Jr.:
A rounding method with improved error tolerance for division by convergence. ACSCC 2008: 1814-1818 - [c86]Vijay K. Jain, Earl E. Swartzlander Jr.:
32 bit single cycle nonlinear VLSI cell for the ICA algorithm. ICASSP 2008: 1429-1432 - [c85]Hani H. Saleh, Earl E. Swartzlander Jr.:
A floating-point fused dot-product unit. ICCD 2008: 427-431 - [c84]Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.:
High performance IP lookup circuit using DDR SDRAM. SoCC 2008: 371-374 - [p2]Eric Quinnell, Earl E. Swartzlander Jr.:
Floating-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008 - [p1]Earl E. Swartzlander Jr.:
Fixed-Point Computer Arithmetic. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j59]Earl E. Swartzlander Jr.:
The Negative Two's Complement Number System. J. VLSI Signal Process. 49(1): 177-183 (2007) - [c83]Heumpil Cho, Earl E. Swartzlander Jr.:
Serial Parallel Multiplier Design in Quantum-dot Cellular Automata. IEEE Symposium on Computer Arithmetic 2007: 7-15 - [c82]Hani H. Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ICCD 2007: 7-12 - [c81]Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz:
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. VLSI-SoC (Selected Papers) 2007: 1-22 - [c80]Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. VLSI-SoC 2007: 194-199 - 2006
- [j58]Chang Yong Kang, Earl E. Swartzlander Jr.:
Digit-pipelined direct digital frequency synthesis based on differential CORDIC. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1035-1044 (2006) - [c79]Tung N. Pham, Earl E. Swartzlander Jr.:
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology. ASAP 2006: 105-108 - [c78]Earl E. Swartzlander Jr.:
Systolic FFT Processors: Past, Present and Future. ASAP 2006: 153-158 - 2005
- [c77]Youngmoon Choi, Earl E. Swartzlander Jr.:
Parallel Prefix Adder Design with Matrix Representation. IEEE Symposium on Computer Arithmetic 2005: 90-98 - [c76]Moboluwaji O. Sanu, Earl E. Swartzlander Jr.:
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields. ASAP 2005: 134-139 - [c75]Earl E. Swartzlander Jr.:
Three Dimensional System on Chip Technology, invited. IWSOC 2005: 465-470 - 2004
- [c74]Moboluwaji O. Sanu, Earl E. Swartzlander Jr., Craig M. Chase:
Parallel Montgomery Multipliers. ASAP 2004: 63-72 - [c73]Earl E. Swartzlander Jr.:
A Review of Large Parallel Counter Designs. ISVLSI 2004: 89-98 - 2003
- [j57]Mohammad Ibrahim, Earl E. Swartzlander Jr.:
Guest Editorial. J. VLSI Signal Process. 33(1-2): 5 (2003) - [c72]Ayman M. El-Khashab, Earl E. Swartzlander Jr.:
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. ASAP 2003: 378-388 - [c71]Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.:
Quadruple Time Redundancy Adders. DFT 2003: 250-256 - [c70]Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.:
A self-testing method for the pipelined A/D converter. ISCAS (1) 2003: 109-112 - 2002
- [j56]Sungwook Yu, Earl E. Swartzlander Jr.:
A scaled DCT architecture with the CORDIC algorithm. IEEE Trans. Signal Process. 50(1): 160-167 (2002) - [j55]Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.:
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells. J. VLSI Signal Process. 31(2): 77-89 (2002) - [c69]Chang Yong Kang, Earl E. Swartzlander Jr.:
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. ASAP 2002: 111-119 - [c68]Steven M. Currie, Paul R. Schumacher, Barry K. Gilbert, Earl E. Swartzlander Jr., Barbara A. Randall:
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS. ASAP 2002: 335-343 - 2001
- [j54]Sungwook Yu, Earl E. Swartzlander Jr.:
DCT Implementation with Distributed Arithmetic. IEEE Trans. Computers 50(9): 985-991 (2001) - [j53]Sungwook Yu, Earl E. Swartzlander Jr.:
A pipelined architecture for the multidimensional DFT. IEEE Trans. Signal Process. 49(9): 2096-2102 (2001) - [c67]K'Andrea C. Bickerstaff, Earl E. Swartzlander Jr., Michael J. Schulte:
Analysis of Column Compression Multipliers. IEEE Symposium on Computer Arithmetic 2001: 33-39 - [c66]Tat Ngai, Earl E. Swartzlander Jr., Chen He:
Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic. DFT 2001: 78-83 - [c65]Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka:
A fast hybrid carry-lookahead/carry-select adder design. ACM Great Lakes Symposium on VLSI 2001: 149-152 - [c64]Jae-Hyuck Kwak, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Time-shared TMR for fault-tolerant CORDIC processors. ICASSP 2001: 1241-1244 - 2000
- [j52]Michael J. Schulte, Earl E. Swartzlander Jr.:
A Family of Variable-Precision Interval Arithmetic Processors. IEEE Trans. Computers 49(5): 387-397 (2000) - [j51]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR. IEEE Trans. Computers 49(6): 588-595 (2000) - [j50]Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.:
A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms. IEEE Trans. Computers 49(12): 1297-1309 (2000) - [j49]Jae-Hyuck Kwak, Jae Hun Choi, Earl E. Swartzlander Jr.:
High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method. J. VLSI Signal Process. 25(2): 167-177 (2000) - [c63]Ohsang Kwon, Earl E. Swartzlander Jr., Kevin J. Nowka:
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors. ASAP 2000: 235- - [c62]Jae-Hyuck Kwak, Earl E. Swartzlander Jr., Vincenzo Piuri:
Fault-Tolerant High-Performance Cordic Processors. DFT 2000: 164-172
1990 – 1999
- 1999
- [j48]Francescomaria Marino, Earl E. Swartzlander Jr.:
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication. IEEE Trans. Computers 48(9): 951-961 (1999) - [j47]Hyesook Lim, Earl E. Swartzlander Jr.:
Multidimensional systolic arrays for the implementation of discrete Fourier transforms. IEEE Trans. Signal Process. 47(5): 1359-1370 (1999) - [j46]Francescomaria Marino, Vincenzo Piuri, Earl E. Swartzlander Jr.:
A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications. IEEE Trans. Signal Process. 47(11): 3179-3184 (1999) - [c61]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Power Consumption in Fast Dividers Using Time Shared TMR. DFT 1999: 256-264 - [c60]Vincenzo Piuri, Earl E. Swartzlander Jr.:
Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. DFT 1999: 265-273 - [c59]Jae Hun Choi, Jae-Hyuck Kwak, Earl E. Swartzlander Jr.:
High-Speed CORDIC Architecture Based on Redundant Sum Formation and Overlapped s-Selection. ICCD 1999: 68-72 - [c58]Gwangwoo Choe, Earl E. Swartzlander Jr.:
Bipolar merged arithmetic for wavelet architectures. ISCAS (3) 1999: 462-465 - 1998
- [j45]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 20(1): 67-76 (1998) - [j44]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 20(3): 72-73 (1998) - [j43]Earl E. Swartzlander Jr.:
VLSI, MCM, and WSI: A Design Comparison. IEEE Des. Test Comput. 15(3): 28-34 (1998) - [j42]Mary Jane Irwin, Sun-Yuan Kung, Earl E. Swartzlander Jr.:
Editorial Message. J. VLSI Signal Process. 18(1): 7-8 (1998) - [c57]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Error-Correcting Goldschmidt Dividers Using Time Shared TMR. DFT 1998: 224-232 - [c56]Gwangwoo Choe, Earl E. Swartzlander Jr.:
Merged Arithmetic for Computing Wavelet Transforms. Great Lakes Symposium on VLSI 1998: 196-201 - [c55]Moises E. Robinson, Earl E. Swartzlander Jr.:
A reduction scheme to optimize the Wallace multiplier. ICCD 1998: 122-127 - 1997
- [j41]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 19(1): 74-75 (1997) - [j40]Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Hybrid CORDIC Algorithms. IEEE Trans. Computers 46(11): 1202-1207 (1997) - [c54]Thomas K. Callaway, Earl E. Swartzlander Jr.:
Power-Delay Characteristics of CMOS Multipliers. IEEE Symposium on Computer Arithmetic 1997: 26- - [c53]Hercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.:
Realization of a nonlinear digital filter on a DSP array processor. ASAP 1997: 24-33 - [c52]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR. DFT 1997: 243-251 - [c51]Edwin de Angel, Earl E. Swartzlander Jr.:
Survey of low power techniques for ROMs. ISLPED 1997: 7-11 - [r1]Earl E. Swartzlander Jr.:
High-Speed Computer Arithmetic. The Computer Science and Engineering Handbook 1997: 462-481 - 1996
- [j39]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 18(3): 70-71 (1996) - [j38]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 18(4): 62-64 (1996) - [j37]Michael J. Schulte, Earl E. Swartzlander Jr.:
Variable-precision, interval arithmetic coprocessors. Reliab. Comput. 2(1): 47-62 (1996) - [j36]Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr.:
A new design for a lookahead carry generator. J. VLSI Signal Process. 14(3): 295-302 (1996) - [c50]Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr.:
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. ASAP 1996: 35- - [c49]Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Comprehensive Modeling of VLSI Test. DFT 1996: 159-167 - [c48]W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Fault tolerant Newton-Raphson dividers using time shared TMR. DFT 1996: 240-248 - [c47]Hyesook Lim, Earl E. Swartzlander Jr.:
Multidimensional systolic arrays for multidimensional DFTs. ICASSP 1996: 3276-3279 - [c46]Shaoyun Wang, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Granularly-pipelined CORDIC processors for sine and cosine generators. ICASSP 1996: 3298-3301 - 1995
- [j35]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 17(3): 75-77 (1995) - [j34]Earl E. Swartzlander Jr.:
Calculators. IEEE Ann. Hist. Comput. 17(4): 4 (1995) - [j33]Michael J. Schulte, Earl E. Swartzlander Jr.:
A software interface and hardware design for variable-precision interval arithmetic. Reliab. Comput. 1(3): 325-342 (1995) - [j32]K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.:
Parallel reduced area multipliers. J. VLSI Signal Process. 9(3): 181-191 (1995) - [c45]Hercule Kwan, Robert Leonard Nelson Jr., Earl E. Swartzlander Jr.:
Cascaded Implementation of an Iterative Inverse--Square--Root Algorithm, with Overflow Lookahead. IEEE Symposium on Computer Arithmetic 1995: 115- - [c44]Michael J. Schulte, Earl E. Swartzlander Jr.:
Hardware Design and Arithmetic Algorithms for a Variable-Precision, Interval Arithmetic Coprocessor. IEEE Symposium on Computer Arithmetic 1995: 222-229 - [c43]Yuang-Ming Hsu, Earl E. Swartzlander Jr., Vincenzo Piuri:
Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks. ASAP 1995: 54-65 - [c42]Michael J. Schulte, Earl E. Swartzlander Jr.:
A Processor for Staggered Interval Arithmetic. ASAP 1995: 104-112 - [c41]Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Efficient time redundancy for error correcting inner-product units and convolvers. DFT 1995: 198-206 - [c40]Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Characterization and analysis of errors in circuit test. DFT 1995: 261-268 - [c39]Hyesook Lim, Earl E. Swartzlander Jr.:
An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . ICCD 1995: 644-649 - [c38]Michael J. Schulte, Earl E. Swartzlander Jr.:
A coprocessor for accurate and reliable numerical computations. ICCD 1995: 686-691 - [c37]Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks. ISCAS 1995: 977-980 - [c36]Shaoyun Wang, Earl E. Swartzlander Jr.:
Merged CORDIC Algorithm. ISCAS 1995: 1988-1991 - [c35]Yuang-Ming Hsu, Vincenzo Piuri, Earl E. Swartzlander Jr.:
Fault-Tolerant Neural Architectures: The Use of Rotated Operands. ISCAS 1995: 2201-2204 - [c34]Mohammad S. Khan, Earl E. Swartzlander Jr.:
Rapid prototyping fault-tolerant heterogeneous digital signal processing systems. RSP 1995: 187-193 - 1994
- [j31]Michael J. Schulte, J. Omar, Earl E. Swartzlander Jr.:
Optimal initial approximations for the Newton-Raphson division algorithm. Computing 53(3-4): 233-242 (1994) - [j30]Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Boundary scan in board manufacturing. J. Electron. Test. 5(2-3): 263-268 (1994) - [j29]Michael J. Schulte, Earl E. Swartzlander Jr.:
Hardware Designs for Exactly Rounded Elemantary Functions. IEEE Trans. Computers 43(8): 964-973 (1994) - [j28]Robert F. Jones, Earl E. Swartzlander Jr.:
Parallel counter implementation. J. VLSI Signal Process. 7(3): 223-232 (1994) - [j27]Ben C. Drerup, Earl E. Swartzlander Jr.:
Fast multiplier bit-product matrix reduction using bit-ordering and parity generation. J. VLSI Signal Process. 7(3): 249-257 (1994) - [j26]Earl E. Swartzlander Jr.:
Editorial. J. VLSI Signal Process. 8(1): 5 (1994) - [c33]Hyesook Lim, Earl E. Swartzlander Jr.:
A systolic array for 2-D DFT and 2-D DCT. ASAP 1994: 123-131 - [c32]Michael J. Schulte, Earl E. Swartzlander Jr.:
A variable-precision interval arithmetic processor. ASAP 1994: 248-258 - [c31]Yuang-Ming Hsu, Earl E. Swartzlander Jr.:
Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers. DFT 1994: 159-167 - [c30]Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham:
A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. ICCD 1994: 302-305 - [c29]Earl E. Swartzlander Jr.:
Heterogeneous Parallel Computing. ICPADS 1994: 8-9 - [c28]José Duato, C. T. Howard Ho, Ferng-Ching Lin, Lionel M. Ni, Earl E. Swartzlander Jr.:
Is It Possible to Fairly Compare Interconnection Networks?. ICPADS 1994: 16-19 - [c27]Thomas L. Casavant, Chi-Yuan Chin, Wen-Tsuen Chen, Kang G. Shin, Earl E. Swartzlander Jr., Joseph E. Urban:
What Types of Research Papers Should We Be Writing? ICPADS 1994: 22-23 - [c26]Yuang-Ming Hsu, Earl E. Swartzlander Jr.:
Sorting Networks with Built-In Error Correction. ICPADS 1994: 379-385 - [c25]Mohammad S. Khan, Earl E. Swartzlander Jr.:
A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors. ISCAS 1994: 97-100 - 1993
- [j25]Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.:
Modified Booth algorithm for high radix fixed-point multiplication. IEEE Trans. Very Large Scale Integr. Syst. 1(2): 164-167 (1993) - [j24]Earl E. Swartzlander Jr., Miroslaw Malek:
Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays. VLSI Design 1(1): 1-7 (1993) - [c24]Michael J. Schulte, Earl E. Swartzlander Jr.:
Exact rounding of certain elementary functions. IEEE Symposium on Computer Arithmetic 1993: 138-145 - [c23]Thomas K. Callaway, Earl E. Swartzlander Jr.:
Estimating the power consumption of CMOS adders. IEEE Symposium on Computer Arithmetic 1993: 210-216 - [c22]K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.:
Reduced area multipliers. ASAP 1993: 478-489 - [c21]Yuang-Ming Hsu, Earl E. Swartzlander Jr.:
VLSI Concurrent Error Correcting Adders and Multipliers. DFT 1993: 287-294 - [c20]Rathish Jayabharathi, Thomas Thomas, Earl E. Swartzlander Jr.:
A Comparative Evaluation of Adders Based on Performance and Testability. ICCD 1993: 314-317 - [c19]Ishaq H. Unwala, Earl E. Swartzlander Jr.:
Superpipelined Adder Designs. ISCAS 1993: 1841-1844 - [c18]Mohammad S. Khan, Earl E. Swartzlander Jr.:
Design and implementation of an interface control unit for rapid prototyping. RSP 1993: 141-148 - [e1]Earl E. Swartzlander Jr., Mary Jane Irwin, Graham A. Jullien:
11th Symposium on Computer Arithmetic, 29 June - 2 July 1993, Windsor, Canada, Proceedings. IEEE Computer Society/ 1993, ISBN 0-8186-3862-1 [contents] - 1992
- [j23]W. Kent Fuchs, Earl E. Swartzlander Jr.:
Wafer-Scale Integration: Architectures and Algorithms - Guest Editors' Introduction. Computer 25(4): 6-8 (1992) - [j22]Thomas W. Lynch, Earl E. Swartzlander Jr.:
A Spanning Tree Carry Lookahead Adder. IEEE Trans. Computers 41(8): 931-939 (1992) - [j21]Earl E. Swartzlander Jr., Vijay K. Jain, Hiroomi Hikawa:
A radix-8 wafer scale FFT processor. J. VLSI Signal Process. 4(2-3): 165-176 (1992) - [c17]Earl E. Swartzlander Jr.:
Advanced technology for improved signal processor efficiency. ASAP 1992: 257-268 - [c16]Vijay K. Jain, Gibert E. Perez, Earl E. Swartzlander Jr.:
Arithmetic Error Analysis of a new Reciprocal Cell. ICCD 1992: 106-109 - [c15]Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.:
Modified Booth Algorithm for High Radix Multiplication. ICCD 1992: 118-121 - [c14]Thomas K. Callaway, Earl E. Swartzlander Jr.:
Implementation of Parallel Processors with Wafer Scale Integration. IPPS 1992: 268-274 - 1991
- [c13]Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr.:
High-speed multiplier design using multi-input counter and compressor circuits. IEEE Symposium on Computer Arithmetic 1991: 43-50 - [c12]David Zhang, Graham A. Jullien, William C. Miller, Earl E. Swartzlander Jr.:
Arithmetic for digital neural networks. IEEE Symposium on Computer Arithmetic 1991: 58-63 - [c11]Thomas W. Lynch, Earl E. Swartzlander Jr.:
The redundant cell adder. IEEE Symposium on Computer Arithmetic 1991: 165-170 - [c10]Earl E. Swartzlander Jr.:
The case for application specific computing. ASAP 1991: 2-9 - 1990
- [j20]Earl E. Swartzlander Jr.:
Editorial. J. VLSI Signal Process. 2(1): 5 (1990) - [j19]Earl E. Swartzlander Jr.:
Generic signal processor implementation with VHSIC. J. VLSI Signal Process. 2(2): 111-116 (1990)
1980 – 1989
- 1989
- [j18]Earl E. Swartzlander Jr.:
Editorial. J. VLSI Signal Process. 1(1): 5 (1989) - [j17]Earl E. Swartzlander Jr.:
Editorial. J. VLSI Signal Process. 1(2): 91 (1989) - [j16]Earl E. Swartzlander Jr.:
Editorial. J. VLSI Signal Process. 1(3): 167 (1989) - 1985
- [j15]Stephen F. Lundstrom, Earl E. Swartzlander Jr.:
Foreword: Advances in Distributed Computing Systems. IEEE Trans. Software Eng. 11(10): 1092-1096 (1985) - [c9]Earl E. Swartzlander Jr., John A. Eldon:
Arithmetic for high speed FFT implementation. IEEE Symposium on Computer Arithmetic 1985: 223-230 - [c8]Earl E. Swartzlander Jr., John A. Eldon, De D. Hsu:
VLSI Testing: A Decade of Experience. COMPCON 1985: 392-396 - [c7]John A. Eldon, Zoltan Stroll, Earl E. Swartzlander Jr.:
Image processing address generator chip. ICASSP 1985: 993-996 - 1984
- [c6]Earl E. Swartzlander Jr., George Hallnor:
Fast transform processor implementation. ICASSP 1984: 347-350 - 1983
- [j14]Earl E. Swartzlander Jr., D. V. Satish Chandra, H. Troy Nagle Jr., Scott A. Starks:
Sign/Logarithm Arithmetic for FFT Implementation. IEEE Trans. Computers 32(6): 526-534 (1983) - [c5]Earl E. Swartzlander Jr., Louis S. Lome, George Hallnor:
Digital signal processing with VLSI technology. ICASSP 1983: 951-954 - 1982
- [j13]Earl E. Swartzlander Jr., Barry K. Gilbert:
Supersystems: Technology and Architecture. IEEE Trans. Computers 31(5): 399-409 (1982) - 1980
- [j12]Earl E. Swartzlander Jr., Barry K. Gilbert:
Arithmetic for Ultra-High-Speed Tomography. IEEE Trans. Computers 29(5): 341-353 (1980) - [j11]Earl E. Swartzlander Jr.:
Merged Arithmetic. IEEE Trans. Computers 29(10): 946-950 (1980) - [c4]Earl E. Swartzlander Jr.:
Signal processing architectures with VLSI. ICASSP 1980: 368-371
1970 – 1979
- 1979
- [j10]Earl E. Swartzlander Jr., Douglas J. Heath:
A Routing Algorithm for Signal Processing Networks. IEEE Trans. Computers 28(8): 567-572 (1979) - [j9]Earl E. Swartzlander Jr.:
Comment on "The Focus Number System". IEEE Trans. Computers 28(9): 693 (1979) - [j8]Earl E. Swartzlander Jr.:
Microprogrammed Control for Specialized Processors. IEEE Trans. Computers 28(12): 930-934 (1979) - 1978
- [j7]Earl E. Swartzlander Jr., Barry K. Gilbert, Irving S. Reed:
Inner Product Computers. IEEE Trans. Computers 27(1): 21-31 (1978) - [c3]Earl E. Swartzlander Jr.:
Merged arithmetic for signal processing. IEEE Symposium on Computer Arithmetic 1978: 239-244 - 1977
- [c2]Earl E. Swartzlander Jr.:
Microprogrammed control for signal processing. MICRO 1977: 80-84 - 1975
- [j6]Earl E. Swartzlander Jr., Aristides G. Alexopoulos:
The Sign/Logarithm Number System. IEEE Trans. Computers 24(12): 1238-1242 (1975) - 1973
- [j5]Earl E. Swartzlander Jr.:
The Quasi-Serial Multiplier. IEEE Trans. Computers 22(4): 317-321 (1973) - [j4]Earl E. Swartzlander Jr.:
Parallel Counters. IEEE Trans. Computers 22(11): 1021-1024 (1973) - [j3]Earl E. Swartzlander Jr.:
The inner product computer (Ph.D. Thesis abstr.). IEEE Trans. Inf. Theory 19(1): 140 (1973) - [j2]Earl E. Swartzlander Jr.:
Review of "Introduction to Mathematical Techniques in Pattern Recognition" by Harry C. Andrews. IEEE Trans. Syst. Man Cybern. 3(3): 302 (1973) - [j1]Earl E. Swartzlander Jr.:
Review of "Fundamentals of Pattern Recognition" by Edward A. Patrick. IEEE Trans. Syst. Man Cybern. 3(5): 528 (1973) - [c1]Earl E. Swartzlander Jr.:
Applications of the inner product computer. ACM Annual Conference 1973: 97-100
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-18 20:30 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
