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ORCIDGeorg Sigl
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- affiliation: Technical University Munich, Germany
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2020 – today
- 2023
[c109]Mathieu Gross, Jonas Krautter, Dennis Gnad, Michael Gruber, Georg Sigl, Mehdi B. Tahoori:
FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU. ASP-DAC 2023: 358-364- 2022
- [j29]Mathieu Gross
, Nisha Jacob, Andreas Zankl, Georg Sigl:
Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC. J. Cryptogr. Eng. 12(2): 181-196 (2022) - [j28]Tim Fritzmann, Michiel Van Beirendonck, Debapriya Basu Roy, Patrick Karl, Thomas Schamberger, Ingrid Verbauwhede, Georg Sigl:
Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(1): 414-460 (2022) - [j27]Bodo Selmke, Maximilian Pollanka, Andreas Duensing, Emanuele Strieder, Hayden Wen, Michael Mittermair, Reinhard Kienberger, Georg Sigl:
On the application of Two-Photon Absorption for Laser Fault Injection attacks Pushing the physical boundaries for Laser-based Fault Injection. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(4): 862-885 (2022) - [j26]Michaela Brunner, Alexander Hepp, Johanna Baehr, Georg Sigl:
Toward a Human-Readable State Machine Extraction. ACM Trans. Design Autom. Electr. Syst. 27(6): 58:1-58:31 (2022) - [j25]Mathieu Gross, Konrad Hohentanner, Stefan Wiehler, Georg Sigl:
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM. ACM Trans. Reconfigurable Technol. Syst. 15(1): 5:1-5:26 (2022) - [j24]Seyed Hamidreza Moghadas, Michael Pehl, Georg Sigl:
ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1716-1727 (2022) - [c108]Maximilian Egger, Thomas Schamberger, Lars Tebelmann, Florian Lippert, Georg Sigl:
A Second Look at the ASCAD Databases. COSADE 2022: 75-99 - [c107]Manuel Brosch, Matthias Probst, Georg Sigl:
Counteract Side-Channel Analysis of Neural Networks by Shuffling. DATE 2022: 1305-1310 - [c106]Alexander Hepp, Johanna Baehr, Georg Sigl:
Golden Model-Free Hardware Trojan Detection by Classification of Netlist Module Graphs. DATE 2022: 1317-1322 - [c105]Patrick Karl, Tim Fritzmann, Georg Sigl:
Hardware Accelerated FrodoKEM on RISC-V. DDECS 2022: 154-159 - [c104]Johanna Baehr, Alexander Hepp, Michaela Brunner, Maja Malenko, Georg Sigl:
Open Source Hardware Design and Hardware Reverse Engineering: A Security Analysis. DSD 2022: 504-512 - [c103]Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl:
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. ICCAD 2022: 69 - [c102]Thomas Schamberger, Lukas Holzbaur, Julian Renner, Antonia Wachter-Zeh, Georg Sigl:
A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. PQCrypto 2022: 327-352 - [i24]Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl:
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. CoRR abs/2208.09235 (2022) - [i23]Michael Gruber, Georg Sigl:
TOFU - Toggle Count Analysis made simple. IACR Cryptol. ePrint Arch. 2022: 129 (2022) - [i22]Patrick Karl, Jonas Schupp, Tim Fritzmann, Georg Sigl:
Post-Quantum Signatures on RISC-V with Hardware Acceleration. IACR Cryptol. ePrint Arch. 2022: 538 (2022) - [i21]Thomas Schamberger, Lukas Holzbaur, Julian Renner, Antonia Wachter-Zeh, Georg Sigl:
A Power Side-Channel Attack on the Reed-Muller Reed-Solomon Version of the HQC Cryptosystem. IACR Cryptol. ePrint Arch. 2022: 724 (2022) - 2021
- [j23]Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl:
Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks. ACM Trans. Embed. Comput. Syst. 20(2): 17:1-17:23 (2021) - [j22]Alexander Kulow, Thomas Schamberger, Lars Tebelmann, Georg Sigl:
Finding the Needle in the Haystack: Metrics for Best Trace Selection in Unsupervised Side-Channel Attacks on Blinded RSA. IEEE Trans. Inf. Forensics Secur. 16: 3254-3268 (2021) - [j21]Michael Gruber, Matthias Probst, Patrick Karl, Thomas Schamberger, Lars Tebelmann, Michael Tempelmeier, Georg Sigl:
DOMREP-An Orthogonal Countermeasure for Arbitrary Order Side-Channel and Fault Attack Protection. IEEE Trans. Inf. Forensics Secur. 16: 4321-4335 (2021) - [c101]Alexander Hepp, Georg Sigl:
Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. CF 2021: 213-220 - [c100]Stefan Hristozov, Manuel Huber, Lei Xu, Jaro Fietz, Marco Liess, Georg Sigl:
The Cost of OSCORE and EDHOC for Constrained Devices. CODASPY 2021: 245-250 - [c99]Michael Gruber, Patrick Karl, Georg Sigl:
Algebraic Fault Analysis of Subterranean 2.0. FDTC 2021: 45-55 - [i20]Stefan Hristozov, Manuel Huber, Lei Xu, Jaro Fietz, Marco Liess, Georg Sigl:
The Cost of OSCORE and EDHOC for Constrained Devices. CoRR abs/2103.13832 (2021) - [i19]Tim Fritzmann, Michiel Van Beirendonck, Debapriya Basu Roy, Patrick Karl, Thomas Schamberger, Ingrid Verbauwhede, Georg Sigl:
Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2021: 479 (2021) - 2020
- [j20]Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann:
Machine learning and structural characteristics for reverse engineering. Integr. 72: 1-12 (2020) - [j19]Matthias Hiller, Ludwig Kürzinger, Georg Sigl:
Review of error correction for PUFs and evaluation on state-of-the-art FPGAs. J. Cryptogr. Eng. 10(3): 229-247 (2020) - [j18]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4482-4495 (2020) - [j17]Tim Fritzmann, Georg Sigl, Johanna Sepúlveda:
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(4): 239-280 (2020) - [c98]Grace Li Zhang, Michaela Brunner, Bing Li, Georg Sigl, Ulf Schlichtmann:
Timing Resilience for Efficient and Secure Circuits. ASP-DAC 2020: 623-628 - [c97]Thomas Schamberger, Julian Renner, Georg Sigl, Antonia Wachter-Zeh:
A Power Side-Channel Attack on the CCA2-Secure HQC KEM. CARDIS 2020: 119-134 - [c96]Tim Fritzmann, Georg Sigl, Johanna Sepúlveda:
Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LAC. DATE 2020: 1420-1425 - [c95]Stefan Hristozov, Manuel Huber, Georg Sigl:
Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks. HOST 2020: 316-327 - [c94]Debapriya Basu Roy, Tim Fritzmann, Georg Sigl:
Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers. ICCAD 2020: 35:1-35:9 - [c93]Michaela Brunner, Michael Gruber, Michael Tempelmeier, Georg Sigl:
Logic Locking Induced Fault Attacks. ISVLSI 2020: 114-119 - [c92]Martin Striegel, Johann Heyszl, Florian Jakobsmeier, Yacov Matveev, Georg Sigl:
Secure and user-friendly over-the-air firmware distribution in a portable faraday cage. WISEC 2020: 173-183 - [i18]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR abs/2003.00862 (2020) - [i17]Martin Striegel, Florian Jakobsmeier, Yacov Matveev, Johann Heyszl, Georg Sigl:
Secure and User-Friendly Over-the-Air Firmware Distribution in a Portable Faraday Cage. CoRR abs/2005.12347 (2020) - [i16]Tim Fritzmann, Georg Sigl, Johanna Sepúlveda:
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2020: 446 (2020) - [i15]Thomas Schamberger, Julian Renner, Georg Sigl, Antonia Wachter-Zeh:
A Power Side-Channel Attack on the CCA2-Secure HQC KEM. IACR Cryptol. ePrint Arch. 2020: 910 (2020)
2010 – 2019
- 2019
- [j16]Vincent Immler, Johannes Obermaier, Kuan Kuan Ng, Fei Xiang Ke, JinYu Lee, Yak Peng Lim, Wei Koon Oh, Keng Hoong Wee, Georg Sigl:
Secure Physical Enclosures from Covers with Tamper-Resistance. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(1): 51-96 (2019) - [j15]Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich:
A Calibratable Detector for Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1067-1079 (2019) - [c91]Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann:
Machine learning and structural characteristics for reverse engineering. ASP-DAC 2019: 96-103 - [c90]Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl:
Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC. ASHES@CCS 2019: 3-12 - [c89]Martin Striegel, Carsten Rolfes, Johann Heyszl, Fabian Helfert, Maximilian Hornung, Georg Sigl:
EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. EWSN 2019: 184-193 - [c88]Michaela Brunner, Johanna Baehr, Georg Sigl:
Improving on State Register Identification in Sequential Hardware Reverse Engineering. HOST 2019: 151-160 - [c87]Michael Tempelmeier, Maximilian Werner, Georg Sigl:
Using Hardware Software Codesign for Optimised Implementations of High-Speed and Defence in Depth CAESAR Finalists. HOST 2019: 228-237 - [c86]Matthias Niedermaier, Dominik Merli, Georg Sigl:
A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices. MECO 2019: 1-5 - [i14]Martin Striegel, Carsten Rolfes, Johann Heyszl, Fabian Helfert, Maximilian Hornung, Georg Sigl:
EyeSec: A Retrofittable Augmented Reality Tool for Troubleshooting Wireless Sensor Networks in the Field. CoRR abs/1907.12364 (2019) - [i13]Matthias Niedermaier, Martin Striegel, Felix Sauer, Dominik Merli, Georg Sigl:
Efficient Intrusion Detection on Low-Performance Industrial IoT Edge Node Devices. CoRR abs/1908.03964 (2019) - [i12]Matthias Niedermaier, Dominik Merli, Georg Sigl:
A Secure Dual-MCU Architecture for Robust Communication of IIoT Devices. CoRR abs/1908.04133 (2019) - [i11]Matthias Niedermaier, Florian Fischer, Dominik Merli, Georg Sigl:
Network Scanning and Mapping for IIoT Edge Node Device Security. CoRR abs/1910.07622 (2019) - [i10]Stefan Hristozov, Manuel Huber, Georg Sigl:
Protecting RESTful IoT Devices from Battery Exhaustion DoS Attacks. CoRR abs/1911.08134 (2019) - 2018
- [j14]Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018(1): 1-17 (2018) - [j13]Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl:
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 392-403 (2018) - [c85]Florian Unterstein, Johann Heyszl, Fabrizio De Santis, Robert Specht, Georg Sigl:
High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And an Improved Construction. CT-RSA 2018: 413-434 - [c84]Johannes Obermaier, Vincent Immler, Matthias Hiller, Georg Sigl:
A measurement system for capacitive PUF-based security enclosures. DAC 2018: 64:1-64:6 - [c83]Georg Sigl, Mathieu Gross, Michael Pehl:
Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. ESSCIRC 2018: 12-17 - [c82]Johanna Sepúlveda, Damian Aboul-Hassan, Georg Sigl, Bernd Becker, Matthias Sauer:
Towards the formal verification of security properties of a Network-on-Chip router. ETS 2018: 1-6 - [c81]Bodo Selmke, Kilian Zinnecker, Philipp Koppermann, Katja Miller, Johann Heyszl, Georg Sigl:
Locked out by Latch-up? An Empirical Study on Laser Fault Injection into Arm Cortex-M Processors. FDTC 2018: 7-14 - [c80]Robert Specht, Vincent Immler, Florian Unterstein, Johann Heyszl, Georg Sigl:
Dividing the threshold: Multi-probe localized EM analysis on threshold implementations. HOST 2018: 33-40 - [c79]Vincent Immler, Johannes Obermaier, Martin König, Matthias Hiller, Georg Sigl:
B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection. HOST 2018: 49-56 - [c78]Michael Tempelmeier, Fabrizio De Santis, Georg Sigl, Jens-Peter Kaps:
The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates. HOST 2018: 73-80 - [c77]Samuel Weiser, Andreas Zankl, Raphael Spreitzer, Katja Miller, Stefan Mangard, Georg Sigl:
DATA - Differential Address Trace Analysis. Krypto-Tag 2018 - [c76]Johannes Obermaier, Florian Hauschild, Matthias Hiller, Georg Sigl:
An embedded key management system for PUF-based security enclosures. MECO 2018: 1-6 - [c75]Michael Tempelmeier, Georg Sigl, Jens-Peter Kaps:
Experimental Power and Performance Evaluation of CAESAR Hardware Finalists. ReConFig 2018: 1-6 - [c74]Samuel Weiser, Andreas Zankl, Raphael Spreitzer, Katja Miller, Stefan Mangard, Georg Sigl:
DATA - Differential Address Trace Analysis: Finding Address-based Side-Channels in Binaries. USENIX Security Symposium 2018: 603-620 - [i9]Florian Unterstein, Johann Heyszl, Fabrizio De Santis, Robert Specht, Georg Sigl:
High-Resolution EM Attacks Against Leakage-Resilient PRFs Explained - And An Improved Construction. IACR Cryptol. ePrint Arch. 2018: 55 (2018) - [i8]Philipp Koppermann, Eduard Pop, Johann Heyszl, Georg Sigl:
18 Seconds to Key Exchange: Limitations of Supersingular Isogeny Diffie-Hellman on Embedded Devices. IACR Cryptol. ePrint Arch. 2018: 932 (2018) - 2017
- [j12]Martha Johanna Sepúlveda, Daniel Flórez, Vincent Immler, Guy Gogniat, Georg Sigl:
Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs. Microprocess. Microsystems 50: 164-174 (2017) - [j11]Robert Hesselbarth, Johann Heyszl, Georg Sigl:
Fast and reliable PUF response evaluation from unsettled bistable rings. Microprocess. Microsystems 52: 325-332 (2017) - [j10]Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Low-latency X25519 hardware implementation: breaking the 100 microseconds barrier. Microprocess. Microsystems 52: 491-497 (2017) - [j9]Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Johanna Sepúlveda:
Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection. Microprocess. Microsystems 52: 556-565 (2017) - [c73]Lars Tebelmann, Michael Pehl, Georg Sigl:
EM Side-Channel Analysis of BCH-based Error Correction for PUF-based Key Generation. ASHES@CCS 2017: 43-52 - [c72]Nisha Jacob, Johann Heyszl, Andreas Zankl, Carsten Rolfes, Georg Sigl:
How to Break Secure Boot on FPGA SoCs Through Malicious Hardware. CHES 2017: 425-442 - [c71]Fabrizio De Santis, Andreas Schauer, Georg Sigl:
ChaCha20-Poly1305 authenticated encryption for high-speed embedded IoT applications. DATE 2017: 692-697 - [c70]Oscar M. Guillen, Thomas Pöppelmann, Jose Maria Bermudo Mera, Elena Fuentes Bongenaar, Georg Sigl, Johanna Sepúlveda:
Towards post-quantum security for IoT endpoints with NTRU. DATE 2017: 698-703 - [c69]Nisha Jacob, Carsten Rolfes, Andreas Zankl, Johann Heyszl, Georg Sigl:
Compromising FPGA SoCs using malicious hardware blocks. DATE 2017: 1122-1127 - [c68]Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Automatic generation of high-performance modular multipliers for arbitrary mersenne primes on FPGAs. HOST 2017: 35-40 - [c67]Vincent Immler, Matthias Hiller, Johannes Obermaier, Georg Sigl:
Take a moment and have some t: Hypothesis testing on raw PUF data. HOST 2017: 128-129 - [c66]Johanna Sepúlveda, Andreas Zankl, Daniel Flórez, Georg Sigl:
Towards Protected MPSoC Communication for Information Protection against a Malicious NoC. ICCS 2017: 1103-1112 - [c65]Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl:
Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips. ISVLSI 2017: 284-289 - [c64]Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl:
Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication. ReCoSoC 2017: 1-7 - [c63]Johanna Sepúlveda, Ramon Fernandes, César A. M. Marcon, Daniel Florez, Georg Sigl:
A security-aware routing implementation for dynamic data protection in zone-based MPSoC. SBCCI 2017: 59-64 - [c62]Nisha Jacob, Jakob Wittmann, Johann Heyszl, Robert Hesselbarth, Florian Wilde, Michael Pehl, Georg Sigl, Kai Fischer:
Securing FPGA SoC configurations independent of their manufacturers. SoCC 2017: 114-119 - [c61]Markus Stefan Wamser, Georg Sigl:
Pushing the limits further: Sub-atomic AES. VLSI-SoC 2017: 1-6 - [c60]Markus Stefan Wamser, Georg Sigl:
Pushing the Limits Further: Sub-Atomic AES. VLSI-SoC (Selected Papers) 2017: 220-239 - [i7]Nisha Jacob, Johann Heyszl, Andreas Zankl, Carsten Rolfes, Georg Sigl:
How to Break Secure Boot on FPGA SoCs through Malicious Hardware. IACR Cryptol. ePrint Arch. 2017: 625 (2017) - [i6]Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve. IACR Cryptol. ePrint Arch. 2017: 814 (2017) - 2016
- [j8]Manuel Huber, Benjamin Taubmann, Sascha Wessel, Hans P. Reiser, Georg Sigl:
A flexible framework for mobile device forensics based on cold boot attacks. EURASIP J. Inf. Secur. 2016: 17 (2016) - [j7]Stefan Gehrer, Georg Sigl:
Area-Efficient PUF-Based Key Generation on System-on-Chips with FPGAs. J. Circuits Syst. Comput. 25(1): 1640002:1-1640002:20 (2016) - [j6]Matthias Hiller, Meng-Day (Mandel) Yu, Georg Sigl:
Cherry-Picking Reliable PUF Bits With Differential Sequence Coding. IEEE Trans. Inf. Forensics Secur. 11(9): 2065-2076 (2016) - [c59]Fabrizio De Santis, Tobias Bauer, Georg Sigl:
Squeezing Polynomial Masking in Tower Fields - A Higher-Order Masked AES S-Box. CARDIS 2016: 192-208 - [c58]Andreas Zankl, Johann Heyszl, Georg Sigl:
Automated Detection of Instruction Cache Leaks in Modular Exponentiation Software. CARDIS 2016: 228-244 - [c57]Matthias Hiller, Aysun Gurur Önalan, Georg Sigl, Martin Bossert:
Online Reliability Testing for PUF Key Derivation. TrustED@CCS 2016: 15-22 - [c56]Fabrizio De Santis, Tobias Bauer, Georg Sigl:
Hiding Higher-Order Univariate Leakages by Shuffling Polynomial Masking Schemes: A More Efficient, Shuffled, and Higher-Order Masked AES S-box. TIS@CCS 2016: 17-26 - [c55]Oscar M. Guillen, Dawin Schmidt, Georg Sigl:
Practical evaluation of code injection in encrypted firmware updates. DATE 2016: 325-330 - [c54]Robert Hesselbarth, Georg Sigl:
Fast and Reliable PUF Response Evaluation from Unsettled Bistable Rings. DSD 2016: 82-90 - [c53]Philipp Koppermann, Fabrizio De Santis, Johann Heyszl, Georg Sigl:
X25519 Hardware Implementation for Low-Latency Applications. DSD 2016: 99-106 - [c52]Andreas Zankl, Katja Miller, Johann Heyszl, Georg Sigl:
Towards Efficient Evaluation of a Time-Driven Cache Attack on Modern Processors. ESORICS (2) 2016: 3-19 - [c51]Bodo Selmke, Johann Heyszl, Georg Sigl:
Attack on a DFA Protected AES by Simultaneous Laser Fault Injections. FDTC 2016: 36-46 - [c50]Oscar M. Guillen, Fabrizio De Santis, Ralf Brederlow, Georg Sigl:
Towards Side-Channel Secure Firmware Updates - A Minimalist Anomaly Detection Approach. FPS 2016: 345-360 - [c49]Ralph Nyberg, Johann Heyszl, Dietmar Heinz, Georg Sigl:
Enhancing Fault Emulation of Transient Faults by Separating Combinational and Sequential Fault Propagation. ACM Great Lakes Symposium on VLSI 2016: 209-214 - [c48]Vincent Immler, Maxim Hennig, Ludwig Kürzinger, Georg Sigl:
Practical Aspects of Quantization and Tamper-Sensitivity for Physically Obfuscated Keys. CS2@HiPEAC 2016: 13-18 - [c47]Michael Tempelmeier, Fabrizio De Santis, Jens-Peter Kaps, Georg Sigl:
An area-optimized serial implementation of ICEPOLE authenticated encryption schemes. HOST 2016: 49-54 - [c46]Michael Tempelmeier, Georg Sigl:
MaskVer: a tool helping designers detect flawed masking implementations. IVSW 2016: 1-6 - [c45]Johanna Sepúlveda, Daniel Florez, Ramon Fernandes, César A. M. Marcon, Guy Gogniat, Georg Sigl:
Towards risk aware NoCs for data protection in MPSoCs. ReCoSoC 2016: 1-8 - [c44]Ramon Fernandes, César A. M. Marcon, Rodrigo Cataldo, Jarbas Silveira, Georg Sigl, Martha Johanna Sepúlveda:
A security aware routing approach for NoC-based MPSoCs. SBCCI 2016: 1-6 - [c43]Cezar Reinbrecht, Altamiro Amadeu Susin, Lilian Bossuet, Georg Sigl, Martha Johanna Sepúlveda:
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack. SBCCI 2016: 1-6 - [i5]Matthias Hiller, Michael Pehl, Gerhard Kramer, Georg Sigl:
Algebraic Security Analysis of Key Generation with Physical Unclonable Functions. IACR Cryptol. ePrint Arch. 2016: 854 (2016) - 2015
- [j5]Matthias Hiller, Michael Pehl, Georg Sigl:
Fehlerkorrekturverfahren zur sicheren Schlüsselerzeugung mit Physical Unclonable Functions. Datenschutz und Datensicherheit 39(4): 229-233 (2015) - [j4]Ralph Nyberg, Johann Heyszl, Dirk Rabe, Georg Sigl:
Closing the gap between speed and configurability of multi-bit fault emulation environments for security and safety-critical designs. Microprocess. Microsystems 39(8): 1119-1129 (2015) - [c42]