Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Journal of Solid-State Circuits, Volume 58
Volume 58, Number 1, January 2023
- Masum Hossain, Arijit Raychowdhury, Sanu K. Mathew, Yakun Sophia Shao, Yih Wang:
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). 3-7
- Ahmad Khairi, Yoel Krupnik
, Amir Laufer, Yoav Segal, Marco Cusmai, Itamar Levin, Ari Gordon, Yaniv Sabag, Vitali Rahinski, Idan Lotan, Gadi Ori, Noam Familia, Stas Litski, Tali Warshavsky Grafi, Udi Virobnik, Dror Lazar, Yeshayahu Horwitz, Ajay Balankutty, Shiva Kiran, Samuel Palermo, Peng Mike Li, Frank O'Mahony, Ariel Cohen:
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. 8-18 - Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu:
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS. 19-29 - Arian Hashemi Talkhooncheh, Weiwei Zhang, Minwo Wang, David J. Thomson, Martin Ebert, Ke Li, Graham T. Reed, Azita Emami:
A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators. 30-44 - Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen:
A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS. 45-56 - Yu Zhao, Onur Memioglu, Long Kong, Behzad Razavi:
A 56-GHz Fractional-N PLL With 110-fs Jitter. 57-67 - Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe:
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. 68-77 - Suneui Park, Seyeon Yoo, Yuhwan Shin, Jeonghyun Lee, Jaehyouk Choi:
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68. 78-89 - Jae-Gon Lee, Younsik Choi, Hoyeon Jeon, Jong-Jin Lee, Dongsuk Shin:
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC. 90-101 - Brian T. Vanderpool, Phillip J. Restle, Eric Fluhr, Gregory S. Still, Francesco A. Campisano, Ian Charmichael, Eric Marz, Rahul Batra, Richard L. Willaman:
Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. 102-110 - Sumeet Singh Nagi, Uneeb Rathore, Krutikesh Sahoo, Tim Ling, Subramanian S. Iyer, Dejan Markovic:
A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration. 111-123 - Yihong Zhu, Wenping Zhu, Chongyang Li, Min Zhu, Chenchen Deng, Chen Chen, Shuying Yin, Shouyi Yin, Shaojun Wei, Leibo Liu:
RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems. 124-140 - Saurav Maji, Utsav Banerjee, Samuel H. Fuller, Anantha P. Chandrakasan:
A Threshold Implementation-Based Neural Network Accelerator With Power and Electromagnetic Side-Channel Countermeasures. 141-154 - Ji-Soo Chang, Eunsang Jang, Youngkil Choi, Moonkyu Song, Sanghyo Lee, Gi-Jin Kang, Junho Kim, Uijong Song, Chang-Yeon Cho, Giyeong Ko, Hyunseok Hwang, Junseo Lee, Han-Sol Lee, Yong-Il Kwon, Kyungduck Seo, Taeseon Kim, Hyun-Wook Lim, Seongwook Song, Jae-Youl Lee, Sung Ung Kwak:
A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication. 155-166 - Yi-Yen Hsieh, Yu-Cheng Lin, Chia-Hsiang Yang:
A 96.2-nJ/class Neural Signal Processor With Adaptable Intelligence for Seizure Prediction. 167-176 - Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, Hoi-Jun Yoo:
DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC. 177-188 - Jun-Seok Park, Changsoo Park, Suknam Kwon, Taeho Jeon, Yesung Kang, Heonsoo Lee, Dongwoo Lee, James Kim, Hyeong-Seok Kim, YoungJong Lee, Sangkyu Park, MinSeong Kim, Sanghyuck Ha, Jihoon Bang, Jinpyo Park, SukHwan Lim, Inyup Kang:
A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC. 189-202 - Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst:
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. 203-215 - Yuhao Ju, Jie Gu:
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance. 216-226 - Yang Wang, Yubin Qin, Dazheng Deng, Jingchuan Wei, Yang Zhou, Yuanqi Fan, Tianbao Chen, Hao Sun, Leibo Liu, Shaojun Wei, Shouyi Yin:
An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention. 227-242 - Fengbin Tu, Yiqi Wang, Zihan Wu, Ling Liang, Yufei Ding, Bongjin Kim, Leibo Liu, Shaojun Wei, Yuan Xie, Shouyi Yin:
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. 243-255 - Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Ji Hwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Tae-Sik Yun, Young Jun Koo, Jae-Seung Lee, Byung Kuk Yoon, Young Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun-Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae-Hyung Park, Jong Chan Yun, Seonyeol Kim, Dong-Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee, Jieun Jang, Joohwan Cho:
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. 256-269 - Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho:
A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM. 270-278 - Daewoong Lee, Jaehyeok Baek, Hye-Jung Kwon, Daehyun Kwon, Chulhee Cho, Sang-Hoon Kim, Donggun An, Chulsoon Chang, Unhak Lim, Jiyeon Im, Wonju Sung, Hye-Ran Kim, Sun-Young Park, Hyoung-Joo Kim, Ho-Seok Seol, Juhwan Kim, Jung-Bum Shin, Gil-Young Kang, Yong-Hun Kim, Sooyoung Kim, Wansoo Park, Seok-Jung Kim, ChanYong Lee, Seungseob Lee, TaeHoon Park, Chi-Sung Oh, Hyodong Ban, Hyungjong Ko, Hoyoung Song, Tae-Young Oh, SangJoon Hwang, Kyung Suk Oh, Jung-Hwan Choi, Jooyoung Lee:
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. 279-290 - Dae-Han Kwon, Seongju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dongyoon Ka, Kyu-Dong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Nahsung Kim, Yongkee Kwon, Kornijcuk Vladimir, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Guhyun Kim, Byeongju An, Jaewook Lee, Donguc Ko, Younggun Jun, Ilwoong Kim, Choungki Song, Ilkon Kim, Chanwook Park, Seho Kim, Chunseok Jeong, Euicheol Lim, Dongkyun Kim, Jieun Jang, Il Park, Junhyun Chun, Joohwan Cho:
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application. 291-302 - Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. 303-315 - Jonghak Yuh, Yen-Lung Jason Li, Heguang Li, Yoshihiro Oyama, Cynthia Hsu, Pradeep Anantula, Gwang Yeong Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Yap, Demin Wang, Steve Kim, Yonggang Wu, Min Peng, Jason Lu, Tommy Ip, Seema Malhotra, Taekeun Han, Masatoshi Okumura, Jiwen Liu, Jeongduk John Sohn, Hardwell Chibvongodze, Muralikrishna Balaga, Akihiro Matsuda, Chen Chen, Indra K. V, V. S. N. K. Chaitanya G., Venky Ramachandra, Yosuke Kato, Ravi Kumar, Huijuan Wang, Farookh Moogat, In-Soo Yoon, Kazushige Kanda, Takahiro Shimizu, Noboru Shibata, Kosuke Yanagidaira, Takuyo Kodama, Ryo Fukuda, Yasuhiro Hirashima, Mitsuhiro Abe:
A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface. 316-328
Volume 58, Number 2, February 2023
- Dennis Sylvester:
New Associate Editor. 331 - Jiayang Yu, Jixin Chen, Peigen Zhou, Huanbo Li, Zuojun Wang, Zekun Li, Zhe Chen, Pinpin Yan, Debin Hou, Hao Gao, Wei Hong:
A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm PSAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS. 332-344 - Ziyang Luo, Jin Liu, Hoi Lee:
A 40.68-MHz Active Rectifier With Cycle-Based On-/Off-Delay Compensation for High-Current Biomedical Implants. 345-356 - Bingzheng Yang, Huizhen Jenny Qian, Tianyi Wang, Xun Luo:
A CMOS Wideband Watt-Level 4096-QAM Digital Power Amplifier Using Reconfigurable Power-Combining Transformer. 357-370 - Haikun Jia, Pingda Guan, Wei Deng, Zhihua Wang, Baoyong Chi:
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS. 371-385 - Ruixing He, Yahya M. Tousi:
A mm-Wave Signal Generation and Background Phase Alignment Technique for Scalable Arrays. 386-399 - Minjae Kim, Hyun-Su Lee, Jisan Ahn, Hyung-Min Lee:
A 13.56-MHz Wireless Power and Data Transfer System With Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive Voltage Regulation. 400-410 - Wei Deng, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi:
A D-Band Joint Radar-Communication CMOS Transceiver. 411-427 - Shusuke Kawai, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka:
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. 428-438 - Daniel Wendler, Daniel De Dorigo, Mohammad Amayreh, Alexander Bleitner, Maximilian Marx, Roman Willaredt, Yiannos Manoli:
A 0.0046-mm2 Two-Step Incremental Delta-Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation. 439-450 - Xiudeng Wang, Yinshui Xia, Zhangming Zhu, Ge Shi, Huakang Xia, Yidie Ye, Zhidong Chen, Libo Qian, Lianxi Liu:
Configurable Hybrid Energy Synchronous Extraction Interface With Serial Stack Resonance for Multi-Source Energy Harvesting. 451-461 - Chunxiao Hu, Yun Yin, Tong Li, Yangzi Liu, Liang Xiong, Hongtao Xu:
A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS. 462-473 - Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction. 474-485 - Bo-Hao Chen, Tzu-Ying Wu, Kuo-Lin Zheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A Feedforward Controlled Digital Low-Dropout Regulator With Weight Redistribution Algorithm and Body Voltage Control for Improving Line Regulation With 99.99% Current Efficiency and 0.5-mV Output Voltage Ripple. 486-496 - Yong-Hwa Wen, Tz-Wun Wang, Tzu-Hsien Yang, Sheng-Hsi Hung, Kuo-Lin Zheng, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A -10 to -20-V Inverting Buck-Boost Drive GaN Driver With Sub-1-μA Leakage Current Vth Tracking Technique for 20-MHz Depletion-Mode GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. 497-507 - Nahmil Koo, Hyojun Kim, SeongHwan Cho:
A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 Vpp and T-CMRR of 105 dB in 180-nm CMOS. 508-519 - Hsueh-Yen Shen, Yu-Chi Lee, Tzu-Wei Tong, Chia-Hsiang Yang:
A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator. 520-529 - Yuncheng Lu, Van Loi Le, Tony Tae-Hyoung Kim:
A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN. 530-542 - Junjie Mu, Bongjin Kim:
A Dynamic-Precision Bit-Serial Computing Hardware Accelerator for Solving Partial Differential Equations Using Finite Difference Method. 543-553 - Sumon Kumar Bose, Arindam Basu:
A 389 TOPS/W, Always ON Region Proposal Integrated Circuit Using In-Memory Computing in 65 nm CMOS. 554-568 - Thierry Tambe, En-Yu Yang, Glenn G. Ko, Yuji Chai, Coleman Hooper, Marco Donato, Paul N. Whatmough, Alexander M. Rush, David Brooks, Gu-Yeon Wei:
A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs. 569-581
Volume 58, Number 3, March 2023
- Farhana Sheikh, Yan Lu:
Guest Editorial 2022 Custom Integrated Circuits Conference. 587-588 - Xueyong Zhang, Arindam Basu:
A 915-1220 TOPS/W, 976-1301 GOPS Hybrid In-Memory Computing Based Always-On Image Processing for Neuromorphic Vision Sensors. 589-599 - Jaehoon Heo, Junsoo Kim, Sukbin Lim, Wontak Han, Joo-Young Kim:
T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training. 600-613 - Zhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, Hoi-Jun Yoo:
An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache. 614-623 - Xiaofeng Guo, Run Chen, Zhenqi Chen, Bin Li:
A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier. 624-633 - Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino:
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. 634-646 - Zhixian Deng, Changxuan Han, Yifan Li, Huizhen Jenny Qian, Xun Luo:
A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA. 647-661 - Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo:
A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET. 662-676 - Mohammadreza Beikmirza, Yiyu Shen, Leo C. N. de Vreede, Morteza S. Alavi:
A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter. 677-690 - Bingzheng Yang, Huizhen Jenny Qian, Jie Zhou, Yiyang Shu, Xun Luo:
Millimeter-Wave Quadrature Mixed-Mode Transmitter With Distributed Parasitic Canceling and LO Leakage Self-Suppression. 691-704 - Tianshi Xie, Jianglin Zhu, Dragan Maksimovic, Hanh-Phuc Le:
A Highly Integrated Hybrid DC-DC Converter With nH-Scale IPD Inductors. 705-719 - Donghee Cho, Hyungjoo Cho, Sein Oh, Yoontae Jung, Sohmyung Ha, Chul Kim, Minkyu Je:
A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current. 720-731 - Tuur Van Daele, Filip Tavernier:
Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS. 732-741 - Sandeep Reddy Kukunuru, Yashar Naeimi, Loai G. Salem:
A Series-Parallel Switched-Photovoltaic DC-DC Converter. 742-756 - Shenglong Zhuo, Tao Xia, Lei Zhao, Miao Sun, Yifan Wu, Lei Wang, Hengwei Yu, Jiqing Xu, Jier Wang, Zhihong Lin, Yuan Li, Lei Qiu, Rui Bai, Xuefeng Chen, Patrick Yin Chiang:
Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling. 757-770 - Dhruv Patel, Alireza Sharif Bakhtiar, Tony Chan Carusone:
A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes. 771-784 - Yongxin Li, Nilanjan Pal, Tianyu Wang, Mostafa Gamal Ahmed, Ahmed Abdelrahman, Mohamed Badr Younis, Kyu-Sang Park, Ruhao Xia, Pavan Kumar Hanumolu:
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator. 785-795 - Tianxiang Qu, Qinjing Pan, Liheng Liu, Xiaoyang Zeng, Zhiliang Hong, Jiawei Xu:
A 1.8-GΩ Input-Impedance 0.15-μV Input-Referred-Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction. 796-805 - Zhi-Heng Kang, Shen-Iuan Liu:
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation. 806-816 - Soo-Hun Kim, Seong-Min Ko, Dong-Woo Jee:
A Pixelated Monolithic CMOS PPG Sensor for Spatial Feature Acquisition. 817-826 - Yongtae Lee, Byeonghwa Cho, Changuk Lee, Jongbaeg Kim, Youngcheol Chae:
A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution. 827-837 - Qijun Liu, Miguel Jimenez, Maria Eugenia Inda, Arslan Riaz, Timur Zirtiloglu, Anantha P. Chandrakasan, Timothy K. Lu, Giovanni Traverso, Phillip M. Nadeau, Rabia Tugce Yazicigil:
A Threshold-Based Bioluminescence Detector With a CMOS-Integrated Photodiode Array in 65 nm for a Multi-Diagnostic Ingestible Capsule. 838-851 - Ruiqi Guo, Zhiheng Yue, Xin Si, Hao Li, Te Hu, Limei Tang, Yabing Wang, Hao Sun, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin:
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. 852-866 - Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang, Cheng Huang, Hao Cai:
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS. 867-876 - Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. 877-892
Volume 58, Number 4, April 2023
- Dennis Sylvester:
New Associate Editor. 895 - Dennis Sylvester:
New Associate Editor. 896 - Borivoje Nikolic, Mototsugu Hamada:
Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits. 897-900 - Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Yun Wang, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Jeehoon Park, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station. 901-914 - Yimai Peng, Gordy Carichner, Yejoong Kim, Li-Yu Chen, Rémy Tribhout, Benoît Piranda, Julien Bourgeois, David T. Blaauw, Dennis Sylvester:
A High-Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter. 915-928 - Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn:
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. 929-938 - Hanyue Li, Yuting Shen, Eugenio Cantatore, Pieter Harpe:
A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled Gm-C Integrator. 939-948 - Xiaolin Yang, Marco Ballini, Chutham Sawigun, Wen-Yang Hsu, Jan-Willem Weijers, Jan Putzeys, Carolina Mora Lopez:
An AC-Coupled 1st-Order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition. 949-960 - Hyunchul Yoon, Changuk Lee, Taewoong Kim, Yigi Kwon, Youngcheol Chae:
A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier. 961-971 - Amy Whitcombe, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull:
A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW. 972-982 - Kunihiro Hatakeyama, Yu Okubo, Tomohiro Nakagome, Masahiro Makino, Hiroshi Takashima, Takahiro Akutsu, Takehide Sawamoto, Masanori Nagase, Tatsuo Noguchi, Shoji Kawahito:
A Hybrid ToF Image Sensor for Long-Range 3D Depth Measurement Under High Ambient Light Conditions. 983-992 - Wei-Jhih Jian, Wei-Zen Chen:
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration. 993-1001 - Minxiang Gong, Hua Chen, Xin Zhang, Rinkle Jain, Arijit Raychowdhury:
A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer. 1002-1014 - Luya Zhang, Ali M. Niknejad:
GalEPR: A Galvanically Coupled Electron Paramagnetic Resonance Spectrometer for Deep Tissue Hypoxia Diagnosis. 1015-1024 - Subhajit Ray, Peter R. Kinget:
Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification. 1025-1036 - Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton:
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. 1037-1050 - Yesin Ryu, Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong-Ki Kim, Hyochang Kim, Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Suk Han Lee, Kyounghwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong, Sunghwan Jo, Dajung Cho, Sooyoung Kim, Minsu Lee, Hyunho Kim, Minhwan Kim, Jae San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young-Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee:
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. 1051-1061 - Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. 1062-1073 - Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. 1074-1086 - Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl:
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. 1087-1093 - Yuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, Jian-Gang Jimmy Zhu:
Non-Linear CNN-Based Read Channel for Hard Disk Drive With 30% Error Rate Reduction and Sequential 200-Mbits/s Throughput in 28-nm CMOS. 1094-1105 - Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu K. Mathew:
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. 1106-1116 - Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy:
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. 1117-1128 - Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany:
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. 1129-1141