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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 20
Volume 20, Number 1, January 2012
- Craig Schlottmann, David Abramson, Paul E. Hasler:
A MITE-Based Translinear FPAA. 1-9 - Craig Schlottmann, Csaba Petre, Paul E. Hasler:
A High-Level Simulink-Based Tool for FPAA Configuration. 10-18 - Hongbin Sun, Chuanyin Liu, Wei Xu, Jizhong Zhao, Nanning Zheng, Tong Zhang:
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache. 19-28 - Afshin Nourivand, Asim J. Al-Khalili, Yvon Savaria:
Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures. 29-41 - Maurice Meijer, José Pineda de Gyvez:
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits. 42-51 - Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan
, Günhan Dündar:
FISH: Fast Instruction SyntHesis for Custom Processors. 52-65 - Jinwook Jang, Olivier Franza, Wayne P. Burleson:
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees. 66-79 - Kun-Hung Tsai, Shen-Iuan Liu:
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. 80-88 - Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti:
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link. 89-97 - Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun:
Reliability Modeling and Management of Nanophotonic On-Chip Networks. 98-111 - Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic:
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. 112-125 - Geng-Ming Chiu, James Chien-Mo Li:
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores. 126-134 - Mahdi Shabany, P. Glenn Gulak:
A 675 Mbps, 4 × 4 64-QAM K-Best MIMO Detector in 0.13 µm CMOS. 135-147 - Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro:
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications. 148-156 - Faiz-ul Hassan, Wim Vanderbauwhede, Fernando Rodríguez Salazar:
Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops. 157-161 - Maurizio Costagliola, Davide De Caro, Antonio Girardi, Roberto Izzi, Niccolò Rinaldi, M. Spirito, Paolo Spirito:
An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines. 162-166 - Tung-Hua Yeh, Sying-Jyan Wang:
Power-Aware High-Level Synthesis With Clock Skew Management. 167-171 - Irith Pomeranz, Sudhakar M. Reddy:
Resolution of Diagnosis Based on Transition Faults. 172-176 - Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. 176-181 - Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung:
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). 181-186 - Xiaoxia Wu, Wei Zhao, Mark Nakamoto, Chandra Nimmagadda, Durodami Lisk, Sam Gu, Riko Radojcic, Matt Nowak, Yuan Xie:
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs. 186-191 - Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi:
ORION 2.0: A Power-Area Simulator for Interconnection Networks. 191-196
Volume 20, Number 2, February 2012
- Raghavendra Kulkarni, Jusung Kim, Hyung-Joon Jeon, Jianhong Xiao, José Silva-Martínez:
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations. 197-210 - Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Duo Li, Eduardo H. Pacheco, Murli Tirumala, Lingli Wang:
General Parameterized Thermal Modeling for High-Performance Microprocessor Design. 211-224 - Jungseob Lee, Nam Sung Kim:
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG. 225-235 - Xiang Fu, Huawei Li, Xiaowei Li:
Testable Path Selection and Grouping for Faster Than At-Speed Testing. 236-247 - Sang Phill Park, Dongsoo Lee, Kaushik Roy:
Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code. 248-256 - Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel:
AdNoC: Runtime Adaptive Network-on-Chip Architecture. 257-269 - Phi-Hung Pham, Jongsun Park, Phuong Mau, Chulwoo Kim:
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip. 270-283 - Elio Consoli, Gaetano Palumbo, Melita Pennisi:
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops. 284-295 - Ning Chen, Zhiyuan Yan, Maximilien Gadouleau, Ying Wang, Bruce W. Suter:
Rank Metric Decoder Architectures for Random Linear Network Coding With Error Control. 296-309 - Younghoon Lee, Jungsoo Kim, Chong-Min Kyung:
Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated Surveillance Camera. 310-318 - Jaydeep P. Kulkarni, Kaushik Roy:
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. 319-332 - Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits. 333-343 - Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez:
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. 344-356 - Antonis M. Paschalis, Ioannis Voyiatzis, Dimitris Gizopoulos:
Accumulator Based 3-Weight Pattern Generation. 357-361 - Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu:
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme. 361-366 - Yu-Chi Tsao, Ken Choi:
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm. 366-371 - B. Ramkumar, Harish M. Kittur:
Low-Power and Area-Efficient Carry Select Adder. 371-375 - Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo:
A Low-Power Single-Phase Clock Multiband Flexible Divider. 376-380 - Ehsan Pakbaznia, Massoud Pedram:
Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating. 380-385 - Chung-Yi Li, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, Kiwing To:
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. 385-389
Volume 20, Number 3, March 2012
- Jung-Won Han, Kwisung Yoo, Dongmyung Lee, Kangyeob Park, Wonseok Oh, Sung Min Park:
A Low-Power Gigabit CMOS Limiting Amplifier Using Negative Impedance Compensation and Its Application. 393-399 - Muhammad Khurram, S. M. Rezaul Hasan:
A 3-5 GHz Current-Reuse gm-Boosted CG LNA for Ultrawideband in 130 nm CMOS. 400-409 - Stelios Neophytou, Maria K. Michael:
Test Pattern Generation of Relaxed n-Detect Test Sets. 410-423 - Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays. 424-436 - José Luis Núñez-Yáñez, Atukem Nabina, Eddie Hung, George Vafiadis:
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding. 437-448 - M. Anwar Hasan, Ashkan Hosseinzadeh Namin, Christophe Nègre:
Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials. 449-458 - Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. 459-472 - Jai-Ming Lin, Zhi-Xiong Hung:
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems. 473-484 - Iris Hui-Ru Jiang, Hua-Yu Chang:
ECOS: Stable Matching Based Metal-Only ECO Synthesis. 485-497 - Jiying Xue, Yangdong Deng, Zuochang Ye, Hongrui Wang, Liu Yang, Zhiping Yu:
A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization. 498-511 - Koushik Chakraborty, Sanghamitra Roy:
Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs. 512-522 - Atanu Chattopadhyay, Zeljko Zilic:
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks. 523-536 - Jason Helge Anderson, Qiang Wang, Chirag Ravishankar:
Raising FPGA Logic Density Through Synthesis-Inspired Architecture. 537-550 - Xuan Guan, Yunsi Fei, Hai Lin:
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing. 551-563 - Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. 564-568 - Francisco Garcia-Herrero, María José Canet, Javier Valls, Pramod Kumar Meher:
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes. 568-573 - Amine Dehbaoui, Victor Lomné, Thomas Ordas, Lionel Torres, Michel Robert, Philippe Maurine:
Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence. 573-577
Volume 20, Number 4, April 2012
- Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang:
WiT: Optimal Wiring Topology for Electromigration Avoidance. 581-592 - Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin:
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. 593-604 - Mingoo Seok, Scott Hanson, David T. Blaauw, Dennis Sylvester:
Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation. 605-615 - Taniya Siddiqua, Sudhanva Gurumurthi:
Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting. 616-629 - Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi:
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling. 630-642 - Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays. 643-654 - Yuan-Ho Chen, Tsin-Yuan Chang:
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. 655-664 - Chang-Hsin Cheng, Yu Liu, Chun-Lung Hsu:
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications. 665-672 - Ta-Wen Kuan, Jhing-Fa Wang, Jia-Ching Wang, Po-Chuan Lin, Gaung-Hui Gu:
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm. 673-683 - Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre:
Loop Acceleration Exploration for ASIP Architecture. 684-696 - Kai Liu, Evgeniy Belyaev, Jie Guo:
VLSI Architecture of Arithmetic Coder Used in SPIHT. 697-710 - Ang-Chih Hsieh, TingTing Hwang:
TSV Redundancy: Architecture and Design Issues in 3-D IC. 711-722 - Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty:
Physical-Defect Modeling and Optimization for Fault-Insertion Test. 723-736 - Moo-young Kim, Hokyu Lee, Chulwoo Kim:
PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration. 737-741 - Hailong Jiao, Volkan Kursun:
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits. 741-745 - Shao-Chang Huang, Ke-Horng Chen, Weiyao Lin, Zon-Lon Lee, Kun-Wei Chang, Erica Hsu, Wenson Lee, Lin-Fwu Chen, Chris Chun-Hung Lu:
Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality. 746-750 - Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi:
Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron. 750-754 - Jinjin He, Huaping Liu, Zhongfeng Wang, Xinming Huang, Kai Zhang:
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders. 755-759 - Junhui Gu, Jianhui Wu, Danhong Gu, Meng Zhang, Longxing Shi:
All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector. 760-764 - Sang-Hyun Cho, Chang-Kyo Lee, Sang-Gug Lee, Seung-Tak Ryu:
A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm. 765-769 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB). 770-774
Volume 20, Number 5, May 2012
- Songjun Pan, Yu Hu, Xiaowei Li:
IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults. 777-790 - W. Paul Griffin, Anand Raghunathan, Kaushik Roy:
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations. 791-803 - Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. 804-817 - Anson H. T. Tse, David B. Thomas, Wayne Luk:
Design Exploration of Quadrature Methods in Option Pricing. 818-826 - Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki:
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. 827-840 - Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen, Jinn-Shyan Wang:
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security. 841-854 - Fahad Ahmed, Linda Milor:
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells. 855-864 - Boyuan Yan, Sheldon X.-D. Tan, Lingfei Zhou, Jie Chen, Ruijing Shen:
Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports. 865-877 - Tobias Strauch:
Single Cycle Access Structure for Logic Test. 878-891 - Nandish Ashutosh Mehta, Bharadwaj Amrutur:
Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor. 892-901 - Weixun Wang, Prabhat Mishra:
System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems. 902-910 - Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha P. Chandrakasan:
The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage. 911-924 - Saumya Chandra, Anand Raghunathan, Sujit Dey:
Variation-Aware Voltage Level Selection. 925-936 - Cheng-Wen Wei, Sheng-Jie Su, Tian-Sheuan Chang, Shyh-Jye Jou:
Sub µW Noise Reduction for CIC Hearing Aids. 937-947 - Tai-You Lu, Wei-Zen Chen:
A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System. 948-958 - Terng-Yin Hsu, Shau-Yu Cheng:
Low-Complexity Sequential Searcher for Robust Symbol Synchronization in OFDM Systems. 959-963 - Won-Young Lee, Lee-Sup Kim:
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS. 964-968 - Jaehyouk Choi, Woonyun Kim, Kyutae Lim:
A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL. 969-973
Volume 20, Number 6, June 2012
- Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou:
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. 977-988 - Wei-Chih Hsieh, Wei Hwang:
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. 989-1001 - Jianchao Lu, Ying Teng, Baris Taskin:
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs. 1002-1011 - Wei Fei, Hao Yu, Wei Zhang, Kiat Seng Yeo:
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis. 1012-1025 - Irith Pomeranz:
Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs. 1026-1035 - Zhen Wang, Mark G. Karpovsky, Ajay Joshi:
Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes. 1036-1048 - Sheng Wei, Miodrag Potkonjak:
Scalable Hardware Trojan Diagnosis. 1049-1057 - Francisco Barranco, Matteo Tomasi, Javier Díaz, Mauricio Vanegas, Eduardo Ros:
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA. 1058-1067 - Manohar Ayinala, Michael J. Brown, Keshab K. Parhi:
Pipelined Parallel FFT Architectures via Folding Transformation. 1068-1081 - Seok-Hoon Kim, Sung-Eui Yoon, Sang-Hye Chung, Young-Jun Kim, Hong-Yun Kim, Kyusik Chung, Lee-Sup Kim:
A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider. 1082-1093 - Duo Liu, Yi Wang, Zhiwei Qin, Zili Shao, Yong Guan:
A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems. 1094-1107 - Alejandro Valero, Julio Sahuquillo, Vicente Lorente, Salvador Petit, Pedro López, José Duato:
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. 1108-1117 - Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici:
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. 1118-1131 - Yang Zhao, Krishnendu Chakrabarty, Ryan Sturmer, Vamsee K. Pamula:
Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips. 1132-1145 - Sampo Tuuna, Ethiopia Nigussie, Jouni Isoaho, Hannu Tenhunen:
Modeling of Energy Dissipation in RLC Current-Mode Signaling. 1146-1151 - Ming Ming Wong, M. L. Dennis Wong, Asoke K. Nandi, Ismat Hijazin:
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes. 1151-1155 - Irith Pomeranz:
Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage. 1156-1160
Volume 20, Number 7, July 2012
- Chixiang Ma, Hao Cao, Ping Lin:
A Low-Power Low-Cost Design of Primary Synchronization Signal Detection. 1161-1166