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ORCID44th DAC 2007: San Diego, CA, USA
- Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007. IEEE 2007
Keynotes
- Lawrence D. Burns:
Designing a New Automotive DNA. - Oh-Hyun Kwon:
Perspective of the Future Semiconductor Industry: Challenges and Solutions. - Jan M. Rabaey:
Design without Borders - A Tribute to the Legacy of A. Richard Newton.
Trusted Hardware
- Cynthia E. Irvine, Karl N. Levitt:
Trusted Hardware: Can It Be Trustworthy? 1-4 - Steven Trimberger:
Trusted Design in FPGAs. 5-8 - G. Edward Suh
, Srinivas Devadas:
Physical Unclonable Functions for Device Authentication and Secret Key Generation. 9-14 - Kris Tiri:
Side-Channel Attack Pitfalls. 15-20
Panel
- Francine Bacchini, Gregory S. Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada:
Megatrends and EDA 2017. 21-22
Industrial Application of System Level Methods
- Walter H. Tibboel, Víctor Reyes, Martin Klompstra, Dennis Alders:
System-Level Design Flow Based on a Functional Reference for HW and SW. 23-28 - Hiren D. Patel, Sandeep K. Shukla:
Model-driven Validation of SystemC Designs. 29-34 - Bishnupriya Bhattacharya, John Rose, Stuart Swan:
Language Extensions to SystemC: Process Control Constructs. 35-38 - Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya:
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. 39-42
Novel Techniques for Interconnect
- Zhengtao Yu, Xun Liu:
Design of Rotary Clock Based Circuits. 43-48 - Muhammet Mustafa Ozdal:
Escape Routing For Dense Pin Clusters In Integrated Circuits. 49-54 - Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan:
TROY: Track Router with Yield-driven Wire Planning. 55-58 - Min Pan, Chris C. N. Chu:
IPR: An Integrated Placement and Routing Algorithm. 59-62
Formal and Semi-Formal Verification Techniques
- Flavio M. de Paula, Alan J. Hu:
An Effective Guidance Strategy for Abstraction-Guided Simulation. 63-68 - Lovleen Bhatia, Jayesh Gaur, Praveen Tiwari, Raj S. Mitra, Sunil H. Matange:
Leveraging Semi-Formal and Sequential Equivalence Techniques for Multimedia SOC Performance Validation. 69-74 - Jiang Long, Andrew Seawright:
Synthesizing SVA Local Variables for Formal Verification. 75-80
Leakage Power Analysis and Optimization
- De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang:
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. 81-86 - Jie Gu, Sachin S. Sapatnekar, Chris H. Kim:
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift. 87-92 - Khaled R. Heloue, Navid Azizi, Farid N. Najm:
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation. 93-98 - Tao Li, Zhiping Yu:
Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage. 99-102 - Jun Seomun, Jaehyun Kim, Youngsoo Shin:
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits. 103-106
Panel
- Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian:
Making Manufacturing Work For You. 107-108
Energy and Performance Issues in On-Chip Communication Networks
- Ümit Y. Ogras, Radu Marculescu, Puru Choudhary, Diana Marculescu:
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip. 110-115 - Théodore Marescaux, Henk Corporaal:
Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT. 116-121 - Zhonghai Lu, Ming Liu, Axel Jantsch:
Layered Switching for Networks on Chip. 122-127 - Lap-Fai Leung, Chi-Ying Tsui:
Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands. 128-131 - Assaf Shacham, Keren Bergman, Luca P. Carloni:
The Case for Low-Power Photonic Networks on Chip. 132-135
Circuit Simulation
- Shweta Srivastava, Jaijeet S. Roychowdhury:
Interdependent Latch Setup/Hold Time Characterization via Euler-Newton Curve Tracing on State-Transition Equations. 136-141 - Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury:
PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels. 142-147 - Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan:
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. 148-153 - Suwen Yang, Mark R. Greenstreet:
Simulating Improbable Events. 154-157 - Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy:
SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits. 158-161
Signal and Power Delivery Integrity
- Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan:
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. 162-167 - Behnam Amelifard, Massoud Pedram:
Optimal Selection of Voltage Regulator Modules in a Power Delivery Network. 168-173 - Ravikishore Gandikota, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester, Murat R. Becer:
Top-k Aggressors Sets in Delay Noise Analysis. 174-179 - Zhanyuan Jiang, Shiyan Hu, Weiping Shi:
A New Twisted Differential Line Structure in Global Bus Design. 180-183 - Abinash Roy, Noha H. Mahmoud, Masud H. Chowdhury:
Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew. 184-187
Functional Verification of ESL Models
- Moshe Y. Vardi:
Formal Techniques for SystemC Verification; Position Paper. 188-192 - Anmol Mathur, Venkat Krishnaswamy:
Design for Verification in System-level Models and RTL. 193-198 - Atsushi Kasuya, Tesh Tesfaye:
Verification Methodologies in a TLM-to-RTL Design Flow. 199-204 - Alfred Kölbl, Jerry R. Burch, Carl Pixley:
Memory Modeling in ESL-RTL Equivalence Checking. 205-209
Panel
- Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis:
Early Power-Aware Design & Validation: Myth or Reality? 210-211
Memories in Embedded Systems
- Yuan-Hao Chang, Jen-Wei Hsieh, Tei-Wei Kuo:
Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design. 212-217 - Ram Kumar, Akhilesh Singhania, Andrew Castner, Eddie Kohler, Mani B. Srivastava:
A System For Coarse Grained Memory Protection In Tiny Embedded Processors. 218-223 - Hakduran Koc, Mahmut T. Kandemir, Ehat Ercanli, Ozcan Ozturk:
Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors. 224-229 - Liping Xue, Ozcan Ozturk, Mahmut T. Kandemir:
A Memory-Conscious Code Parallelization Scheme. 230-233 - Ann Gordon-Ross, Frank Vahid:
A Self-Tuning Configurable Cache. 234-237
Statistical Techniques for Timing Analysis and Design
- Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques. 238-243 - Zhuo Feng, Peng Li, Yaping Zhan:
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction. 244-249 - Lerong Cheng, Jinjun Xiong, Lei He:
Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation Sources. 250-255 - Amith Singhee, Rob A. Rutenbar:
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. 256-261
Wild and Crazy Ideas (WACI)
- Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz:
Chip Multi-Processor Generator. 262-263 - Stephen A. Edwards, Edward A. Lee:
The Case for the Precision Timed (PRET) Machine. 264-265 - Paul Bogdan, Radu Marculescu:
Quantum-Like Effects in Network-on-Chip Buffers Behavior. 266-267 - Farinaz Koushanfar, Miodrag Potkonjak:
CAD-based Security, Cryptography, and Digital Rights Management. 268-269 - Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester:
Line-End Shortening is Not Always a Failure. 270-271 - Steven P. Levitan:
You Can Get There From Here: Connectivity of Random Graphs on Grids. 272-273 - Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy:
High Performance and Low Power Electronics on Flexible Substrate. 274-275 - Junchen Liu, Ian O'Connor, David Navarro, Frédéric Gaffiot:
Novel CNTFET-based Reconfigurable Logic Gate Design. 276-277
Distributed Computing: Automotive Network Design and Analysis
- Abhijit Davare, Qi Zhu, Marco Di Natale, Claudio Pinello, Sri Kanajan, Alberto L. Sangiovanni-Vincentelli:
Period Optimization for Hard Real-time Distributed Automotive Systems. 278-283 - Andrei Hagiescu, Unmesh D. Bordoloi, Samarjit Chakraborty, Prahladavaradan Sampath, P. Vignesh V. Ganesan, S. Ramesh:
Performance Analysis of FlexRay-based ECU Networks. 284-289 - Juan R. Pimentel, Jason Paskvan:
Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application. 290-293 - Zonghua Gu, Xiuqiang He, Mingxuan Yuan:
Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking. 294-299
Emerging Nanoscale Hybrid Circuits and Architectures
- Wei Zhang, Li Shang, Niraj K. Jha:
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. 300-305 - Hamed F. Dadgour, Kaustav Banerjee:
Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications. 306-311 - Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Robert G. Knobel:
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors. 312-317
Physical Implementation of FPGAs
- Lei Cheng, Deming Chen, Martin D. F. Wong:
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. 318-323 - Tomasz S. Czajkowski, Stephen Dean Brown:
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. 324-329 - Shahin Golshan, Elaheh Bozorgzadeh:
Single-Event-Upset (SEU) Awareness in FPGA Routing. 330-333 - Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits. 334-337
Process Aware Physical Design
- Ruiming Chen, Hai Zhou:
Fast Min-Cost Buffer Insertion under Process Variations. 338-343 - Brian Taylor, Larry T. Pileggi:
Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks. 344-349 - Olivier Rizzo, Hanno Melzner:
Concurrent Wire Spreading, Widening, and Filling. 350-353 - Min-Chun Tsai, Daniel Zhang, Zongwu Tang:
Modeling Litho-Constrained Design Layout. 354-357
Reliable Design and CAD Solutions for Circuit Aging
- Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy:
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement. 358-363 - Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao:
The Impact of NBTI on the Performance of Combinational and Sequential Circuits. 364-369 - Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
NBTI-Aware Synthesis of Digital Circuits. 370-375
Silicon, Safety and Self-Driving Cars
- Hartmut Hiller:
"There Is More Than Moore In Automotive ...". 376 - Leonid B. Goldgeisser, Ernst Christen, Zhichao Deng:
Modeling Safe Operating Area in Hardware Description Languages. 377-382 - Dave Ferguson:
Autonomous Automobiles: Developing Cars That Drive Themselves. 383
Silicon Measurement Correlation to Reliability, Noise and Timing Effects
- Li-C. Wang, Pouria Bastani, Magdy S. Abadir:
Design-Silicon Timing Correlation A Data Mining Perspective. 384-389 - Kip Killpack, Chandramouli V. Kashyap, Eli Chiprout:
Silicon Speedpath Measurement and Feedback into EDA flows. 390-395 - Kanak Agarwal, Sani R. Nassif:
Characterizing Process Variation in Nanometer CMOS. 396-399 - Makoto Nagata:
On-Chip Measurements Complementary to Design Flow for Integrity in SoCs. 400-403
Optimizing Arithmetic and Communication
- Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. 404-409 - Rebecca L. Collins, Luca P. Carloni:
Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System. 410-415 - Jordi Cortadella, Michael Kishinevsky:
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow. 416-419 - Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
Optimization of Area in Digital FIR Filters using Gate-Level Metrics. 420-423
Analog and RF Simulation
- Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram:
Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. 424-429 - Henry H. Y. Chan, Zeljko Zilic:
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. 430-435 - Wei Dong, Peng Li:
Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning. 436-439 - Jaeha Kim, Kevin D. Jones, Mark A. Horowitz:
Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch. 440-443
Panel
- Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil:
TLM: Crossing Over From Buzz To Adoption. 444-445
Panel
- Nick Smith, Andrew Chien, Christopher Hegarty, Walden C. Rhines, Alberto L. Sangiovanni-Vincentelli, Frank Winters:
Electronics: The New Differential in the Automotive Industry. 446
Modern Placement Techniques
- Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu:
MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. 447-452 - Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris C. N. Chu:
RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. 453-458 - Huaizhi Wu, Martin D. F. Wong:
Improving Voltage Assignment by Outlier Detection and Incremental Placement. 459-464 - Mark Po-Hung Lin, Shyh-Chang Lin:
Analog Placement Based on Novel Symmetry-Island Formulation. 465-470
Advances in Embedded Hardware Design
- Raimund Kirner, Martin Schoeberl:
Modeling the Function Cache for Worst-Case Execution Time Analysis. 471-476 - Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin:
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration. 477-482 - Shufu Mao, Tilman Wolf:
Hardware Support for Secure Processing in Embedded Systems. 483-488 - Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran:
RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. 489-492 - Piti Piyachon, Yan Luo:
Compact State Machines for High Performance Pattern Matching. 493-496
Bridging the Gap with Silicon
- Qunzeng Liu, Sachin S. Sapatnekar:
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. 497-502 - Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Robert Trzcinski:
Statistical Framework for Technology-Model-Product Co-Design and Convergence. 503-508 - Ying-Yen Chen, Jing-Jia Liou:
Extraction of Statistical Timing Profiles Using Test Data. 509-514 - Krishnan Sundaresan, Nihar R. Mahapatra:
An Analysis of Timing Violations Due to Spatially Distributed Thermal Effects in Global Wires. 515-520
Practical Solutions for Power-Aware Testing
- Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra:
Scan Test Planning for Power Reduction. 521-526 - Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja:
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. 527-532 - Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram:
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design. 533-538 - Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer:
New Test Data Decompressor for Low Power Applications. 539-544
Virtual Automotive Platforms
- Razvan Racu, Arne Hamann, Rolf Ernst, Kai Richter:
Automotive Software Integration. 545-550 - Marco Di Natale:
Virtual Platforms and Timing Analysis: Status, Challenges and Future Directions. 551-555 - Antal Rajnak, Ajay Kumar:
Computer-aided Architecture Design & Optimized Implementation of Distributed Automotive EE Systems. 556-561
The Future of Interconnects: How Will Billions of Transistors Communicate in the Nanometer Era
- Kerry Bernstein, Paul S. Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steven J. Koester, John Magerlein, Ruchir Puri, Albert M. Young:
Interconnects in the Third Dimension: Design Challenges for 3D ICs. 562-567 - Azad Naeemi, Reza Sarvari, James D. Meindl:
Performance Modeling and Optimization for Single- and Multi-Wall Carbon Nanotube Interconnects. 568-573 - Jaijeet S. Roychowdhury:
Micro-Photonic Interconnects: Characteristics, Possibilities and Limitations. 574-575 - Louis Scheffer:
CAD Implications of New Interconnect Technologies. 576-581