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ORCID55th DAC 2018: San Francisco, CA, USA
- Proceedings of the 55th Annual Design Automation Conference, DAC 2018, San Francisco, CA, USA, June 24-29, 2018. ACM 2018, ISBN 978-1-5386-4114-9
- Hossein Sayadi, Nisarg Patel, Sai Manoj P. D.
, Avesta Sasan, Setareh Rafatirad, Houman Homayoun:
Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification. 1:1-1:6 - Bita Darvish Rouhani, M. Sadegh Riazi, Farinaz Koushanfar:
Deepsecure: scalable provably-secure deep learning. 2:1-2:6 - Song Bian, Masayuki Hiromoto, Takashi Sato:
DWE: decrypting learning with errors with errors. 3:1-3:6 - Weizhe Hua, Zhiru Zhang, G. Edward Suh:
Reverse engineering convolutional neural networks through side-channel information leaks. 4:1-4:6 - Daekyu Park, Donghyun Kang, Young Ik Eom:
OFTL: ordering-aware FTL for maximizing performance of the journaling file system. 5:1-5:6 - Chundong Wang, Sudipta Chattopadhyay:
LAWN: boosting the performance of NVMM file system through reducing write amplification. 6:1-6:6 - Fei Wu, Jiaona Zhou, Shunzhuo Wang, Yajuan Du, Chengmo Yang, Changsheng Xie:
FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs. 7:1-7:6 - Won-Kyung Kang, Sungjoo Yoo:
Dynamic management of key states for reinforcement learning-assisted garbage collection to reduce long tail latency in SSD. 8:1-8:6 - Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang:
WB-trees: a meshed tree representation for FinFET analog layout designs. 9:1-9:6 - Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. 10:1-10:6 - Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Multi-objective bayesian optimization for analog/RF circuit synthesis. 11:1-11:6 - Kaige Jia, Zheyu Liu, Qi Wei, Fei Qiao, Xinjun Liu, Yi Yang, Hua Fan, Huazhong Yang:
Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processors. 12:1-12:6 - Hyeon Uk Sim, Saken Kenzhegulov, Jongeun Lee:
DPS: dynamic precision scaling for stochastic computing-based deep neural networks. 13:1-13:6 - Mateja Putic, Swagath Venkataramani, Schuyler Eldridge, Alper Buyuktosunoglu, Pradip Bose, Mircea Stan:
Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration. 14:1-14:6 - Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, C.-J. Richard Shi:
Exploring the programmability for deep learning processors: from architecture to tensorization. 15:1-15:6 - Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei:
LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. 16:1-16:6 - Brandon Reagen, Udit Gupta, Lillian Pentecost, Paul N. Whatmough, Sae Kyu Lee, Niamh Mulholland, David M. Brooks, Gu-Yeon Wei:
Ares: a framework for quantifying the resilience of deep neural networks. 17:1-17:6 - Zihao Liu, Tao Liu, Wujie Wen, Lei Jiang, Jie Xu, Yanzhi Wang, Gang Quan:
DeepN-JPEG: a deep neural network favorable JPEG-based image compression framework. 18:1-18:6 - Jeff Zhang, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg:
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators. 19:1-19:6 - Sayeh Sharify, Alberto Delmas Lascorz, Kevin Siu, Patrick Judd, Andreas Moshovos:
Loom: exploiting weight and activation precisions to accelerate convolutional neural networks. 20:1-20:6 - Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu:
Parallelizing SRAM arrays with customized bit-cell for binary neural networks. 21:1-21:6 - Mohammad Reza Mahmoodi, Dmitri B. Strukov:
An ultra-low energy internally analog, externally digital vector-matrix multiplier based on NOR flash memory technology. 22:1-22:6 - Lennart Bamberg, Robert Schmidt, Alberto García Ortiz:
Coding approach for low-power 3D interconnects. 23:1-23:6 - Anthony Agnesina, Amanvir Sidana, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta, Sung Kyu Lim:
A novel 3D DRAM memory cube architecture for space applications. 24:1-24:6 - Fulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
A general graph based pessimism reduction framework for design optimization of timing closure. 25:1-25:6 - Grace Li Zhang, Bing Li, Masanori Hashimoto, Ulf Schlichtmann:
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units. 26:1-26:6 - Shaoheng Luo, Cheng Zhuo, Houle Gan:
Noise-aware DVFS transition sequence optimization for battery-powered IoT devices. 27:1-27:6 - Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi:
Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. 28:1-28:6 - Peter Munk, Andreas Abele, Eike Thaden, Arne Nordmann, Rakshith Amarnath, Markus Schweizer, Simon Burton:
Semi-automatic safety analysis and optimization. 29:1-29:6 - Cumhur Erkan Tuncali, James Kapinski, Hisahiro Ito, Jyotirmoy V. Deshmukh:
Reasoning about safety of learning-enabled components in autonomous cyber-physical systems. 30:1-30:6 - Kosuke Watanabe, Eunsuk Kang, Chung-Wei Lin, Shinichi Shiraishi:
Runtime monitoring for safety of intelligent vehicles. 31:1-31:6 - Markus Miettinen, Thien Duc Nguyen, Ahmad-Reza Sadeghi, N. Asokan:
Revisiting context-based authentication in IoT. 32:1-32:6 - Siam U. Hussain, Bita Darvish Rouhani, Mohammad Ghasemzadeh, Farinaz Koushanfar:
MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud servers. 33:1-33:6 - Donghyun Kwon, Kuenwhee Oh, Junmo Park, Seungyong Yang, Yeongpil Cho, Brent ByungHoon Kang, Yunheung Paek:
Hypernel: a hardware-assisted framework for kernel protection without nested paging. 34:1-34:6 - Salessawi Ferede Yitbarek, Todd M. Austin:
Reducing the overhead of authenticated memory encryption using delta encoding and ECC memory. 35:1-35:6 - Andrew B. Kahng:
Reducing time and effort in IC implementation: a roadmap of challenges and solutions. 36:1-36:6 - Shankar Sadasivam, Zhuo Chen, Jinwon Lee, Rajeev Jain:
Efficient reinforcement learning for automating human decision-making in SoC design. 37:1-37:6 - Shubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Pierce Chuang, Leland Chang:
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors. 38:1-38:6 - Majed Valad Beigi, Gokhan Memik:
Thermal-aware optimizations of reRAM-based neuromorphic computing systems. 39:1-39:6 - Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph:
Compiler-guided instruction-level clock scheduling for timing speculative processors. 40:1-40:6 - Yunfei Gu, Dengxue Yan, Vaibhav Verma, Mircea R. Stan, Xuan Zhang:
SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors. 41:1-41:6 - Veni Mohan, Akhilesh Iyer, John Sartori:
Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems. 42:1-42:6 - An Zou, Jingwen Leng, Xin He, Yazhou Zu, Vijay Janapa Reddi, Xuan Zhang:
Efficient and reliable power delivery in voltage-stacked manycore system with hybrid charge-recycling regulators. 43:1-43:6 - Stephan Held, Benjamin Rockel:
Exact algorithms for delay-bounded steiner arborescences. 44:1-44:6 - Run-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang:
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. 45:1-45:6 - Guan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang:
Obstacle-avoiding open-net connector with precise shortest distance estimation. 46:1-46:6 - Chien-Pang Lu, Iris Hui-Ru Jiang:
COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain design. 47:1-47:6 - Aysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat:
A machine learning framework to identify detailed routing short violations from a placed netlist. 48:1-48:6 - Hai-Juan Yu, Yao-Wen Chang:
DSA-friendly detailed routing considering double patterning and DSA template assignments. 49:1-49:6 - Cunxi Yu, Houping Xiao, Giovanni De Micheli:
Developing synthesis flows without human knowledge. 50:1-50:6 - Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton:
Efficient computation of ECO patch functions. 51:1-51:6 - Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic:
Canonical computation without canonical representation. 52:1-52:6 - Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli:
SAT based exact synthesis using DAG topology families. 53:1-53:6 - Sanbao Su, Yi Wu, Weikang Qian:
Efficient batch statistical error estimation for iterative multi-level approximate logic synthesis. 54:1-54:6 - Soheil Hashemi, Hokchhay Tann, Sherief Reda:
BLASYS: approximate logic synthesis using boolean matrix factorization. 55:1-55:6 - Seonbong Kim, Joon-Sung Yang:
Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise system. 56:1-56:6 - Chun-Feng Wu, Ming-Chang Yang, Yuan-Hao Chang:
Improving runtime performance of deduplication system with host-managed SMR storage drives. 57:1-57:6 - Wen Wen, Youtao Zhang, Jun Yang:
Wear leveling for crossbar resistive memory. 58:1-58:6 - Wenqin Huangfu, Shuangchen Li, Xing Hu, Yuan Xie:
RADAR: a 3D-reRAM based DNA alignment accelerator architecture. 59:1-59:6 - Shunning Jiang, Berkin Ilbeyi, Christopher Batten:
Mamba: closing the performance gap in productive hardware development frameworks. 60:1-60:6 - Angie Wang, Paul Rigge, Adam M. Izraelevitz, Chick Markley, Jonathan Bachrach, Borivoje Nikolic:
ACED: a hardware library for generating DSP systems. 61:1-61:6 - Venkata Yaswanth Raparti, Sudeep Pasricha:
PARM: power supply noise aware resource management for NoC based multicore systems in the dark silicon era. 62:1-62:6 - Heba Khdr, Hussam Amrouch, Jörg Henkel:
Aging-constrained performance optimization for multi cores. 63:1-63:6 - Johannes Obermaier, Vincent Immler, Matthias Hiller, Georg Sigl:
A measurement system for capacitive PUF-based security enclosures. 64:1-64:6 - Shaza Zeitouni, David Gens, Ahmad-Reza Sadeghi:
It's hammer time: how to attack (rowhammer-based) DRAM-PUFs. 65:1-65:6 - Younghyun Kim, Yongwoo Lee:
CamPUF: physically unclonable function based on CMOS image sensor fixed pattern noise. 66:1-66:6 - Jack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri:
Tamper-resistant pin-constrained digital microfluidic biochips. 67:1-67:6 - Anil Kanduri, Antonio Miele, Amir M. Rahmani, Pasi Liljeberg, Cristiana Bolchini, Nikil D. Dutt:
Approximation-aware coordinated power/performance management for heterogeneous multi-cores. 68:1-68:6 - Anuj Pathania, Heba Khdr, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
QoS-aware stochastic power management for many-cores. 69:1-69:6 - Geraldo F. Oliveira, Larissa Rozales Gonçalves, Marcelo Brandalero, Antonio Carlos Schneider Beck, Luigi Carro:
Employing classification-based algorithms for general-purpose approximate computing. 70:1-70:6 - Lin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu:
Using imprecise computing for improved non-preemptive real-time scheduling. 71:1-71:6 - Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer:
A modular digital VLSI flow for high-productivity SoC design. 72:1-72:6 - Michael Bedford Taylor:
Basejump STL: systemverilog needs a standard template library for hardware design. 73:1-73:6 - Gage Hills, Daniel Bankman, Bert Moons, Lita Yang, Jake Hillard, Alex Kahng, Rebecca Park, Marian Verhelst, Boris Murmann, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra:
TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs. 74:1-74:10 - Derong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
OPERON: optical-electrical power-efficient route synthesis for on-chip signals. 75:1-75:6 - Subrahmanya Teja, Jaydeep P. Kulkarni:
Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigation. 76:1-76:6 - Amit Ranjan Trivedi, Ahish Shylendra:
Ultralow power acoustic feature-scoring using gaussian I-V transistors. 77:1-77:6 - Hyunsu Chae, Joon-Sung Yang:
Test cost reduction for X-value elimination by scan slice correlation analysis. 78:1-78:6 - Christian Dietrich, Achim Schmider, Oskar Pusz, Guillermo Payá Vayá, Daniel Lohmann:
Cross-layer fault-space pruning for hardware-assisted fault injection. 79:1-79:6 - Farah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrión Schäfer:
A machine learning based hard fault recuperation model for approximate hardware accelerators. 80:1-80:6 - Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha:
SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architectures. 81:1-81:6 - Mark Clark, Avinash Kodi, Razvan C. Bunescu, Ahmed Louri:
LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs. 82:1-82:6 - Rodrigo Cataldo, Ramon Fernandes, Kevin J. M. Martin, Johanna Sepúlveda, Altamiro Amadeu Susin, César A. M. Marcon, Jean-Philippe Diguet:
Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications. 83:1-83:6 - Xianwei Cheng, Yang Zhao, Hui Zhao, Yuan Xie:
Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUs. 84:1-84:6 - Shivam Swami, Joydeep Rakshit, Kartik Mohanram:
STASH: security architecture for smart hybrid memories. 85:1-85:6 - Shivam Swami, Kartik Mohanram:
ACME: advanced counter mode encryption for secure non-volatile memories. 86:1-86:6 - Poovaiah M. Palangappa, Kartik Mohanram:
CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs. 87:1-87:6 - Patrick Cronin, Chengmo Yang, Yongpan Liu:
A collaborative defense against wear out attacks in non-volatile processors. 88:1-88:6 - Sandip Ray, Wen Chen, Rosario Cammarota:
Protecting the supply chain for automotives and IoTs. 89:1-89:4 - Xavier Carpent, Karim Eldefrawy, Norrathep Rattanavipanon, Ahmad-Reza Sadeghi, Gene Tsudik:
Reconciling remote attestation and safety-critical operation on simple IoT devices. 90:1-90:6 - Bo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik:
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. 91:1-91:6 - Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan:
Application level hardware tracing for scaling post-silicon debug. 92:1-92:6 - Haifeng Gu, Mingsong Chen, Tongquan Wei, Li Lei, Fei Xie:
Specification-driven automated conformance checking for virtual prototype and post-silicon designs. 93:1-93:6 - Perry van Wesel, Julien Schmaltz:
Formal micro-architectural analysis of on-chip ring networks. 94:1-94:6 - Hanbin Hu, Qingran Zheng, Ya Wang, Peng Li:
HFMV: hybridizing formal methods and machine learning for verification of analog and mixed-signal circuits. 95:1-95:6 - He-Teng Zhang, Jie-Hong R. Jiang:
Cost-aware patch generation for multi-target function rectification of engineering change orders. 96:1-96:6 - Enrique Díaz, Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla:
Modelling multicore contention on the AURIXTM TC27x. 97:1-97:6 - David Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Cache side-channel attacks and time-predictability in high-performance critical real-time systems. 98:1-98:6 - Mischa Möstl, Rolf Ernst:
Cross-layer dependency analysis with timing dependence graphs. 99:1-99:6 - Matina Maria Trompouki, Leonidas Kosmidis:
Brook auto: high-level certification-friendly programming for GPU-powered automotive systems. 100:1-100:6 - Christine Jakobs, Peter Tröger, Matthias Werner, Philipp Mundhenk, Karsten Schmidt:
Dynamic vehicle software with AUTOCONT. 101:1-101:6 - Artur Mrowca, Thomas Pramsohler, Sebastian Steinhorst, Uwe Baumgarten:
Automated interpretation and reduction of in-vehicle network traces at a large scale. 102:1-102:6 - Ximing Qiao, Xiong Cao, Huanrui Yang, Linghao Song, Hai Li:
Atomlayer: a universal reRAM-based CNN accelerator with atomic layer computation. 103:1-103:6 - Fuqiang Liu, Chenchen Liu:
Towards accurate and high-speed spiking neuromorphic systems with data quantization-aware deep networks. 104:1-104:6 - Shaahin Angizi, Zhezhi He, Adnan Siraj Rakin, Deliang Fan:
CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator. 105:1-105:6 - Peiqi Wang, Yu Ji, Chi Hong, Yongqiang Lyu, Dongsheng Wang, Yuan Xie:
SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory. 106:1-106:6 - Yi Cai, Yujun Lin, Lixue Xia, Xiaoming Chen, Song Han, Yu Wang, Huazhong Yang:
Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsification. 107:1-107:6 - Mohsen Imani, Chenyu Huang, Deqian Kong, Tajana Rosing:
Hierarchical hyperdimensional computing for energy efficient classification. 108:1-108:6 - Shiqi Lian, Yinhe Han, Xiaoming Chen, Ying Wang, Hang Xiao:
Dadu-P: a scalable accelerator for robot motion planning in a dynamic environment. 109:1-109:6 - Hayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda:
Data prediction for response flows in packet processing cache. 110:1-110:6 - Fabio Montagna, Abbas Rahimi, Simone Benatti, Davide Rossi, Luca Benini:
PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platform. 111:1-111:6 - Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang:
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. 112:1-112:6 - Yang Song, Olivier Alavoine, Bill Lin:
SARA: self-aware resource allocation for heterogeneous MPSoCs. 113:1-113:6