default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI Technology and Circuits 2022: Honolulu, HI, USA
- IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. IEEE 2022, ISBN 978-1-6654-9772-5
- Gayle Murdoch, Matin O'Toole, Giulio Marti, Ankit Pokhrel, Diana Tsvetanova, Stefan Decoster, Shreya Kundu, Yusuke Oniki, Arame Thiam, Quoc Toan Le
, Olalla Varela Pedreira, Alicja Lesniewska, Gerardo Martinez-Alanis, Seongho Park, Zsolt Tokei:
First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP. 1-2 - C.-Y. Liao, K.-Y. Hsiang, Z.-F. Lou, H.-C. Tseng, C.-Y. Lin, Z.-X. Li, F.-C. Hsieh, C. C. Wang, F.-S. Chang, W.-C. Ray, Y.-Y. Tseng, Shu-Tong Chang, T. C. Chen, Min-Hung Lee:
Endurance > 1011 Cycling of 3D GAA Nanosheet Ferroelectric FET with Stacked HfZrO2 to Homogenize Corner Field Toward Mitigate Dead Zone for High-Density eNVM. 1-2 - Christopher Patrick, S. C. Song, Irfan Khan, Nader Nikfar, Matt Severson, Shree Pandey, Matt Kaiser, Manav Shah, Pat Lawlor, Deb Marich, Carina Affinito, Rajeev Jain:
From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologies. 1-2 - Zehao Lin, Mengwei Si, Peide D. Ye:
Ultra-Fast Operation of BEOL-Compatible Atomic-Layer-Deposited In2O3 Fe-FETs: Achieving Memory Performance Enhancement with Memory Window of 2.5 V and High Endurance > 109 Cycles without VT Drift Penalty. 1-2 - Martin van den Brink, Anthony Yen, Paul van Wijnen, Michael Lercel, Boudewijn Sluijk:
Holistic Patterning to Advance Semiconductor Manufacturing in the 2020s and Beyond. 3-7 - Wei-Jhih Jian, Wei-Zen Chen:
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrms Resolution with Background Self-Calibration. 8-9 - Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka:
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. 10-11 - Sarthak Sharma, Hao Gao, Gernot Hueber, Andrea Mazzanti:
A Magnetically Coupled Dual-Core 154-GHz Class-F Oscillator with -177.1 FoM and -87 dBc/Hz PN at 1-MHz Offset in a 22-nm FDSOI with Third-Harmonic Extraction. 12-13 - Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie:
A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation. 14-15 - Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany:
A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. 16-17 - Zichen Fan, Hyochan An, Qirui Zhang, Boxun Xu, Li Xu, Chien-Wei Tseng, Yimai Peng, Ang Cao, Bowen Liu, Changwoo Lee, Zhehong Wang, Fanghao Liu, Guanru Wang, Shenghao Jiang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester:
Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating. 18-19 - Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst:
TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge. 20-21 - Steven Hsu, Amit Agarwal, Mark A. Anders, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy, James W. Tschanz, Vivek De:
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. 22-23 - Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang:
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. 24-25 - Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos:
A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. 26-27 - Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. 28-29 - Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, Deog-Kyoon Jeong:
0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link. 30-31 - Paul van der Wagt, Allan Parks, Greg Warwar, Lawrence Choi, Bradley Salz, Shih-Tun Chen, Ron Sartschev, Divyesh Gajjar:
A 9 Gb/s 1.1 Vpp Precision Single-Ended Pin Electronics Driver in 40nm CMOS. 32-33 - Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. 34-35 - Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu:
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. 36-37 - Sangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo:
Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing. 38-39 - Zih-Sing Fu, Yu-Chi Lee, Alex Park, Chia-Hsiang Yang:
A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training. 40-41 - Wen-Cong Huang, I-Ting Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Chia-Hsiang Yang:
A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality. 42-43 - Jubin Kang, Yongjae Park, Jung-Hye Hwang, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim:
A 640×480 Indirect Time-of-Flight Image Sensor with Tetra Pixel Architecture for Tap Mismatch Calibration and Motion Artifact Suppression. 44-45 - Kunihiro Hatakeyama, Yu Okubo, Tomohiro Nakagome, Masahiro Makino, Hiroshi Takashima, Takahiro Akutsu, Takehide Sawamoto, Masanori Nagase, Tatsuo Noguchi, Shoji Kawahito:
A Hybrid Indirect ToF Image Sensor for Long-Range 3D Depth Measurement under High Ambient Light Conditions. 46-47 - Chia-Chi Kuo, Rihito Kuroda:
A 4-Tap CMOS Time-of-Flight Image Sensor with In-pixel Analog Memory Array Achieving 10Kfps High-Speed Range Imaging and Depth Precision Enhancement. 48-49 - Karim Ali Ahmed, Longyang Lin, Praveenakumar Shivappa Salamani, Massimo Alioto:
Imager with Dynamic LSB Adaptation and Ratiometric Readout for Low-Bit Depth 5-μW Peak Power in Purely-Harvested Systems. 50-51 - Kyeongwon Jeong, Gichan Yun, Sohmyung Ha, Minkyu Je:
A 600mVPP-Input-Range 94.5dB-SNDR NS-SAR-Nested DSM with 4th-Order Truncation-Error Shaping and Input-Impedance Boosting for Biosignal Acquisition. 52-53 - Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn:
An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer. 54-55 - Kazunori Hasebe, Shinichirou Etou, Daisuke Miyazaki, Taiki Iguchi, Yuki Yagishita, Mika Takasaki, Takeru Nogamida, Hiroyuki Watanabe, Tomohiro Matsumoto, Yasushi Katayama:
A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques. 56-57 - Hanyue Li, Yuting Shen, Eugenio Cantatore, Pieter Harpe:
A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator. 58-59 - Xiaolin Yang, Marco Ballini, Chutham Sawigun, Wen-Yang Hsu, Jan-Willem Weijers, Jan Putzeys, Carolina Mora Lopez:
A 128-Channel AC-Coupled 1st-order Δ-Δ∑ IC for Neural Signal Acquisition. 60-61 - Can Livanelioglu, Woojun Choi, Donghwan Kim, Jiawei Liao, Rosario M. Incandela, Giorgio Cristiano, Taekwang Jang:
A 0.0014 mm2, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits. 62-63 - Gabriele Atzeni, Jongyup Lim, Jiawei Liao, Alessandro Novello, Jungho Lee, Eunseong Moon, Michael Barrow, Joseph G. Letner, Joseph T. Costello, Samuel R. Nason, Paras R. Patel, Parag G. Patil, Hun-Seok Kim, Cynthia A. Chestek, Jamie Phillips, David T. Blaauw, Taekwang Jang:
A 260×274 μm2 572 nW Neural Recording Micromote Using Near-Infrared Power Transfer and an RF Data Uplink. 64-65 - Omid Ghadami, Hongyu Lu, Matthew R. Chan, Mila Tan, Saeromi Chung, Sang Heon Lee, Matthew T. Holden, Ryan de Ridder, Barry Merriman, Drew A. Hall:
Helix: An Electrochemical CMOS DNA Synthesizer. 66-67 - Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy:
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. 68-69 - Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina:
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra. 70-71 - Qirui Zhang, Hyochan An, Zichen Fan, Zhehong Wang, Ziyun Li, Guanru Wang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester:
A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence. 72-73 - Yu-Chen Lo, Yi-Chung Wu, Chia-Hsiang Yang:
A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing. 74-75 - Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami:
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization. 76-77 - Rahul Gulve, Navid Sarhangnejad, Gairik Dutta, Motasem Sakr, Don Nguyen, Roberto Rangel, Wenzheng Chen, Zhengfan Xia, Mian Wei, Nikita Gusev, Esther Y. H. Lin, Xiaonong Sun, Leo Hanxu, Nikola Katic, Ameer Abdelhadi, Andreas Moshovos, Kiriakos N. Kutulakos, Roman Genov:
A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging. 78-79 - Toshiki Sugimoto, Tuan Thanh Ta, Koichi Kokubun, Satoshi Kondo, Tetsuro Itakura, Hisaaki Katagiri, Yutaka Ota, Mitsuhiro Sengoku, Honam Kwon, Keita Sasaki, Hiroshi Kubota, Kazuhiro Suzuki, Katsuyuki Kimura, Akihide Sai:
1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation. 80-81 - Su-Hyun Han, Bumjun Kim, Seonghyeok Park, Yongjae Park, Jung-Hoon Chun, Jaehyuk Choi, Seong-Jin Kim:
A 100×80 CMOS Flash LiDAR Sensor with 0.0011mm2 In-Pixel Histogramming TDC Based on Analog Counter and Self-Calibrated Single-Slope ADC. 82-83 - Yimai Peng, Seokhyeon Jeong, Kyojin Choo, Yejoong Kim, Li-Yu Chen, Rohit Rothe, Li Xu, Ilya Gurin, Omid Oliaei, Vadim Tsinker, Stephen Bart, Peter Hartwell, David T. Blaauw, Dennis Sylvester:
A 184nW, 121µg/√Hz Noise Floor Triaxial MEMS Accelerometer with Integrated CMOS Readout Circuit and Variation-Compensated High Voltage MEMS Biasing. 84-85 - Byeongwoo Koo, Sunghan Do, Sang-Pil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jung-Ho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET. 86-87 - Hyunchul Yoon, Teawoong Kim, Yigi Kwon, Youngcheol Chae:
A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. 88-89 - Jaehoon Lee, Yong Lim, Jongmi Lee, Taejin Jang, Kwonwoo Kang, Jongpil Cho, Seunghyun Oh, Jongwoo Lee:
A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET. 90-92 - Jia-Ching Wang, Bing-Yang Li, Tai-Haur Kuo:
A 9.8-fJ/conv.-step FoMW 8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators. 92-93 - Ruicong Chen, Hanrui Wang, Anantha P. Chandrakasan, Hae-Seung Lee:
RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience. 94-95 - Michihiro Ide, Yuasa Keito, Sena Kato, Dongwon You, Ashbir Aviat Fadila, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 28-GHz Fully-Passive Retro-Reflective Phased-Array Backscattering Transceiver for 5G Network with 24-GHz Beam-Steered Wireless Power Transfer. 96-97 - Zheng Li, Jian Pang, Yi Zhang, Yudai Yamazaki, Qiaoyu Wang, Peng Luo, Weichu Chen, Yijing Liao, Minzhe Tang, Zhengyan Guo, Yun Wang, Xi Fu, Dongwon You, Naoki Oshima, Shinichi Hori, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station. 98-99 - Athanasios Ramkaj, Adalberto Cantoni, Gabriele Manganaro, Siddharth Devarajan, Michiel Steyaert, Filip Tavernier:
A 30GHz-BW < -57dB-IM3 Direct RF Receiver Analog Front End in 16nm FinFET. 100-101 - Wei Zhu, Ruitao Wang, Jian Zhang, Jiawen Wang, Chenguang Li, Yan Wang:
An Ultra-compact Bidirectional T/R Folded 25.8-39.2GHz Phased-Array Transceiver Front-End with Embedded TX Power Detection/Self-calibration Path Supporting 64-/256-/512-QAM at 28-/39-GHz band for 5G in 65nm CMOS Technology. 102-103 - Ji-Seon Paek, Jeongkwang Lee, Wan Kim, Jun-Suk Bang, Jongwoo Lee:
Fully Integrated 2x2 MIMO Real Simultaneous Dual Band WiFi CMOS Power Amplifiers With a Single Inductor Multiple Output Supply Modulation Technique. 104-105 - Qiankai Cao, Jie Gu:
A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management. 106-107 - Yang Zhao, Ziyun Li, Yonggan Fu, Yongan Zhang, Chaojian Li, Cheng Wan, Haoran You, Shang Wu, Xu Ouyang, Vivek Boominathan, Ashok Veeraraghavan, Yingyan Lin:
i-FlatCam: A 253 FPS, 91.49 µJ/Frame Ultra-Compact Intelligent Lensless Camera for Real-Time and Efficient Eye Tracking in VR/AR. 108-109 - Nail Etkin Can Akkaya, Gary Chan, Hung-Jen Liao, Yih Wang, Jonathan Chang:
A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology. 110-111 - Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni:
Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs. 112-113 - Seungyeob Baik, Taeryoung Seol, Sehwan Lee, Geunha Kim, SeongHwan Cho, Arup K. George, Junghyup Lee:
A 2.54μJ∙ppm2-FOMS Supply- and Temperature-Independent Time-Locked ΔΣ Capacitance-to-Digital Converter in 0.18-μm CMOS. 114-115 - Gabriele Atzeni, Rosario M. Incandela, Youngwoo Ji, Alessandro Novello, Hesam Ghiasi, Giorgio Cristiano, Jiawei Liao, Qiuting Huang, Taekwang Jang:
An Impedance-boosted Switched-capacitor Low-noise Amplifier Achieving 0.4 NEF. 116-117 - You Li, David E. Duarte, Yongping Fan:
A 90.9kS/s, 0.7nJ/conversion Hybrid Temperature Sensor in 4nm-class CMOS. 118-119 - Teruki Someya, Vincent Van Hoek, Jan A. Angevare, Sining Pan, Kofi A. A. Makinwa:
A 210nW BJT-based Temperature Sensor with an Inaccuracy of ±0.15°C (3σ) from -15°C to 85°C. 120-121 - Miguel Urteaga, Zach Griffith, A. Arias-Purdue, A. Carter, Petra Rowell, J. Hacker, B. Brar:
InP HBT Technologies for sub-THz Communications. 122-123 - Youngmin Kim, Hongjong Park, Iljin Lee, Joonhoi Hur, Sangmin Yoo:
High Efficiency 29-/38-GHz Hybrid Transceiver Front-Ends Utilizing Si CMOS and GaAs HEMT for 5G NR Millimeter-Wave Mobile Applications. 124-125 - Qiang Yu, Han Wui Then, Derek Thomson, Jessica C. Chou, Jeffrey Garrett, Iwen Huang, Ibukunoluwa Momson, Surej Ravikumar, Seahee Hwangbo, Alvaro Latorre-Rey, Ananda Roy, Marko Radosavljevic, Michael Beumer, Pratik Koirala, Nicole Thomas, Nityan Nair, Heli Vora, Samuel Bader, Johann Rode, Jonathan Jensen, Said Rami:
5G mmWave Power Amplifier and Low-Noise Amplifier in 300mm GaN-on-Si Technology. 126-127 - Wei Zhu, Jian Zhang, Jiawen Wang, Ruitao Wang, Chenguang Li, Kai Wang, Yan Wang:
A Packaged 90-to-96GHz 16-Element Phased Array with 18.8/15.8dBm Psat/OP1dB, 14.8% TX PAE in 65nm CMOS Process and +51dBm Array EIRP. 128-129 - Yesin Ryu, Young-Cheon Kwon, Jaehoon Lee, Sung-Gi Ahn, Jaewon Park, Kijun Lee, Yu Ho Choi, Han-Won Cho, Jae San Kim, Jungyu Lee, Haesuk Lee, Seung Ho Song, Je-Min Ryu, Yeong Ho Yun, Useung Shin, Dajung Cho, Jeong Hoan Park, Jae-Seung Jeong, Sukhan Lee, Kyounghwan Lim, Tae-Sung Kim, Kyungmin Kim, Yu Jin Cha, Ik Joo Lee, Tae Kyu Byun, Han Sik Yoo, Yeong Geol Song, Myung-Kyu Lee, Sunghye Cho, Sung-Rae Kim, Ji-Min Choi, Hyoungmin Kim, Soo Young Kim, Jaeyoun Youn, Myeong-O. Kim, Kyomin Sohn, SangJoon Hwang, JooYoung Lee:
A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. 130-131 - Hyunjin Shin, Sangkyung Won, Dohui Kim, Byunghun Choi, Gyusung Kim, Myeonghee Oh, Jaeseung Choi, Jongwook Kye:
A 32Mb Embedded Flash Memory based on 28nm with the best Cell Efficiency and Robust Design achievement featuring 13.48Mb/mm2 at 0.85V. 132-133 - Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono:
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C. 134-135 - Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni:
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. 136-137 - Raghavan Kumar, Vikram B. Suresh, Sachin Taneja, Mark A. Anders, Steven Hsu, Amit Agarwal, Vivek De, Sanu Mathew:
A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS. 138-139 - Hui Zhang, Longyang Lin, Qiang Fang, Massimo Alioto:
On-Chip Laser Voltage Probing Attack Detection with 100% Area Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design. 140-141 - Kyung-Hoon Lee, Jinwoo Park, Younghyo Park, Byeongwoo Koo, Sunghan Do, Woongtaek Lim, Sungno Lee, Hyochul Shin, Eunhye Oh, Youngjae Cho, Michael Choi, Jongshin Shin:
An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application. 142-143 - Viveka Konandur Rajanna, Himadri Singh Raghav, Tianqi Wang, Massimo Alioto:
Fully-Digital Broadband Calibration-Less Impedance Monitor for Probe Insertion Detection against Power Analysis Attacks. 144-145 - Sanquan Song, Stephen G. Tell, Brian Zimmer, Sudhir S. Kudva, Nikola Nedovic, C. Thomas Gray:
An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process. 146-147 - Hyunsub Norbert Rie, Chang Soo Yoon, Jindo Byun, Sucheol Lee, Garam Kim, Joohwan Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, Minsu Jung, Go-Eun Cha, Minjae Lee, YoungMin Kim, Byeori Han, Yuseong Jeon, Jisun Lee, EunSeok Shin, Hyuk-Jun Kwon, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko:
A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application. 148-149 - Jung-Hun Park, Kwang-Hoon Lee, Yongjae Lee, Jung-Woo Sull, Yoonho Song, Sanghee Lee, Hyeonseok Lee, Hoyeon Cho, Jonghyun Oh, Han-Gon Ko, Deog-Kyoon Jeong:
A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. 150-151 - Ji-Young Kim, Taeryeong Kim, Jeonghyeok You, Ki-Ryong Kim, Byoung-Mo Moon, Kyomin Sohn, Seong-Ook Jung:
A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. 152-153 - Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. 154-155 - Woohyun Kwon, Hyosup Won, Taeho Kim, Ha-Il Song, Hanho Choi, Sejun Jeon, Soon-Won Kwon, Huxian Jin, Jun-Gi Jo, Tai Young Kim, Jake Eu, Jinho Park, Hyeon-Min Bae:
A 25.78125Gbps Bi-directional Transceiver with Framed-Pulsewidth Modulation (FPWM) for Extended Reach Optical Links in 28nm CMOS. 156-157 - Yimai Peng, Gordy Carichner, Yejoong Kim, Li-Yu Chen, Rémy Tribhout, Benoît Piranda, Julien Bourgeois, David T. Blaauw, Dennis Sylvester:
A 286nW, 103V High Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter. 158-159 - Fu-Bin Yang, Dao-Han Yao, Po-Hung Chen:
A Shared-Inductor Structure-Reconfigurable Regulating Rectifier (SR-RR) Enabling 6.78-MHz AC-DC Rectification and 1-MHz DC-DC Energy Recycling. 160-161 - Jun-Chau Chien, Zong-Jun Cheng, Shu-Yan Chuang, Hsiu-Cheng Yeh, Guan-Yu Huang, Hung-Yu Hou, Yi-Ting Chen, Wei-Yang Weng, Chi-Yang Tseng, Liang-In Lin:
A Scalable Standing-Wave-Oscillator-based Imager with Near-Field-Modulated Pixels Achieving 64% Filling Factor for RF Intraoperative Imaging. 162-163 - Changgui Yang, Yunshan Zhang, Ziyi Chang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao:
A 0.4mm3 Battery-Less Crystal-Less Neural-Recording SoC Achieving 1.6cm Backscattering Range with 2mm×2mm On-Chip Antenna. 164-165 - Kyunghyun Son, Dongjae Shin, Jisan Lee, Bongyong Jang, Dongsik Shim, Hyunil Byun, Chang-Bum Lee, Yongchul Cho, Tatsuhiro Otsuka, Changgyun Shin, Inoh Hwang, Eunkyung Lee, Kyoungho Ha, Hyuck Choo:
Palm-sized LiDAR module with III/V-on-Si optical phased array. 166-167 - Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. 168-169 - Amy Whitcombe, Chun C. Lee, Asma Kuriparambil Thekkumpate, Somnath Kundu, Jaykant Timbadiya, Abhishek Agrawal, Brent R. Carlton, Peter Sagazio, Stefano Pellerano, Christopher D. Hull:
A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW. 170-171 - Kyoung-Jun Moon, Dong-Ryeol Oh, Young-Hyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sung-No Lee, Hee-Chang Hwang, Hyo-Chul Shin, Young-Jae Cho, Michael Choi, Jongshin Shin:
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. 172-173 - Dong-Jin Chang, Seung-Tak Ryu:
A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs. 174-175 - Minxiang Gong, Xin Zhang, Arijit Raychowdhury:
A 90.4% Peak Efficiency 48V/1V Three-Level Hybrid Dickson Converter with Gradient Descent Run-Time Optimizer and GaN/Si Hybrid Conversion. 176-177 - Yuanqing Huang, Yogesh Ramadass, Dongsheng Brian Ma:
A 90.7% 4-W 3P4S Hybrid Switching Converter Using Adaptive VCF Rebalancing Technique and Switching Node Dual-Edge tdead Modulation for Extreme 48V/1V Direct DC-DC Conversion. 178-179 - Gyeong-Gu Kang, Ji-Hun Lee, Se-Un Shin, Gyu-Hyeong Cho, Hyun-Sik Kim:
A 5.6W-Power 96.6%-Efficiency Boost-Oriented SIDO Step-Up/Down DC-DC Converter Embedding Buck Conversion with an Energy-Balancing Capacitor. 180-181 - Hyun-Ki Han, Min-Woo Ko, Jeong-Hyun Cho, Gyeong-Gu Kang, Seok-Tae Koh, Hong-Hyun Bae, Hyun-Sik Kim:
A Monolithic 48V-to-1V 10A Quadruple Step-Down DC-DC Converter with Hysteretic Copied On-Time 4-Phase Control and 2× Slew Rate All-Hysteretic Mode. 182-183 - Subhajit Ray, Peter R. Kinget:
A 31-Feature, 80nW, 0.53mm2 Audio Analog Feature Extractor based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification. 184-185 - Naoaki Nishimura, Atsushi Matamura, Preston Birdsong, Shaolong Liu, Abhishek Bandyopadhyay, Mariana T. Markova, Rajeev Morajkar:
Common-mode Stable Multilevel Output Stage with EMI Reduction Feedback Loop for Class-D audio Amplifier. 186-187