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Paul Kwon
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2020 – today
- 2024
- [c2]Zhongkai Wang, Minsoo Choi, Paul Kwon, Zhaokai Liu, Bozhi Yin, Kyoungtae Lee, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS. ISCAS 2024: 1-5 - 2022
- [j1]Kunmo Kim, Paul Kwon, Elad Alon:
Accurate Statistical BER Analysis of DFE Error Propagation in the Presence of Residual ISI. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 619-623 (2022) - [c1]Zhongkai Wang, Minsoo Choi, Paul Kwon, Kyoungtae Lee, Bozhi Yin, Zhaokai Liu, Kwanseo Park, Ayan Biswas, Jaeduk Han, Sijun Du, Elad Alon:
A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology. VLSI Technology and Circuits 2022: 34-35
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last updated on 2024-07-16 22:28 CEST by the dblp team
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