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"A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking ..."

Aida Varzaghani et al. (2022)

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DOI: 10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830304

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  dblp key:
  - conf/vlsit/VarzaghaniBLGYE22
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  - https://dblp.org/rec/conf/vlsit/VarzaghaniBLGYE22
Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos:
A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. VLSI Technology and Circuits 2022: 26-27

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