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ORCIDJan Craninckx
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- affiliation: imec, Leuven, Belgium
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2020 – today
- 2022
[j70]Jorge Lagos
, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx:
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits 57(4): 1112-1124 (2022)- [j69]Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits 57(6): 1673-1683 (2022) - [j68]Anirudh Kankuppe, Sehoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Siddhartha Sinha, Piet Wambacq, Jan Craninckx:
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS. IEEE J. Solid State Circuits 57(7): 1982-1996 (2022) - [j67]Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx:
Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS. IEEE J. Solid State Circuits 57(7): 1997-2010 (2022) - [j66]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57(7): 2068-2077 (2022) - [j65]Sehoon Park, Dae-Woong Park, Kristof Vaesen, Anirudh Kankuppe, Siddhartha Sinha, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS. IEEE J. Solid State Circuits 57(7): 2114-2129 (2022) - [j64]Xiaohua Huang, Marco Ballini, Shiwei Wang, Beatrice Miccoli, Chris Van Hoof, Georges G. E. Gielen, Jan Craninckx, Nick Van Helleputte, Carolina Mora Lopez:
A Compact, Low-Power Analog Front-End With Event-Driven Input Biasing for High-Density Neural Recording in 22-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 804-808 (2022) - [c92]Steven Van Winckel, Alican Çaglar, Benjamin Gys, Steven Brebels, Anton Potocnik, Bertrand Parvais, Piet Wambacq, Jan Craninckx:
A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout. ESSCIRC 2022: 61-64 - [c91]Rohith Acharya, Anton Potocnik, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu:
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. VLSI Technology and Circuits 2022: 230-231 - 2021
- [j63]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits 56(4): 1227-1240 (2021) - [j62]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits 56(8): 2360-2374 (2021) - [j61]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2813-2826 (2021) - [j60]Keigo Bunsen, Ewout Martens, Davide Dermit, Jan Craninckx:
A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 592-596 (2021) - [c90]Alican Çaglar, Steven Van Winckel, Steven Brebels, Piet Wambacq, Jan Craninckx:
A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout. A-SSCC 2021: 1-3 - [c89]Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC 2021: 207-210 - [c88]Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx:
A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS. ESSCIRC 2021: 295-298 - [c87]Anirudh Kankuppe, Sehoon Park, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS. ESSCIRC 2021: 471-474 - [c86]Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx:
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. ISCAS 2021: 1-5 - [c85]Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx:
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits 2021: 1-2 - [c84]Ewout Martens, Davide Dermit, Mithlesh Shrivas, Shun Nagata, Jan Craninckx:
A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW. VLSI Circuits 2021: 1-2 - [c83]Iuliana P. Radu, Roy Li, Anton Potocnik, Tsvetan Ivanov, Danny Wan, Stefan Kubicek, Nard I. Dumoulin Stuyck, Jeroen Verjauw, Julien Jussot, Yann Canvel, Clement Godfrin, Massimo Mongillo, Rohith Acharya, Asser Elsayed, Mohamed Shehata, Xiaoyu Piao, Antoine Pacco, Laurent Souriau, Sebastien Couet, B. T. Chan, Jan Craninckx, Bertrand Parvais, Alexander Grill, Subramanian Narasimhamoorthy, Steven Van Winckel, Steven Brebels, Fahd A. Mohiyaddin, George Simion, Bogdan Govoreanu:
Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing. VLSI Circuits 2021: 1-2 - [c82]Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. VLSI Circuits 2021: 1-2 - 2020
- [j59]Cheng-Hsueh Tsai, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq:
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE J. Solid State Circuits 55(7): 1854-1863 (2020) - [j58]Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx:
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits 55(12): 3294-3307 (2020) - [c81]Toshio Yasue, Fortunato Frazzica, Annachiara Spagnolo, David San Segundo Bello, Maarten De Bock, Piet Wambacq, Jan Craninckx:
A 1st Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC. IEEE SENSORS 2020: 1-4 - [c80]Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC 2020: 254-256 - [c79]Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx:
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC 2020: 278-280 - [c78]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j57]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54(2): 403-416 (2019) - [j56]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54(3): 646-658 (2019) - [j55]Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits 54(4): 1059-1073 (2019) - [j54]Jan Craninckx:
New Associate Editors. IEEE J. Solid State Circuits 54(6): 1515-1516 (2019) - [j53]Jan Craninckx:
Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 54(8): 2107 (2019) - [j52]Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx:
A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth. IEEE J. Solid State Circuits 54(12): 3503-3512 (2019) - [j51]Shiwei Wang, Carolina Mora Lopez, Seyed Kasra Garakoui, Ho Sung Chun, Didac Gomez Salinas, Wim Sijbers, Jan Putzeys, Ewout Martens, Jan Craninckx, Nick Van Helleputte:
A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels. IEEE Trans. Biomed. Circuits Syst. 13(6): 1625-1634 (2019) - [c77]Aritra Banerjee, Kristof Vaesen, Akshay Visweswaran, Khaled Khalaf, Qixian Shi, Steven Brebels, Davide Guermandi, Cheng-Hsueh Tsai, Johan Nguyen, Alaa Medra, Yao Liu, Giovanni Mangraviti, Orges Furxhi, Bert Gyselinckx, André Bourdoux, Jan Craninckx, Piet Wambacq:
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). CICC 2019: 1-11 - [c76]Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq:
A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter. ESSCIRC 2019: 111-114 - [c75]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC 2019: 58-60 - [c74]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC 2019: 68-70 - [c73]Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx:
A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error. ISSCC 2019: 408-410 - 2018
- [j50]Jan Craninckx:
New Associate Editors. IEEE J. Solid State Circuits 53(4): 963-964 (2018) - [j49]Ewout Martens, Benjamin P. Hershberg, Jan Craninckx:
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits 53(4): 1161-1171 (2018) - [j48]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 53(5): 1243 (2018) - [j47]Gengzhen Qi, Barend van Liempd, Pui-In Mak, Rui Paulo Martins, Jan Craninckx:
A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA. IEEE J. Solid State Circuits 53(5): 1431-1442 (2018) - [j46]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 53(7): 1875 (2018) - [j45]Lin-Kun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans:
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. Sensors 18(11): 3683 (2018) - [c72]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC 2018: 1-4 - [c71]Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits 2018: 215-216 - 2017
- [j44]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 52(4): 887 (2017) - [j43]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 52(7): 1699 (2017) - [j42]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 52(9): 2223 (2017) - [j41]John R. Long, Jan Craninckx, Behzad Razavi:
Introducing Our Sister Publication: IEEE Solid-State Circuits Letters. IEEE J. Solid State Circuits 52(10): 2519-2520 (2017) - [j40]Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx, Wim Van Thillo:
A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. IEEE J. Solid State Circuits 52(10): 2613-2626 (2017) - [c70]Mark Ingels, Davide Dermit, Yao Liu, Hans Cappelle, Jan Craninckx:
A 2×14bit digital transmitter with memoryless current unit cells and integrated AM/PM calibration. ESSCIRC 2017: 324-327 - [c69]Alyosha C. Molnar, Jan Craninckx, Aarno Pärssinen:
Session 18 overview: Full duplex wireless front-ends. ISSCC 2017: 312-313 - [c68]Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx:
F2: High-performance frequency generation for wireless and wireline systems. ISSCC 2017: 503-505 - 2016
- [j39]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits 51(7): 1593-1606 (2016) - [j38]Jan Craninckx:
Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits 51(8): 1732 (2016) - [j37]Jan Craninckx:
50th Anniversary of the Journal. IEEE J. Solid State Circuits 51(11): 2519 (2016) - [j36]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits 51(12): 3078-3092 (2016) - [c67]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC 2016: 176-177 - [c66]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. ISSCC 2016: 250-252 - [c65]Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx:
20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC 2016: 356-357 - [c64]Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic:
F3: Radio architectures and circuits towards 5G. ISSCC 2016: 498-501 - [c63]Harish Krishnaswamy, Jan Craninckx, Tae Wook Kim:
EE2: Do we need to downscale our radios below 20nm? ISSCC 2016: 519 - [c62]Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx:
A Fractional-n subsampling PLL based on a digital-to-time converter. MIPRO 2016: 66-71 - 2015
- [j35]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". IEEE J. Solid State Circuits 50(2): 619 (2015) - [j34]Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx:
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. IEEE J. Solid State Circuits 50(5): 1203-1213 (2015) - [j33]Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx:
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits 50(9): 2002-2011 (2015) - [j32]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. IEEE J. Solid State Circuits 50(12): 3065-3076 (2015) - [j31]Chunshu Li, Min Li, Khaled Khalaf, André Bourdoux, Marian Verhelst, Mark Ingels, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre, Sofie Pollin:
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. J. Signal Process. Syst. 78(1): 5-19 (2015) - [c61]Qixian Shi, Davide Guermandi, Jan Craninckx, Piet Wambacq:
Flicker noise upconversion mechanisms in K-band CMOS VCOs. A-SSCC 2015: 1-4 - [c60]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. ESSCIRC 2015: 80-83 - [c59]Björn Debaillie, Barend van Liempd, Benjamin P. Hershberg, Jan Craninckx, Kari Rikkinen, D. J. van den Broek, Eric A. M. Klumperink, Bram Nauta:
In-band full-duplex transceiver technology for 5G mobile networks. ESSCIRC 2015: 84-87 - [c58]Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx:
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC 2015: 164-167 - [c57]Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx:
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC 2015: 176-179 - [c56]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. ISSCC 2015: 1-3 - [c55]Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx:
2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. ISSCC 2015: 1-3 - 2014
- [j30]Björn Debaillie, Dirk-Jan van den Broek, Cristina Lavin, Barend van Liempd, Eric A. M. Klumperink, Carmen Palacios, Jan Craninckx, Bram Nauta, Aarno Pärssinen:
Analog/RF Solutions Enabling Compact Full-Duplex Radios. IEEE J. Sel. Areas Commun. 32(9): 1662-1673 (2014) - [j29]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. IEEE J. Solid State Circuits 49(5): 1173-1183 (2014) - [j28]Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx:
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits 49(8): 1815-1826 (2014) - [c54]Mina Mikhael, Barend van Liempd, Jan Craninckx, Rafik Guindi, Björn Debaillie:
A Full-Duplex Transceiver Prototype with In-System Automated Tuning of the RF Self-Interference Cancellation. 5GU 2014: 110-115 - [c53]Barend van Liempd, Björn Debaillie, Jan Craninckx, Cristina Lavin, Carmen Palacios, S. Malotaux, John R. Long, D. J. van den Broek, Eric A. M. Klumperink:
RF self-interference cancellation for full-duplex. CrownCom 2014: 526-531 - [c52]Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx:
A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. ESSCIRC 2014: 79-82 - [c51]Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx:
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. ESSCIRC 2014: 83-86 - [c50]Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx:
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. ESSCIRC 2014: 215-218 - [c49]Mark Ingels, Xiaoqiang Zhang, Kuba Raczkowski, Sungwoo Cha, Pieter Palmers, Jan Craninckx:
A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3. ESSCIRC 2014: 379-382 - [c48]Barend van Liempd, Jan Craninckx, R. Singh, Patrick Reynaert, S. Malotaux, John R. Long:
A dual-notch +27dBm Tx-power electrical-balance duplexer. ESSCIRC 2014: 463-466 - [c47]Vito Giannini, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx, Piet Wambacq:
14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. ISSCC 2014: 250-251 - [c46]Bob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx:
A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. VLSIC 2014: 1-2 - 2013
- [j27]Vincenzo Chironi, Björn Debaillie, Stefano D'Amico, Andrea Baschirotto, Jan Craninckx, Mark Ingels:
A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 918-925 (2013) - [c45]Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx:
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. CICC 2013: 1-4 - [c44]Mark Ingels, Yoshikazu Furuta, Xiaoqiang Zhang, Sungwoo Cha, Jan Craninckx:
A multiband 40nm CMOS LTE SAW-less modulator with -60dBc C-IM3. ISSCC 2013: 338-339 - [c43]Min Li, Khaled Khalaf, Chunshu Li, Vojkan Vidojkovic, Mark Ingels, André Bourdoux, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre:
Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited). SiPS 2013: 324-329 - 2012
- [j26]Jan Craninckx:
CMOS software-defined radio transceivers: Analog design in digital technology. IEEE Commun. Mag. 50(4): 136-144 (2012) - [j25]Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits 47(4): 990-1002 (2012) - [j24]Bob Verbruggen, Masao Iriguchi, Jan Craninckx:
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 47(12): 2880-2887 (2012) - [j23]Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas:
A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 80-92 (2012) - [c42]Peng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen:
Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping. DATE 2012: 1215-1220 - [c41]Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels:
A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors. ESSCIRC 2012: 341-344 - [c40]Bob Verbruggen, Masao Iriguchi, Jan Craninckx:
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. ISSCC 2012: 466-468 - [c39]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. ISSCC 2012: 470-472 - 2011
- [j22]Jonathan Borremans, Gunjan Mandal, Vito Giannini, Björn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx:
A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers. IEEE J. Solid State Circuits 46(7): 1659-1671 (2011) - [c38]Mark Ingels, Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx:
An impedance modulated class-E polar amplifier in 90 nm CMOS. A-SSCC