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Jan Craninckx
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- affiliation: imec, Leuven, Belgium
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2020 – today
- 2024
- [j75]Pratap Tumkur Renukaswamy
, Kristof Vaesen, Nereo Markulic
, Jan Craninckx
:
A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL. IEEE J. Solid State Circuits 59(6): 1684-1696 (2024) - [c100]Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx:
22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC 2024: 396-398 - 2023
- [j74]Alican Çaglar
, Steven Van Winckel
, Steven Brebels
, Piet Wambacq
, Jan Craninckx
:
Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout. IEEE J. Solid State Circuits 58(6): 1586-1596 (2023) - [j73]Lai Wei
, Zihao Zheng, Nereo Markulic
, Jorge Lagos
, Ewout Martens
, Rui Paulo Martins
, Yan Zhu, Jan Craninckx
, Chi-Hang Chan
:
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4679-4691 (2023) - [c99]Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx:
Calibration Techniques for Optimizing Performance of High-Speed ADCs. CICC 2023: 1-8 - [c98]Sriram Balamurali, Giovanni Mangraviti, Zhiwei Zhong, Piet Wambacq, Jan Craninckx:
A 13-16 GHz Low-Noise Oscillator with Enhanced Tank Energy in 22-nm FDSOI. ESSCIRC 2023: 125-128 - [c97]Lucas Moura Santana
, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx:
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC 2023: 389-392 - [c96]Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx:
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. ISSCC 2023: 74-75 - [c95]Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx:
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. MWSCAS 2023: 895-899 - 2022
- [j72]Jorge Lagos
, Nereo Markulic
, Benjamin P. Hershberg
, Davide Dermit
, Mithlesh Shrivas
, Ewout Martens
, Jan Craninckx
:
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits 57(4): 1112-1124 (2022) - [j71]Zihao Zheng, Lai Wei, Jorge Lagos
, Ewout Martens
, Yan Zhu
, Chi-Hang Chan
, Jan Craninckx
, Rui Paulo Martins
:
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits 57(6): 1673-1683 (2022) - [j70]Anirudh Kankuppe
, Sehoon Park
, Kristof Vaesen, Dae-Woong Park, Barend van Liempd
, Siddhartha Sinha
, Piet Wambacq
, Jan Craninckx
:
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS. IEEE J. Solid State Circuits 57(7): 1982-1996 (2022) - [j69]Sriram Balamurali
, Giovanni Mangraviti
, Cheng-Hsueh Tsai
, Piet Wambacq
, Jan Craninckx
:
Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS. IEEE J. Solid State Circuits 57(7): 1997-2010 (2022) - [j68]Lucas Moura Santana
, Ewout Martens
, Jorge Lagos
, Benjamin P. Hershberg
, Piet Wambacq
, Jan Craninckx
:
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57(7): 2068-2077 (2022) - [j67]Sehoon Park
, Dae-Woong Park
, Kristof Vaesen, Anirudh Kankuppe
, Siddhartha Sinha
, Barend van Liempd
, Piet Wambacq
, Jan Craninckx
:
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS. IEEE J. Solid State Circuits 57(7): 2114-2129 (2022) - [j66]Xiaohua Huang
, Marco Ballini
, Shiwei Wang
, Beatrice Miccoli, Chris Van Hoof
, Georges G. E. Gielen
, Jan Craninckx
, Nick Van Helleputte
, Carolina Mora Lopez
:
A Compact, Low-Power Analog Front-End With Event-Driven Input Biasing for High-Density Neural Recording in 22-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 804-808 (2022) - [c94]Steven Van Winckel
, Alican Çaglar
, Benjamin Gys
, Steven Brebels, Anton Potocnik
, Bertrand Parvais
, Piet Wambacq, Jan Craninckx:
A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout. ESSCIRC 2022: 61-64 - [c93]Rohith Acharya, Anton Potocnik
, Steven Brebels, Alexander Grill, Jeroen Verjauw, Tsvetan Ivanov, Daniel Perez Lozano, Danny Wan, Fahd A. Mohiyaddin, Jacques Van Damme, A. M. Vadiraj, Massimo Mongillo
, Georges G. E. Gielen, Francky Catthoor, Jan Craninckx, Iuliana P. Radu, Bogdan Govoreanu:
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements. VLSI Technology and Circuits 2022: 230-231 - 2021
- [j65]Benjamin P. Hershberg
, Nereo Markulic
, Jorge Lagos
, Ewout Martens
, Davide Dermit
, Jan Craninckx
:
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits 56(4): 1227-1240 (2021) - [j64]Benjamin P. Hershberg
, Davide Dermit
, Barend van Liempd
, Ewout Martens
, Nereo Markulic
, Jorge Lagos
, Jan Craninckx
:
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits 56(8): 2360-2374 (2021) - [j63]Benjamin P. Hershberg
, Barend van Liempd
, Nereo Markulic
, Jorge Lagos
, Ewout Martens
, Davide Dermit
, Jan Craninckx
:
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 68(7): 2813-2826 (2021) - [j62]Keigo Bunsen
, Ewout Martens, Davide Dermit, Jan Craninckx
:
A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 592-596 (2021) - [c92]Alican Çaglar
, Steven Van Winckel
, Steven Brebels, Piet Wambacq, Jan Craninckx:
A 4.2mW 4K 6-8GHz CMOS LNA for Superconducting Qubit Readout. A-SSCC 2021: 1-3 - [c91]Lucas Moura Santana
, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC 2021: 207-210 - [c90]Sriram Balamurali, Giovanni Mangraviti, Cheng-Hsueh Tsai, Piet Wambacq, Jan Craninckx:
A 55-63 GHz fundamental Quad-Core VCO with NMOS-only stacked oscillator in 28 nm CMOS. ESSCIRC 2021: 295-298 - [c89]Anirudh Kankuppe
, Sehoon Park
, Kristof Vaesen, Dae-Woong Park, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS. ESSCIRC 2021: 471-474 - [c88]Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx:
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. ISCAS 2021: 1-5 - [c87]Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas
, Ewout Martens, Jan Craninckx:
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits 2021: 1-2 - [c86]Ewout Martens, Davide Dermit, Mithlesh Shrivas
, Shun Nagata, Jan Craninckx:
A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW. VLSI Circuits 2021: 1-2 - [c85]Iuliana P. Radu, Roy Li, Anton Potocnik, Tsvetan Ivanov, Danny Wan, Stefan Kubicek, Nard I. Dumoulin Stuyck, Jeroen Verjauw, Julien Jussot, Yann Canvel, Clement Godfrin, Massimo Mongillo
, Rohith Acharya, Asser Elsayed, Mohamed Shehata, Xiaoyu Piao, Antoine Pacco, Laurent Souriau, Sebastien Couet, B. T. Chan, Jan Craninckx, Bertrand Parvais
, Alexander Grill, Subramanian Narasimhamoorthy, Steven Van Winckel, Steven Brebels, Fahd A. Mohiyaddin, George Simion, Bogdan Govoreanu:
Solid state qubits: how learning from CMOS fabrication can speed-up progress in Quantum Computing. VLSI Circuits 2021: 1-2 - [c84]Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC. VLSI Circuits 2021: 1-2 - 2020
- [j61]Cheng-Hsueh Tsai
, Zhiwei Zong
, Federico Pepe
, Giovanni Mangraviti
, Jan Craninckx
, Piet Wambacq
:
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE J. Solid State Circuits 55(7): 1854-1863 (2020) - [j60]Pratap Tumkur Renukaswamy
, Nereo Markulic
, Piet Wambacq
, Jan Craninckx
:
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits 55(12): 3294-3307 (2020) - [c83]Toshio Yasue, Fortunato Frazzica
, Annachiara Spagnolo, David San Segundo Bello, Maarten De Bock, Piet Wambacq, Jan Craninckx:
A 1st Order Incremental Sigma-Delta with Refined Digitally Implemented Feed-Forward for 2-stage ADC. IEEE SENSORS 2020: 1-4 - [c82]Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC 2020: 254-256 - [c81]Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park
, Anirudh Kankuppe
, Qixian Shi, Piet Wambacq, Jan Craninckx:
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC 2020: 278-280 - [c80]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j59]Jorge Lagos
, Benjamin P. Hershberg
, Ewout Martens
, Piet Wambacq
, Jan Craninckx
:
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54(2): 403-416 (2019) - [j58]Jorge Lagos
, Benjamin P. Hershberg
, Ewout Martens
, Piet Wambacq
, Jan Craninckx
:
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54(3): 646-658 (2019) - [j57]Nereo Markulic
, Pratap Tumkur Renukaswamy
, Ewout Martens
, Barend van Liempd
, Piet Wambacq
, Jan Craninckx
:
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits 54(4): 1059-1073 (2019) - [j56]Jan Craninckx:
New Associate Editors. IEEE J. Solid State Circuits 54(6): 1515-1516 (2019) - [j55]Jan Craninckx:
Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 54(8): 2107 (2019) - [j54]Qixian Shi
, Keigo Bunsen
, Nereo Markulic
, Jan Craninckx
:
A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth. IEEE J. Solid State Circuits 54(12): 3503-3512 (2019) - [j53]Shiwei Wang
, Carolina Mora Lopez
, Seyed Kasra Garakoui, Ho Sung Chun, Didac Gomez Salinas, Wim Sijbers
, Jan Putzeys
, Ewout Martens, Jan Craninckx
, Nick Van Helleputte
:
A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels. IEEE Trans. Biomed. Circuits Syst. 13(6): 1625-1634 (2019) - [c79]Aritra Banerjee
, Kristof Vaesen, Akshay Visweswaran, Khaled Khalaf, Qixian Shi, Steven Brebels, Davide Guermandi, Cheng-Hsueh Tsai, Johan Nguyen
, Alaa Medra, Yao Liu, Giovanni Mangraviti, Orges Furxhi
, Bert Gyselinckx, André Bourdoux, Jan Craninckx, Piet Wambacq:
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). CICC 2019: 1-11 - [c78]Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq:
A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter. ESSCIRC 2019: 111-114 - [c77]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC 2019: 58-60 - [c76]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC 2019: 68-70 - [c75]Qixian Shi, Keigo Bunsen
, Nereo Markulic, Jan Craninckx:
A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error. ISSCC 2019: 408-410 - 2018
- [j52]Jan Craninckx
:
New Associate Editors. IEEE J. Solid State Circuits 53(4): 963-964 (2018) - [j51]Ewout Martens
, Benjamin P. Hershberg, Jan Craninckx
:
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits 53(4): 1161-1171 (2018) - [j50]Jan Craninckx
:
New Associate Editor. IEEE J. Solid State Circuits 53(5): 1243 (2018) - [j49]Gengzhen Qi, Barend van Liempd
, Pui-In Mak
, Rui Paulo Martins
, Jan Craninckx
:
A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA. IEEE J. Solid State Circuits 53(5): 1431-1442 (2018) - [j48]Jan Craninckx
:
New Associate Editor. IEEE J. Solid State Circuits 53(7): 1875 (2018) - [j47]Lin-Kun Wu
, David San Segundo Bello, Philippe Coppejans, Jan Craninckx
, Andreas Süss, Maarten Rosmeulen, Piet Wambacq
, Jonathan Borremans:
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. Sensors 18(11): 3683 (2018) - [c74]Jorge Lagos
, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC 2018: 1-4 - [c73]Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits 2018: 215-216 - 2017
- [j46]Jan Craninckx
:
New Associate Editor. IEEE J. Solid State Circuits 52(4): 887 (2017) - [j45]Jan Craninckx
:
New Associate Editor. IEEE J. Solid State Circuits 52(7): 1699 (2017) - [j44]Jan Craninckx
:
New Associate Editor. IEEE J. Solid State Circuits 52(9): 2223 (2017) - [j43]John R. Long, Jan Craninckx
, Behzad Razavi:
Introducing Our Sister Publication: IEEE Solid-State Circuits Letters. IEEE J. Solid State Circuits 52(10): 2519-2520 (2017) - [j42]Davide Guermandi
, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx
, Wim Van Thillo:
A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. IEEE J. Solid State Circuits 52(10): 2613-2626 (2017) - [c72]Mark Ingels, Davide Dermit, Yao Liu, Hans Cappelle, Jan Craninckx
:
A 2×14bit digital transmitter with memoryless current unit cells and integrated AM/PM calibration. ESSCIRC 2017: 324-327 - [c71]Alyosha C. Molnar, Jan Craninckx, Aarno Pärssinen:
Session 18 overview: Full duplex wireless front-ends. ISSCC 2017: 312-313 - [c70]Jiayoon Ru, Kohei Onizuka, Pavan Kumar Hanumolu, Roberto Nonis, Howard C. Luong, Jan Craninckx:
F2: High-performance frequency generation for wireless and wireline systems. ISSCC 2017: 503-505 - 2016
- [j41]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
:
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits 51(7): 1593-1606 (2016) - [j40]Jan Craninckx
:
Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits 51(8): 1732 (2016) - [j39]Jan Craninckx
:
50th Anniversary of the Journal. IEEE J. Solid State Circuits 51(11): 2519 (2016) - [j38]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
:
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits 51(12): 3078-3092 (2016) - [c69]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
:
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC 2016: 176-177 - [c68]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
:
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. ISSCC 2016: 250-252 - [c67]Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx
:
20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC 2016: 356-357 - [c66]Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic:
F3: Radio architectures and circuits towards 5G. ISSCC 2016: 498-501 - [c65]Harish Krishnaswamy, Jan Craninckx, Tae Wook Kim:
EE2: Do we need to downscale our radios below 20nm? ISSCC 2016: 519 - [c64]Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
:
A Fractional-n subsampling PLL based on a digital-to-time converter. MIPRO 2016: 66-71 - 2015
- [j37]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
:
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". IEEE J. Solid State Circuits 50(2): 619 (2015) - [j36]Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx
:
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. IEEE J. Solid State Circuits 50(5): 1203-1213 (2015) - [j35]Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx
:
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits 50(9): 2002-2011 (2015) - [j34]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
:
An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. IEEE J. Solid State Circuits 50(12): 3065-3076 (2015) - [j33]Chunshu Li, Min Li, Khaled Khalaf, André Bourdoux, Marian Verhelst
, Mark Ingels, Piet Wambacq, Jan Craninckx
, Liesbet Van der Perre
, Sofie Pollin
:
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. J. Signal Process. Syst. 78(1): 5-19 (2015) - [c63]Qixian Shi, Davide Guermandi, Jan Craninckx
, Piet Wambacq:
Flicker noise upconversion mechanisms in K-band CMOS VCOs. A-SSCC 2015: 1-4 - [c62]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
:
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. ESSCIRC 2015: 80-83 - [c61]Björn Debaillie, Barend van Liempd, Benjamin P. Hershberg, Jan Craninckx
, Kari Rikkinen, D. J. van den Broek, Eric A. M. Klumperink, Bram Nauta
:
In-band full-duplex transceiver technology for 5G mobile networks. ESSCIRC 2015: 84-87 - [c60]Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx
:
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC 2015: 164-167 - [c59]Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx
:
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC 2015: 176-179 - [c58]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx
:
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. ISSCC 2015: 1-3 - [c57]Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx
:
2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. ISSCC 2015: 1-3 - 2014
- [j32]Björn Debaillie, Dirk-Jan van den Broek, Cristina Lavin, Barend van Liempd, Eric A. M. Klumperink, Carmen Palacios, Jan Craninckx
, Bram Nauta
, Aarno Pärssinen
:
Analog/RF Solutions Enabling Compact Full-Duplex Radios. IEEE J. Sel. Areas Commun. 32(9): 1662-1673 (2014) - [j31]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
:
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. IEEE J. Solid State Circuits 49(5): 1173-1183 (2014) - [j30]Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx
:
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits 49(8): 1815-1826 (2014) - [c56]Mina Mikhael, Barend van Liempd, Jan Craninckx
, Rafik Guindi, Björn Debaillie:
A Full-Duplex Transceiver Prototype with In-System Automated Tuning of the RF Self-Interference Cancellation. 5GU 2014: 110-115 - [c55]Barend van Liempd, Björn Debaillie, Jan Craninckx
, Cristina Lavin, Carmen Palacios, Satoshi Malotaux, John R. Long, D. J. van den Broek, Eric A. M. Klumperink:
RF self-interference cancellation for full-duplex. CrownCom 2014: 526-531 - [c54]Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx
:
A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. ESSCIRC 2014: 79-82 - [c53]Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx
:
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. ESSCIRC 2014: 83-86 - [c52]Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx
:
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. ESSCIRC 2014: 215-218 - [c51]Mark Ingels, Xiaoqiang Zhang, Kuba Raczkowski, Sungwoo Cha, Pieter Palmers, Jan Craninckx
:
A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3. ESSCIRC 2014: 379-382 - [c50]Barend van Liempd, Jan Craninckx
, R. Singh, Patrick Reynaert, Satoshi Malotaux, John R. Long:
A dual-notch +27dBm Tx-power electrical-balance duplexer. ESSCIRC 2014: 463-466 - [c49]Vito Giannini
, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx
, Piet Wambacq:
14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. ISSCC 2014: 250-251 - [c48]Bob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx
:
A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. VLSIC 2014: 1-2 - 2013
- [j29]Vincenzo Chironi, Björn Debaillie, Stefano D'Amico
, Andrea Baschirotto
, Jan Craninckx
, Mark Ingels:
A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 918-925 (2013) - [c47]Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx
:
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. CICC 2013: 1-4 - [c46]Mark Ingels, Yoshikazu Furuta, Xiaoqiang Zhang, Sungwoo Cha, Jan Craninckx
:
A multiband 40nm CMOS LTE SAW-less modulator with -60dBc C-IM3. ISSCC 2013: 338-339 - [c45]Min Li, Khaled Khalaf, Chunshu Li, Vojkan Vidojkovic, Mark Ingels, André Bourdoux, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre:
Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited). SiPS 2013: 324-329 - 2012
- [j28]Jan Craninckx
:
CMOS software-defined radio transceivers: Analog design in digital technology. IEEE Commun. Mag. 50(4): 136-144 (2012) - [j27]Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas
, Jan Craninckx
, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits 47(4): 990-1002 (2012) - [j26]Bob Verbruggen, Masao Iriguchi, Jan Craninckx
:
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 47(12): 2880-2887 (2012) - [j25]Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli
, Jan Craninckx
, Geert Van der Plas
:
A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 80-92 (2012) - [c44]Peng Gao
, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen:
Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping. DATE 2012: 1215-1220 - [c43]Wagdy M. Gaber, Piet Wambacq, Jan Craninckx
, Mark Ingels:
A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors. ESSCIRC 2012: 341-344 - [c42]Bob Verbruggen, Masao Iriguchi, Jan Craninckx
:
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. ISSCC 2012: 466-468 - [c41]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx
:
A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. ISSCC 2012: 470-472 - 2011
- [j24]Jonathan Borremans, Gunjan Mandal, Vito Giannini
, Björn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx
:
A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers. IEEE J. Solid State Circuits 46(7): 1659-1671 (2011) - [c40]Mark Ingels, Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto
, Jan Craninckx
:
An impedance modulated class-E polar amplifier in 90 nm CMOS. A-SSCC 2011: 285-288 - [c39]Jan Craninckx
, Jonathan Borremans, Mark Ingels:
SAW-less software-defined radio transceivers in 40nm CMOS. CICC 2011: 1-8 - [c38]Wagdy M. Gaber, Piet Wambacq, Jan Craninckx
, Mark Ingels:
A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter. ESSCIRC 2011: 139-142 - [c37]Kameswaran Vengattaramane, Jonathan Borremans, Michiel Steyaert
, Jan Craninckx
:
A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration. ESSCIRC 2011: 275-278 - [c36]Jonathan Borremans, Gunjan Mandal, Vito Giannini
, Tomohiro Sano, Mark Ingels, Bob Verbruggen, Jan Craninckx
:
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers. ISSCC 2011: 62-64 - [c35]Vito Giannini
, Mark Ingels, Tomohiro Sano, Björn Debaillie, Jonathan Borremans, Jan Craninckx
:
A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS. ISSCC 2011: 374-376 - [p1]Jan Craninckx, Geert Van der Plas
:
Low-Power ADCs for Bio-Medical Applications. Bio-Medical CMOS ICs 2011: 157-190 - 2010
- [j23]Pieter Crombez, Geert Van der Plas
, Michiel Steyaert
, Jan Craninckx
:
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. IEEE J. Solid State Circuits 45(6): 1159-1171 (2010) - [j22]Bob Verbruggen, Jan Craninckx
, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 45(10): 2080-2090 (2010) - [j21]Jonathan Borremans, Kameswaran Vengattaramane, Vito Giannini
, Björn Debaillie, Wim Van Thillo, Jan Craninckx
:
A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 45(10): 2116-2129 (2010) - [j20]Arnd Geis, Julien Ryckaert, Lynn Bos, Gerd Vandersteen, Yves Rolain, Jan Craninckx
:
A 0.5 mm 2 Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler. IEEE J. Solid State Circuits 45(11): 2375-2387 (2010) - [j19]Mark Ingels, Vito Giannini
, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx
:
A 5 mm2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform. IEEE J. Solid State Circuits 45(12): 2794-2806 (2010) - [c34]Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx:
An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. DATE 2010: 697-701 - [c33]Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels:
A compact digital amplitude modulator in 90nm CMOS. DATE 2010: 702-705 - [c32]Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Vito Giannini
, Jan Craninckx
:
A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point. ESSCIRC 2010: 402-405 - [c31]Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto
, Jan Craninckx
, Mark Ingels:
An area efficient digital amplitude modulator in 90nm CMOS. ISCAS 2010: 2219-2222 - [c30]Bob Verbruggen, Jan Craninckx
, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
:
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC 2010: 296-297 - [c29]Mark Ingels, Vito Giannini
, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx
:
A 5mm2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver. ISSCC 2010: 458-459 - [c28]Jonathan Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, Jan Craninckx
:
A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS. ISSCC 2010: 480-481 - [c27]Stefan Heinen, Domine Leenaerts, Trudy Stetzler, Yiannos Manoli, Jan Craninckx, Ali M. Niknejad, Didier Belot, Raf Roovers, K. P. Pun, Jed Hurwitz:
Reconfigurable RF and data converters. ISSCC 2010: 512-513
2000 – 2009
- 2009
- [b1]Liesbet Van der Perre, Jan Craninckx, Antoine Dejonghe:
Green Software Defined Radios - Enabling seamless connectivity while saving on hardware and energy. Series on Integrated Circuits and Systems, Springer 2009, ISBN 978-1-4020-8210-8, pp. 1-157 - [j18]Bob Verbruggen, Jan Craninckx
, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
:
A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits 44(3): 874-882 (2009) - [j17]Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx
:
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. IEEE J. Solid State Circuits 44(7): 1942-1949 (2009) - [j16]Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx
, Geert Van der Plas:
A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits 44(11): 2873-2880 (2009) - [j15]Vito Giannini
, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Jonathan Borremans, Joris Van Driessche, Jan Craninckx
, Mark Ingels:
A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS. IEEE J. Solid State Circuits 44(12): 3486-3498 (2009) - [j14]Björn Debaillie, Peter Van Wesemael, Gerd Vandersteen, Jan Craninckx
:
Calibration of Direct-Conversion Transceivers. IEEE J. Sel. Top. Signal Process. 3(3): 488-498 (2009) - [c26]Yi Ke, Jan Craninckx, Georges G. E. Gielen:
A design methodology for fully reconfigurable Delta-Sigma data converters. DATE 2009: 1379-1384 - [c25]Pieter Crombez, Geert Van der Plas
, Michiel Steyaert
, Jan Craninckx
:
A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS. ESSCIRC 2009: 336-339 - [c24]Kameswaran Vengattaramane, Jan Craninckx
, Michiel Steyaert
:
Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL. ISCAS 2009: 2397-2400 - [c23]Vito Giannini
, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert
, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx
, Mark Ingels:
A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS. ISSCC 2009: 408-409 - [c22]Jan Craninckx:
Clock synthesis design. ISSCC 2009: 510 - 2008
- [j13]Willem Laflere, Michiel S. J. Steyaert
, Jan Craninckx
:
A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer. IEEE J. Solid State Circuits 43(2): 460-467 (2008) - [j12]Jonathan Borremans, Andrea Bevilacqua
, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx
:
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. IEEE J. Solid State Circuits 43(12): 2693-2705 (2008) - [j11]Pieter Crombez, Jan Craninckx
, Piet Wambacq, Michiel Steyaert
:
A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized Gm-C Biquad in 0.13-mu m CMOS. IEEE Trans. Circuits Syst. II Express Briefs 55-II(3): 224-228 (2008) - [j10]Yi Ke, Jan Craninckx
, Georges G. E. Gielen
:
A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios. IEEE Trans. Circuits Syst. II Express Briefs 55-II(3): 229-233 (2008) - [c21]Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx
:
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. ESSCIRC 2008: 410-413 - [c20]Björn Debaillie, Peter Van Wesemael, Jan Craninckx
:
Calibration of SDR Circuit Imperfections. GLOBECOM 2008: 4700-4704 - [c19]Björn Debaillie, Peter Van Wesemael, Jan Craninckx
:
Calibration Method Enabling Low-Cost SDR. ICC 2008: 4899-4903 - [c18]Vito Giannini
, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto
, Geert Van der Plas, Jan Craninckx
:
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. ISSCC 2008: 238-239 - [c17]Bob Verbruggen, Jan Craninckx
, Maarten Kuijk, Piet Wambacq, Geert Van der Plas
:
A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS. ISSCC 2008: 252-253 - [c16]Jonathan Borremans, Stephane Bronckers, Piet Wambacq, Maarten Kuijk, Jan Craninckx
:
A Single-Inductor Dual-Band VCO in a 0.06mm2 5.6GHz Multi-Band Front-End in 90nm Digital CMOS. ISSCC 2008: 324-325 - [c15]Stefan Heinen, Francesco Svelto, Jan Craninckx, Mototsugu Hamada, Domine Leenaerts, Chris Rudell:
Architectures and Circuit Techniques for Nanoscale RF CMOS (Forum). ISSCC 2008: 654-655 - 2007
- [j9]Dries Hauspie, Eun-Chul Park, Jan Craninckx
:
Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size. IEEE J. Solid State Circuits 42(7): 1472-1480 (2007) - [j8]Vito Giannini
, Jan Craninckx
, Stefano D'Amico
, Andrea Baschirotto
:
Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends. IEEE J. Solid State Circuits 42(7): 1501-1512 (2007) - [j7]Julien Ryckaert, Geert Van der Plas
, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx
:
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a. IEEE J. Solid State Circuits 42(12): 2860-2869 (2007) - [j6]Antoine Dejonghe, Bruno Bougard, Sofie Pollin
, Jan Craninckx
, André Bourdoux, Liesbet Van der Perre
, Francky Catthoor:
Green Reconfigurable Radio Systems. IEEE Signal Process. Mag. 24(3): 90-101 (2007) - [c14]Pieter Crombez, Jan Craninckx
, Piet Wambacq, Michiel Steyaert
:
Linearity guidelines for gm-C biquad filter design using architecture optimization with Volterra analysis. ECCTD 2007: 216-219 - [c13]Willem Laflere, Michiel Steyaert
, Jan Craninckx
:
A power amplifier driver using self-oscillating pulse-width modulators. ESSCIRC 2007: 380-383 - [c12]Mark Ingels, Charlotte Soens, Jan Craninckx
, Vito Giannini
, T. Kim, Björn Debaillie, Michael Libois, Michaël Goffioul, Joris Van Driessche:
A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier. ESSCIRC 2007: 436-439 - [c11]Vincent De Heyn, Geert Van der Plas
, Julien Ryckaert, Jan Craninckx
:
A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS. ESSCIRC 2007: 484-487 - [c10]Yi Ke, Soheil Radiom, Hamidreza Rezaee, Guy A. E. Vandenbosch, Jan Craninckx
, Georges G. E. Gielen
:
Optimal Design Methodology for High-Order Continuous-Time Wideband Delta-Sigma Converters. ICECS 2007: 743-746 - [c9]Julien Ryckaert, Geert Van der Plas
, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx
:
A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. ISSCC 2007: 120-591 - [c8]Jan Craninckx
, Geert Van der Plas
:
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. ISSCC 2007: 246-600 - [c7]Jan Craninckx
, M. Liu, Dries Hauspie, Vito Giannini
, T. Kim, Jaehoon Lee, Mike Libois, Björn Debaillie, Charlotte Soens, Andrea Baschirotto, Joris Van Driessche, Liesbet Van der Perre
, Peter Vanbekbergen:
A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS. ISSCC 2007: 346-607 - [c6]Liesbet Van der Perre
, Bruno Bougard, Jan Craninckx
, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, Miguel Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen:
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. ISSCC 2007: 568-569 - 2006
- [c5]Vito Giannini, Pierluigi Nuzzo, Fernando De Bernardinis, Jan Craninckx, Boris Come, Stefano D'Amico, Andrea Baschirotto:
A synthesis tool for power-efficient base-band filter design. DATE 2006: 162-163 - [c4]Vito Giannini, Jan Craninckx, J. Compiet, Boris Come, Stefano D'Amico, Andrea Baschirotto:
Fully reconfigurable active-Gm-RC biquadratic cells for software defined radio applications. ISCAS 2006 - 2005
- [c3]Mingxu Liu, Jan Craninckx
:
A 5-GHz BiCMOS variable-gain low noise amplifier with inductorless low-gain branch. ESSCIRC 2005: 223-226 - 2004
- [c2]Jan Craninckx, Vincent Gravot, Stéphane Donnay:
A harmonic quadrature LO generator using a 90° delay-locked loop [zero-IF transceiver applications]. ESSCIRC 2004: 127-130 - 2003
- [c1]Jan Craninckx, Stéphane Donnay:
4G terminals: how are we going to design them? DAC 2003: 79-84
1990 – 1999
- 1998
- [j5]Jan Craninckx
, Michel S. J. Steyaert
:
A fully integrated CMOS DCS-1800 frequency synthesizer. IEEE J. Solid State Circuits 33(12): 2054-2065 (1998) - 1997
- [j4]Jan Craninckx
, Michiel S. J. Steyaert
:
A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors. IEEE J. Solid State Circuits 32(5): 736-744 (1997) - 1996
- [j3]Jan Craninckx
, Michiel S. J. Steyaert
:
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS. IEEE J. Solid State Circuits 31(7): 890-897 (1996) - 1995
- [j2]Michel S. J. Steyaert
, Wim Dehaene, Jan Craninckx
, Mairtin Walsh, Peter Real:
A CMOS rectifier-integrator for amplitude detection in hard disk servo loops. IEEE J. Solid State Circuits 30(7): 743-751 (1995) - [j1]Jan Craninckx
, Michel S. J. Steyaert
:
A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler. IEEE J. Solid State Circuits 30(12): 1474-1482 (1995)
Coauthor Index
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