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ORCIDEugenio Dentoni Litta
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2020 – today
- 2023
[c16]Hiroaki Arimura, S. Brus, Jacopo Franco, Yusuke Oniki, A. Vandooren, T. Conard, B. T. Chan, B. Kannan, M. Samiee, W. Li, P. Deminskyi, E. Shero, J. Bakke, N. Jourdan, G. Alessio Verni, J. W. Maes, M. Givens, Lars-Åke Ragnarsson, Jérôme Mitard, E. Dentoni Litta, N. Horiguchi:
Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET. VLSI Technology and Circuits 2023: 1-2- [c15]Jacopo Franco, Hiroaki Arimura, J.-F. de Marneffe, S. Brus, Romain Ritzenthaler, E. Dentoni Litta, Kris Croes, Ben Kaczer, N. Horiguchi:
Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions. VLSI Technology and Circuits 2023: 1-2 - [c14]Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo
, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans:
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. VLSI Technology and Circuits 2023: 1-2 - [c13]Victor Vega-Gonzalez, D. Radisic, Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster, Yusuke Oniki, P. Puttarame, Kevin Vandersmissen, J. P. Soulie, A. Peter, A. Sepulveda, D. Batuk, G. T. Martinez, Olivier Richard, Jürgen Bömmels, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi, Seongho Park, Zsolt Tokei:
Integration of a Stacked Contact MOL for Monolithic CFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c12]Alessio Spessot, Shairfe Muhammad Salahuddin, Ricardo Escobar, Romain Ritzenthaler, Yang Xiang, Rahul Budhwani, Eugenio Dentoni Litta, Elena Capogreco, Joao Bastos, Yangyin Chen, Naoto Horiguchi:
Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations. IMW 2022: 1-4 - [c11]J. P. Bastos, Barry J. O'Sullivan, Jacopo Franco, Stanislav Tyaginov, Brecht Truijen, Adrian Vaisman Chasin, Robin Degraeve, Ben Kaczer, Romain Ritzenthaler, Elena Capogreco, E. Dentoni Litta, Alessio Spessot, Yusuke Higashi, Y. Yoon, V. Machkaoutsan, Pierre Fazan, N. Horiguchi:
Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery. IRPS 2022: 1-6 - [c10]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi:
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c9]Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi:
High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. VLSI Technology and Circuits 2022: 306-307 - [c8]A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi:
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. VLSI Technology and Circuits 2022: 330-331 - [c7]Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, Jo De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi:
Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO. VLSI Technology and Circuits 2022: 431-432 - 2021
- [c6]Jacopo Franco, Hiroaki Arimura, J.-F. de Marneffe, A. Vandooren, L.-Å. Ragnarsson, Zhicheng Wu, Dieter Claes, E. Dentoni Litta, N. Horiguchi, Kris Croes, Dimitri Linten, Tibor Grasser, Ben Kaczer:
Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper. ICICDT 2021: 1-4 - 2020
- [c5]Adrian Vaisman Chasin, Jacopo Franco, Erik Bury, Romain Ritzenthaler, Eugenio Dentoni Litta, Alessio Spessot, Naoto Horiguchi, Dimitri Linten, Ben Kaczer:
Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation. IRPS 2020: 1-6
2010 – 2019
- 2019
- [c4]Barry J. O'Sullivan, Romain Ritzenthaler, Gerhard Rzepa, Z. Wu, E. Dentoni Litta, O. Richard, T. Conard, V. Machkaoutsan, Pierre Fazan, C. Kim, Jacopo Franco, Ben Kaczer, Tibor Grasser, Alessio Spessot, Dimitri Linten, N. Horiguchi:
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices. IRPS 2019: 1-8 - 2015
- [c3]Sam Vaziri, Melkamu Belete, Anderson D. Smith, Eugenio Dentoni Litta, Grzegorz Lupina, Max Christian Lemme, Mikael Östling:
Step tunneling-enhanced hot-electron injection in vertical graphene base transistors. ESSDERC 2015: 198-201 - 2014
- [c2]Maryam Olyaei, B. Gunnar Malm, Eugenio Dentoni Litta, Per-Erik Hellström, Mikael Östling:
Improved low-frequency noise for 0.3nm EOT thulium silicate interfacial layer. ESSDERC 2014: 361-364 - 2013
- [c1]Eugenio Dentoni Litta, Per-Erik Hellström, Mikael Östling:
Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs. ESSDERC 2013: 155-158
Coauthor Index
aka: N. Horiguchi
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