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Arnaud Virazel
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Journal Articles
- 2021
- [j36]Patrick Girard
, Yuanqing Cheng
, Arnaud Virazel
, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
:
A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE 109(2): 149-169 (2021) - [j35]Pablo Ilha Vaz
, Patrick Girard
, Arnaud Virazel
, Hassen Aziza
:
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1122-1131 (2021) - 2020
- [j34]Bastien Deveautour, Arnaud Virazel
, Patrick Girard
, Valentin Gherman:
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits. J. Electron. Test. 36(1): 33-46 (2020) - [j33]Marcello Traiola
, Arnaud Virazel
, Patrick Girard
, Mario Barbareschi
, Alberto Bosio
:
A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE 108(12): 2178-2194 (2020) - 2018
- [j32]Aymen Touati
, Alberto Bosio
, Patrick Girard, Arnaud Virazel
, Paolo Bernardi
, Matteo Sonza Reorda
, Etienne Auvray:
Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. 6(2): 278-287 (2018) - 2017
- [j31]Imran Wali, Bastien Deveautour, Arnaud Virazel
, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
:
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33(1): 25-36 (2017) - [j30]Alejandro Nocua
, Arnaud Virazel
, Alberto Bosio, Patrick Girard, Cyril Chevalier:
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26(8): 1740004:1-1740004:19 (2017) - [j29]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel
, Paolo Bernardi
, Matteo Sonza Reorda
:
Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. 26(8): 1740007:1-1740007:18 (2017) - [j28]Alejandro Nocua
, Arnaud Virazel
, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13(1): 10-28 (2017) - 2016
- [j27]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
:
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32(2): 147-161 (2016) - [j26]Kapil Juneja, Darayus Adil Patel, Rajesh Kumar Immadi, Balwant Singh, Sylvie Naudet, Pankaj Agarwal, Arnaud Virazel
, Patrick Girard:
An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization. J. Electron. Test. 32(6): 721-733 (2016) - [j25]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
, Philippe Debaud, Stephane Guilhot:
Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. 25(3): 1640013:1-1640013:18 (2016) - 2014
- [j24]D. A. Tran, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30(4): 401-413 (2014) - [j23]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray:
Intra-Cell Defects Diagnosis. J. Electron. Test. 30(5): 541-555 (2014) - [j22]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
, Nabil Badereddine:
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. 30(5): 611-627 (2014) - [j21]Aida Todri-Sanial
, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
:
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2131-2144 (2014) - [j20]Joao Azevedo, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
, Jérémy Alvarez-Herault, Ken Mackay:
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2326-2335 (2014) - 2013
- [j19]Aida Todri
, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
:
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 306-319 (2013) - [j18]Aida Todri
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
:
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 958-970 (2013) - 2012
- [j17]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. J. Electron. Test. 28(2): 215-228 (2012) - [j16]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. 28(3): 317-329 (2012) - 2010
- [j15]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed:
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. 6(2): 359-374 (2010) - [j14]Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers 59(3): 289-300 (2010) - 2009
- [j13]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. J. Electron. Test. 25(2-3): 127-144 (2009) - [j12]Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. 3(6): 581-592 (2009) - [j11]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 17(10): 1556-1559 (2009) - 2008
- [j10]Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty
, Arnaud Virazel
, Serge Pravossoudovitch, Christian Landrault:
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. J. Electron. Test. 24(4): 353-364 (2008) - 2007
- [j9]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electron. Test. 23(5): 435-444 (2007) - 2006
- [j8]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electron. Test. 22(1): 89-99 (2006) - [j7]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Simone Borri, Magali Bastian Hage-Hassan:
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electron. Test. 22(3): 287-296 (2006) - 2005
- [j6]Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
:
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electron. Test. 21(2): 169-179 (2005) - [j5]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Simone Borri, Magali Hage-Hassan:
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electron. Test. 21(5): 551-561 (2005) - 2002
- [j4]Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich:
High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Des. Test Comput. 19(5): 44-52 (2002) - [j3]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
Hardware Generation of Random Single Input Change Test Sequences. J. Electron. Test. 18(2): 145-157 (2002) - 2001
- [j2]Arnaud Virazel
, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. J. Electron. Test. 17(3-4): 233-241 (2001) - 1999
- [j1]Patrick Girard
, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel
:
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. J. Electron. Test. 14(1-2): 95-102 (1999)
Conference and Workshop Papers
- 2024
- [c153]Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE 2024: 1-6 - [c152]G. Mongelli, Xhesila Xhafa, Eric Faehn, D. Robins, P. Girard, Arnaud Virazel:
A Graph-Based Methodology for Speeding up Cell-Aware Model Generation. IOLTS 2024: 1-6 - 2023
- [c151]Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel:
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS 2023: 1-4 - [c150]Xhesila Xhafa, Patrick Girard, Arnaud Virazel:
Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies. ETS 2023: 1-2 - [c149]Xhesila Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel
, Gregory di Pendina, Patrick Girard, Arnaud Virazel:
On Using Cell-Aware Methodology for SRAM Bit Cell Testing. ETS 2023: 1-4 - [c148]J. Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel:
Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. ITC 2023: 310-319 - 2022
- [c147]Riccardo Cantoro, Francesco Garau, Patrick Girard, Nima Kolahimahmoudi, Sandro Sartoni, Matteo Sonza Reorda
, Arnaud Virazel
:
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries. ETS 2022: 1-2 - [c146]S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
:
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. ETS 2022: 1-4 - [c145]J. Lefevre, P. Debaud, Patrick Girard
, Arnaud Virazel
:
A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. ETS 2022: 1-2 - [c144]P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel
:
A Comprehensive Learning-Based Flow for Cell-Aware Model Generation. ITC 2022: 484-488 - 2021
- [c143]P. D'Hondt, Aymen Ladhar, Patrick Girard
, Arnaud Virazel
:
A Learning-Based Methodology for Accelerating Cell-Aware Model Generation. DATE 2021: 1580-1585 - [c142]Lila Ammoura, Marie-Lise Flottes, Patrick Girard
, Arnaud Virazel
:
Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS 2021: 1-4 - [c141]Alberto Bosio, Ian O'Connor, Marcello Traiola
, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique
, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel
, Koen Bertels:
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*. ETS 2021: 1-10 - [c140]S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
:
A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. ETS 2021: 1-4 - [c139]Riccardo Cantoro, Patrick Girard, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda
, Arnaud Virazel:
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement. IOLTS 2021: 1-4 - [c138]Bastien Deveautour, Marcello Traiola
, Arnaud Virazel
, Patrick Girard
:
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing. IOLTS 2021: 1-7 - [c137]Safa Mhamdi, Patrick Girard, Arnaud Virazel
, Alberto Bosio, Aymen Ladhar:
Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED 2021: 48-53 - [c136]J. Lefevre, Philippe Debaud, Patrick Girard
, Arnaud Virazel
:
A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors. ITC 2021: 1-9 - 2020
- [c135]Marcello Traiola
, Arnaud Virazel
, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Maximizing Yield for Approximate Integrated Circuits. DATE 2020: 810-815 - [c134]Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino
, Lukás Sekanina, Marcello Traiola
, Zdenek Vasícek, Arnaud Virazel
:
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS 2020: 1-10 - [c133]Bastien Deveautour, Marcello Traiola
, Arnaud Virazel
, Patrick Girard
:
QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction. ETS 2020: 1-6 - [c132]Safa Mhamdi, Patrick Girard, Arnaud Virazel
, Alberto Bosio, Aymen Ladhar:
Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS 2020: 1-2 - [c131]Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea
, T. Vayssade, Arnaud Virazel
:
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS 2020: 1-4 - [c130]Pablo Ilha Vaz, Patrick Girard
, Arnaud Virazel
, Hassen Aziza:
A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications. IOLTS 2020: 1-6 - [c129]Safa Mhamdi, Patrick Girard
, Arnaud Virazel
, Alberto Bosio, Aymen Ladhar:
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC 2020: 1-10 - 2019
- [c128]Safa Mhamdi, Arnaud Virazel
, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar:
Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS 2019: 21-26 - [c127]Hassen Aziza, Mathieu Moreau
, Annie Pérez, Arnaud Virazel, Patrick Girard:
A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks. NEWCAS 2019: 1-4 - 2018
- [c126]Marcello Traiola
, Arnaud Virazel
, Patrick Girard
, Mario Barbareschi
, Alberto Bosio:
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS 2018: 85-90 - [c125]Marcello Traiola
, Arnaud Virazel
, Patrick Girard
, Mario Barbareschi, Alberto Bosio:
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT 2018: 1-6 - [c124]Bastien Deveautour, Arnaud Virazel
, Patrick Girard, Serge Pravossoudovitch, Valentin Gherman:
Is aproximate computing suitable for selective hardening of arithmetic circuits? DTIS 2018: 1-6 - [c123]Tien-Phu Ho, Eric Faehn, Arnaud Virazel
, Alberto Bosio, Patrick Girard:
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC 2018: 1-8 - [c122]Marcello Traiola
, Arnaud Virazel
, Patrick Girard, Mario Barbareschi
, Alberto Bosio:
Testing approximate digital circuits: Challenges and opportunities. LATS 2018: 1-6 - 2017
- [c121]Imran Wali, Marcello Traiola
, Arnaud Virazel, Patrick Girard, Mario Barbareschi
, Alberto Bosio:
Towards approximation during test of Integrated Circuits. DDECS 2017: 28-33 - [c120]G. Harcha, Alberto Bosio, Patrick Girard
, Arnaud Virazel
, Paolo Bernardi
:
An effective fault-injection framework for memory reliability enhancement perspectives. DTIS 2017: 1-6 - [c119]Marcello Traiola
, Arnaud Virazel
, Patrick Girard, Mario Barbareschi
, Alberto Bosio:
Towards digital circuit approximation by exploiting fault simulation. EWDTS 2017: 1-7 - [c118]Alberto Bosio, Arnaud Virazel
, Patrick Girard
, Mario Barbareschi:
Approximate computing: Design & test for integrated circuits. LATS 2017: 1 - 2016
- [c117]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel
, Paolo Bernardi
, Matteo Sonza Reorda
:
An effective approach for functional test programs compaction. DDECS 2016: 119-124 - [c116]Alejandro Nocua
, Arnaud Virazel
, Alberto Bosio, Patrick Girard
, Cyril Chevalier:
A hybrid power modeling approach to enhance high-level power models. DDECS 2016: 151-156 - [c115]Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel
:
Auto-adaptive ultra-low power IC. DTIS 2016: 1-6 - [c114]Imran Wali, Bastien Deveautour, Arnaud Virazel
, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
:
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS 2016: 1-2 - [c113]Alberto Bosio, Patrick Girard, Arnaud Virazel:
Test of low power circuits: Issues and industrial practices. ICECS 2016: 524-527 - [c112]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
, Leonardo Bonet Zordan:
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED 2016: 185-191 - [c111]Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel
, Alberto Bosio:
Analysis of setup and hold margins inside silicon for advanced technology nodes. ISQED 2016: 295-300 - [c110]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel
, Paolo Bernardi
, Matteo Sonza Reorda
:
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI 2016: 731-736 - [c109]Alejandro Nocua
, Arnaud Virazel
, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC 2016: 1-6 - 2015
- [c108]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Exploring the impact of functional test programs re-used for power-aware testing. DATE 2015: 1277-1280 - [c107]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
, P. Debaud, S. Guilhot:
Design-for-Diagnosis Architecture for Power Switches. DDECS 2015: 43-48 - [c106]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi
, Matteo Sonza Reorda
:
An effective ATPG flow for Gate Delay Faults. DTIS 2015: 1-6 - [c105]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
, Paolo Bernardi
, Matteo Sonza Reorda
:
Scan-chain intra-cell defects grading. DTIS 2015: 1-6 - [c104]Imran Wali, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard:
An effective hybrid fault-tolerant architecture for pipelined cores. ETS 2015: 1-6 - [c103]Alejandro Nocua, Arnaud Virazel
, Alberto Bosio, Patrick Girard
, Cyril Chevalier:
An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM 2015: 17-20 - [c102]Imran Wali, Arnaud Virazel
, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
:
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS 2015: 89-94 - [c101]Sylvain Clerc, Fady Abouzeid
, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel
, Alberto Bosio, Patrick Girard:
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c100]Anu Asokan, Alberto Bosio, Arnaud Virazel
, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch:
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI 2015: 515-520 - 2014
- [c99]Yuanqing Cheng, Aida Todri-Sanial
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
:
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC 2014: 544-549 - [c98]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
, Etienne Auvray:
On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS 2014: 312-317 - [c97]Carolina Metzler, Aida Todri-Sanial
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
:
Timing-aware ATPG for critical paths with multiple TSVs. DDECS 2014: 116-121 - [c96]Anu Asokan, Aida Todri-Sanial
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
:
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS 2014: 207-212 - [c95]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri
, Arnaud Virazel
, Patrick Girard, P. Debaud, S. Guilhot:
Test and diagnosis of power switches. DDECS 2014: 213-218 - [c94]Imran Wali, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
:
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS 2014: 223-225 - [c93]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
, Arnaud Virazel, S. Bernabovi, Paolo Bernardi
:
An intra-cell defect grading tool. DDECS 2014: 298-301 - [c92]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri
, Arnaud Virazel
, Patrick Girard, P. Debaud, S. Guilhot:
iBoX - Jitter based Power Supply Noise sensor. ETS 2014: 1-2 - [c91]Anu Asokan, Aida Todri-Sanial
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
:
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI 2014: 226-231 - [c90]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
, Arnaud Virazel
, Paolo Bernardi
:
A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW 2014: 69-72 - [c89]Carolina Metzler, Aida Todri-Sanial
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS 2014: 1-6 - 2013
- [c88]Elena I. Vatajelu
, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri
, Arnaud Virazel, Nabil Badereddine:
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium 2013: 109-114 - [c87]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
Test solution for data retention faults in low-power SRAMs. DATE 2013: 442-447 - [c86]Elena I. Vatajelu
, Georgios Tsiligiannis
, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri
, Arnaud Virazel
, Frederic Wrobel
, Frédéric Saigné:
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS 2013: 143-148 - [c85]Elena I. Vatajelu
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS 2013: 39-44 - [c84]Carolina Metzler, Aida Todri-Sanial
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
, Pascal Vivet
, Marc Belleville:
Computing detection probability of delay defects in signal line tsvs. ETS 2013: 1-6 - [c83]Elena I. Vatajelu
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS 2013: 1-6 - [c82]Georgios Tsiligiannis
, Elena I. Vatajelu
, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri
, Arnaud Virazel
, Frederic Wrobel
, Frédéric Saigné:
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS 2013: 145-150 - [c81]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel, Etienne Auvray:
Effect-cause intra-cell diagnosis at transistor level. ISQED 2013: 460-467 - [c80]Yuanqing Cheng, Aida Todri-Sanial
, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel
, Pascal Vivet, Marc Belleville:
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI 2013: 121-126 - [c79]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC 2013: 1-10 - [c78]Georgios Tsiligiannis
, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial
, Arnaud Virazel
, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel
, Frédéric Saigné:
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI 2013: 75-80 - [c77]Aida Todri-Sanial
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
:
Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS 2013: 1-4 - [c76]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS 2013: 1-6 - 2012
- [c75]Joao Azevedo, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium 2012: 125-130 - [c74]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, P. Debaud, S. Guilhot:
Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium 2012: 161-166 - [c73]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
:
Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium 2012: 221-226 - [c72]Joao Azevedo, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial
, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE 2012: 532-537 - [c71]Joao Azevedo, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Coupling-based resistive-open defects in TAS-MRAM architectures. ETS 2012: 1 - [c70]Carolina Metzler, Aida Todri
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
:
Through-Silicon-Via resistive-open defect analysis. ETS 2012: 1 - [c69]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
Defect analysis in power mode control logic of low-power SRAMs. ETS 2012: 1 - [c68]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri
, Arnaud Virazel
, Antoine D. Touboul, Frederic Wrobel
, Frédéric Saigné:
Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS 2012: 121-122 - [c67]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC 2012: 1-10 - [c66]D. A. Tran, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Michael E. Imhof, Hans-Joachim Wunderlich:
A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS 2012: 50-55 - [c65]Alberto Bosio, Luigi Dilillo, Patrick Girard
, Serge Pravossoudovitch, Arnaud Virazel
:
Advanced test methods for SRAMs. VTS 2012: 300-301 - 2011
- [c64]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 - [c63]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium 2011: 136-141 - [c62]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri
, Arnaud Virazel
, Nabil Badereddine:
Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium 2011: 459-460 - [c61]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen:
Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium 2011: 506-510 - [c60]Aida Todri
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
:
A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS 2011: 189-194 - [c59]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS 2011: 353-358 - [c58]Pierre-Didier Mauroux, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS 2011: 359-364 - [c57]Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT 2011: 294-301 - [c56]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
:
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS 2011: 153-158 - [c55]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Nabil Badereddine:
On using address scrambling to implement defect tolerance in SRAMs. ITC 2011: 1-8 - 2010
- [c54]Paolo Rech
, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo:
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium 2010: 100-105 - [c53]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium 2010: 237-242 - [c52]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
A statistical simulation method for reliability analysis of SRAM core-cells. DAC 2010: 853-856 - [c51]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen:
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS 2010: 376-381 - [c50]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA 2010: 265-269 - [c49]Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez:
A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. ETS 2010: 81-86 - [c48]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS 2010: 132-137 - [c47]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Setting test conditions for improving SRAM reliability. ETS 2010: 257 - [c46]Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed:
Is test power reduction through X-filling good enough? ITC 2010: 805 - [c45]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
Parity prediction synthesis for nano-electronic gate designs. ITC 2010: 820 - [c44]Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
Detecting NBTI induced failures in SRAM core-cells. VTS 2010: 75-80 - 2009
- [c43]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium 2009: 355-360 - [c42]Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
A new design-for-test technique for SRAM core-cell stability faults. DATE 2009: 1344-1348 - [c41]Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute:
Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS 2009: 264-269 - [c40]Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Laroussi Bouzaida, Isabelle Izaute:
A case study on logic diagnosis for System-on-Chip. ISQED 2009: 253-259 - [c39]Pierre-Didier Mauroux, Arnaud Virazel
, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard:
NAND flash testing: A preliminary study on actual defects. ITC 2009: 1 - 2008
- [c38]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Magali Bastian, Vincent Gouin:
A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE 2008: 1480-1485 - [c37]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215 - [c36]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Using TMR Architectures for Yield Improvement. DFT 2008: 7-15 - [c35]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS 2008: 165-166 - [c34]Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Magali Bastian:
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC 2008: 1-10 - [c33]Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
SoC Yield Improvement: Redundant Architectures to the Rescue? ITC 2008: 1 - [c32]Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin:
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS 2008: 89-94 - 2007
- [c31]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Fast Bridging Fault Diagnosis using Logic Information. ATS 2007: 33-38 - [c30]Magali Bastian, Vincent Gouin, Patrick Girard, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel
:
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. ATS 2007: 507-510 - [c29]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
, Magali Bastian:
Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533 - [c28]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242 - [c27]Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
DERRIC: A Tool for Unified Logic Diagnosis. ETS 2007: 13-20 - [c26]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. ETS 2007: 77-84 - [c25]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
, Magali Bastian:
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. ETS 2007: 97-104 - [c24]Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga:
A concurrent approach for testing address decoder faults in eFlash memories. ITC 2007: 1-10 - [c23]Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52 - [c22]Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368 - 2006
- [c21]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian:
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261 - [c20]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408 - [c19]Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113 - 2005
- [c18]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Magali Bastian:
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC 2005: 857-862 - [c17]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Magali Bastian Hage-Hassan:
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. ETS 2005: 116-121 - [c16]Nabil Badereddine, Patrick Girard, Arnaud Virazel
, Serge Pravossoudovitch, Christian Landrault:
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549 - [c15]Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault:
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281 - [c14]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Magali Bastian Hage-Hassan:
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS 2005: 183-188 - 2004
- [c13]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium 2004: 266-271 - [c12]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67 - [c11]Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294 - [c10]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. ETS 2004: 140-145 - [c9]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Simone Borri:
March iC-: An Improved Version of March C- for ADOFs Detection. VTS 2004: 129-138 - 2003
- [c8]Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
, Simone Borri:
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium 2003: 250-255 - [c7]Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Defect-oriented dynamic fault models for embedded-SRAMs. ETW 2003: 23-28 - 2002
- [c6]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On Using Efficient Test Sequences for BIST. VTS 2002: 145-152 - 2001
- [c5]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
On hardware generation of random single input change test sequences. ETW 2001: 117-123 - [c4]René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel:
Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424 - 2000
- [c3]Arnaud Virazel
, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay fault testing: choosing between random SIC and random MIC test sequences. ETW 2000: 9-14 - [c2]Patrick Girard
, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
:
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126 - 1998
- [c1]Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel:
A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439
Parts in Books or Collections
- 2022
- [p1]Marcello Traiola
, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel
:
Test and Reliability of Approximate Hardware. Approximate Computing 2022: 233-266
Coauthor Index
aka: Aida Todri-Sanial
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