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2010 – 2019
- 2017
[j10]Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui
, Diego Puschini, Suzanne Lesecq, Edith Beigné:
Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. J. Low Power Electron. 13(3): 298-309 (2017)- 2016
- [j9]Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville:
Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era. ACM J. Emerg. Technol. Comput. Syst. 13(2): 12:1-12:2 (2016) - [j8]Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol:
Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. 57: 76-86 (2016) - 2015
- [j7]Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet:
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(6): 1546-1554 (2015) - [c18]Soundous Chairat, Edith Beigné, Marc Belleville:
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. PATMOS 2015: 55-62 - [c17]Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet:
Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits. RC 2015: 267-272 - 2014
- [j6]Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville:
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. 10(1): 118-126 (2014) - [c16]Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol:
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS 2014: 1-7 - 2013
- [c15]Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard:
A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE 2013: 1056-1057 - [c14]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
Computing detection probability of delay defects in signal line tsvs. ETS 2013: 1-6 - [c13]Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat:
An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT 2013: 9-12 - [c12]Santhosh Onkaraiah, Marc Belleville, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller:
A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. ICICDT 2013: 81-84 - [c11]Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI 2013: 121-126 - 2012
- [j5]Nadine Azémard, Marc Belleville:
Selected Articles from the VARI 2011 Workshop. J. Low Power Electron. 8(1): 82 (2012) - [j4]J. Mazurier, Olivier Weber, François Andrieu, Alain Toffoli, Olivier Thomas, Fabienne Allain, Jean-Philippe Noel, Marc Belleville, Olivier Faynot, T. Poiroux:
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below. J. Low Power Electron. 8(1): 125-132 (2012) - [c10]Marc Belleville, Olivier Thomas, Alexandre Valentian, Fabien Clermidy:
Design challenges for nano-scale devices. ESSDERC 2012: 69-72 - [c9]Florent Dupont, Cyril Condemine, Jean-François Beche, Marc Belleville:
Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring. ICECS 2012: 33-36 - [c8]Dimitri Soussan, Alexandre Valentian, Sylvain Majcherczak, Marc Belleville:
A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing. ICICDT 2012: 1-4 - 2011
- [j3]Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard:
Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. 42(5): 718-732 (2011) - [c7]Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard:
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. ISSCC 2011: 336-337 - 2010
- [j2]Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara:
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. 6(1): 201-210 (2010) - [j1]Marc Belleville, Hervé Fanet, Paolo Fiorini, Pierre Nicole, Marcel J. M. Pelgrom, Christian Piguet, Robert Hahn, Chris Van Hoof, Ruud J. M. Vullers, Marco Tartagni, Eugenio Cantatore:
Energy autonomous sensor systems: Towards a ubiquitous sensor technology. Microelectron. J. 41(11): 740-745 (2010) - [c6]Marc Belleville:
3D Integration for Digital and Imagers Circuits: Opportunities and Challenges. PATMOS 2010: 256
2000 – 2009
- 2009
- [c5]Tristan Thabuis, Patrick Villard, Marc Belleville, Gilles Sicard, Frederic Pistone, Patrick Maillart, Gilbert Decaens:
On-chip data compression for I.R. image sensors. ICECS 2009: 828-831 - [c4]Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard:
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS 2009: 266-275 - [c3]Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara:
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS 2009: 336-346 - 2008
- [c2]Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, Philippe Maurine, Nadine Azémard:
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI 2008: 316-321 - 2007
- [c1]Olivier Thomas, Marina Reyboz, Marc Belleville:
Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. ISCAS 2007: 2778-2781
Coauthor Index
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