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ORCIDIEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 21
Volume 21, Number 1, January 2013
- Dong Hyuk Woo, Nak Hee Seong, Hsien-Hsin S. Lee:
Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV. 1-13 - Liang Li, Robert G. Maunder
, Bashir M. Al-Hashimi, Lajos Hanzo:
A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks. 14-22 - Mario Garrido, Jesús Grajal, Miguel A. Sánchez Marcos, Oscar Gustafsson:
Pipelined Radix-2k Feedforward FFT Architectures. 23-32 - Jui-Hung Hsieh, Tian-Sheuan Chang:
Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications. 33-42 - Hsiao-Yun Chen, Jyun-Nan Lin, Hsiang-Sheng Hu, Shyh-Jye Jou:
STBC-OFDM Downlink Baseband Receiver for Mobile WMAN. 43-54 - Davide De Caro:
Glitch-Free NAND-Based Digitally Controlled Delay-Lines. 55-66 - Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang:
A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique. 67-77 - Aritra Hazra, Sahil Goyal, Pallab Dasgupta, Ajit Pal:
Formal Verification of Architectural Power Intent. 78-91 - Hassan Mostafa, Mohab Anis, Mohamed I. Elmasry:
Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits. 92-101 - Jianwei Dai, Lei Wang:
An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy. 102-112 - Abbas Eslami Kiasari, Zhonghai Lu, Axel Jantsch:
An Analytical Latency Model for Networks-on-Chip. 113-123 - Irith Pomeranz:
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure. 124-132 - Marius Monton, Jakob Engblom, Mark Burton:
Checkpointing for Virtual Platforms and SystemC-TLM. 133-141 - Tsang-Chi Kan, Shih-Hsien Yang, Ting-Feng Chang, Shanq-Jang Ruan:
Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate. 142-147 - Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson:
Scaling Energy Per Operation via an Asynchronous Pipeline. 147-151 - Anh-Tuan Do, Shoushun Chen, Zhi-Hui Kong, Kiat Seng Yeo:
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. 151-156 - Pedro Reviriego, Juan Antonio Maestro, Mark F. Flanagan:
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes. 156-159 - Yunus Emre, Chaitali Chakrabarti:
Techniques for Compensating Memory Errors in JPEG2000. 159-163 - Kan Takeuchi, Masaki Shimada, Takao Sato, Yusaku Katsuki, Hiroumi Yoshikawa, Hiroaki Matsushita:
Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise. 164-168 - Jiafeng Xie, Pramod Kumar Meher, Jianjun He:
Low-Complexity Multiplier for GF(2m) Based on All-One Polynomials. 168-173 - Phi-Hung Pham, Junyoung Song, Jongsun Park, Chulwoo Kim:
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip. 173-177 - Phi-Hung Pham, Phuong Mau, Jungmoon Kim, Chulwoo Kim:
An On-Chip Network Fabric Supporting Coarse-Grained Processor Array. 178-182 - Juan Antonio Gómez Galán, Manuel Pedro, Trinidad Sanchez-Rodriguez, Fernando Muñoz, Ramón González Carvajal, Antonio J. López-Martín:
A Very Linear Low-Pass Filter with Automatic Frequency Tuning. 182-187 - Taesang Cho, Hanho Lee:
A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications. 187-191
Volume 21, Number 2, February 2013
- Davide Rossi, Claudio Mucci, Fabio Campi, Simone Spolzino, Luca Vanzolini, Henning Sahlbach, Sean Whitty, Rolf Ernst, Wolfram Putzke-Röming, Roberto Guerrieri:
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor. 193-205 - Jae-Sung Yoon, Jeong-Hyun Kim, Hyo-Eun Kim, Won-Young Lee, Seok-Hoon Kim, Kyusik Chung, Jun-Seok Park, Lee-Sup Kim:
A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality. 206-216 - Pramod Kumar Meher, Sang Yoon Park:
CORDIC Designs for Fixed Angle of Rotation. 217-228 - Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King:
Application-Driven End-to-End Traffic Predictions for Low Power NoC Design. 229-238 - Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li:
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs. 239-249 - I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS. 250-258 - Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo:
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. 259-269 - You-Gang Chen, Hen-Wai Tsao, Chorng-Sii Hwang:
A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction. 270-280 - Jaeyong Chung, Joonsung Park, Jacob A. Abraham:
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. 281-291 - Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu:
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. 292-305 - Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. 306-319 - Joon-Sung Yang, Nur A. Touba:
Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug. 320-328 - Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu:
AC-Plus Scan Methodology for Small Delay Testing and Characterization. 329-341 - Marshnil Vipin Dave, Mahavir Jain, Maryam Shojaei Baghini, Dinesh Kumar Sharma:
A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects. 342-353 - Xiang Hu, Peng Du, James F. Buckwalter, Chung-Kuan Cheng:
Modeling and Analysis of Power Distribution Networks in 3-D ICs. 354-366 - Kai-Chiang Wu, Diana Marculescu:
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits. 367-379 - Siddhesh S. Mhambrey, Satendra Kumar Maurya, Lawrence T. Clark:
Low Complexity Out-of-Order Issue Logic Using Static Circuits. 380-384 - Jiafeng Xie, Jianjun He, Pramod Kumar Meher:
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials. 385-389
Volume 21, Number 3, March 2013
- Yehea I. Ismail:
Editorial Appointments for the 2013-2014 Term. 393-412 - Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao:
Power-Up Sequence Control for MTCMOS Designs. 413-423 - S. Man Ho Ho, Yanqing Ai, Thomas Chun-Pong Chau, Steve C. L. Yuen, Oliver Chiu-sing Choy, Philip Heng Wai Leong, Kong-Pang Pun:
Architecture and Design Flow for a Highly Efficient Structured ASIC. 424-433 - Santosh Ghosh, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform. 434-442 - Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. 443-453 - Sehun Kook, Hyun Woo Choi, Abhijit Chatterjee:
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements. 454-464 - Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu:
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. 465-474 - Irith Pomeranz:
Computing Two-Pattern Test Cubes for Transition Path Delay Faults. 475-485 - Erin G. Fong, Nathaniel J. Guilar, Travis Kleeburg, Hai Pham, Diego R. Yankelevich, Rajeevan Amirtharajah:
Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance. 486-497 - Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. 498-511 - Josep Rius:
IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption. 512-522 - Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang:
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. 523-532 - Hailong Jiao, Volkan Kursun:
Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits. 533-545 - Kwan Wai Li, Ka Nang Leung, Lincoln Lai Kan Leung:
Sub-mW $LC$ Dual-Input Injection-Locked Oscillator for Autonomous WBSNs. 546-553 - Pierce Chuang, David Li, Manoj Sachdev:
Constant Delay Logic Style. 554-565 - Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny:
A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. 566-570 - Emad Ebrahimi, Sasan Naseh:
A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling. 571-574 - Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon Wook Kim, Chulwoo Kim:
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor. 575-579 - Abhishek A. Sinkar, Taejoon Park, Nam Sung Kim:
Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability. 580-584 - Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, Ying-Zu Lin:
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method. 584-588 - Te-Wen Liao, Jun-Ren Su, Chung-Chih Hung:
Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD. 589-592 - Xiwen Zhang, Hoi Lee:
Gain-Enhanced Monolithic Charge Pump With Simultaneous Dynamic Gate and Substrate Control. 593-596 - Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang:
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. 597-601
Volume 21, Number 4, April 2013
- Kanad Basu, Prabhat Mishra:
RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation. 605-613 - Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, Kaile Gao, Bin Liang:
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes. 614-623 - Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang:
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. 624-635 - Gwo-Long Li, Tzu-Yu Chen, Meng-Wei Shen, Meng-Hsun Wen, Tian-Sheuan Chang:
135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder. 636-647 - Tasreen Charania, Ajoy Opal, Manoj Sachdev:
Analysis and Design of On-Chip Decoupling Capacitors. 648-658 - Yupeng Chen, Bertil Schmidt, Douglas L. Maskell:
Reconfigurable Accelerator for the Word-Matching Stage of BLASTN. 659-669 - Koushik Chakraborty, Sanghamitra Roy:
Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems. 670-679 - Selçuk Köse, Simon Tam, Sally Pinzon, Bruce McDermott, Eby G. Friedman:
Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation. 680-691 - Katherine Shu-Min Li:
CusNoC: Fast Full-Chip Custom NoC Generation. 692-705 - Liang Shi, Jianhua Li, Chun Jason Xue, Xuehai Zhou:
Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems. 706-719 - Kai-Jiun Yang, Shang-Ho Tsai, Gene C. H. Chuang:
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems. 720-731 - Hesam Amir Aslanzadeh, Erik John Pankratz, Chinmaya Mishra, Edgar Sánchez-Sinencio:
Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic Tuning. 732-746 - Yen-Liang Chen, Cheng-Zhou Zhan, Ting-Jyun Jheng, An-Yeu Wu:
Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems. 747-760 - David B. Thomas, Wayne Luk:
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. 761-770 - Yangyang Pan, Yiran Li, Hongbin Sun, Wei Xu, Nanning Zheng, Tong Zhang:
Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs. 771-775 - Irith Pomeranz:
Broadside and Skewed-Load Tests Under Primary Input Constraints. 776-780 - Yasuhiro Ogasahara, Masanori Hashimoto, Toshiki Kanamoto, Takao Onoye:
Supply Noise Suppression by Triple-Well Structure. 781-785 - Giorgos Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures. 786-790 - Keshab K. Parhi:
Comments on "Low-energy CSMT carry generators and binary adders". 791
Volume 21, Number 5, May 2013
- Supriya Karmakar, John A. Chandy, Faquir C. Jain:
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs. 793-806 - Haitham Eissa, Rami Fathy Salem, Ahmed Arafa, Sherif Hany, Abdelrahman ElMously, Mohamed Dessouky, David Nairn, Mohab H. Anis:
Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow. 807-820 - Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction. 821-833 - Mojtaba Mahdavi, Mahdi Shabany:
Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain. 834-847 - Mahdi Shabany, Ameer Youssef, P. Glenn Gulak:
High-Throughput 0.13-µm CMOS Lattice Reduction Core Supporting 880 Mb/s Detection. 848-861 - Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim:
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. 862-874 - Shen-Fu Hsiao, Hou-Jen Ko, Yu-Ling Tseng, Wen-Liang Huang, Shin-Hung Lin, Chia-Sheng Wen:
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. 875-886 - Behnam Ghavami, Mohsen Raji, Hossein Pedram, Massoud Pedram:
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits. 887-900 - Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay:
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed. 901-909 - Suhaib A. Fahmy, A. R. Mohan:
Architecture for Real-Time Nonparametric Probability Density Function Estimation. 910-920 - Jinwook Oh, Seungjin Lee, Hoi-Jun Yoo:
1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor. 921-933 - Ali Peiravi, Mohammad Asyaei:
Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates. 934-943 - Zhigang Hao, Guoyong Shi, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle:
Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks. 944-957 - Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. 958-970 - Hiroaki Inoue, Takashi Takenaka, Masato Motomura:
C-Based Complex Event Processing on Reconfigurable Hardware. 971-974 - Wei Zhang, Hao Wang, Boyang Pan:
Reduced-Complexity LCC Reed-Solomon Decoder Based on Unified Syndrome Computation. 974-978 - Asaf Kaizerman, Sagi Fisher, Alexander Fish:
Subthreshold Dual Mode Logic. 979-983 - Renatas Jakushokas, Eby G. Friedman:
Power Network Optimization Based on Link Breaking Methodology. 983-987
Volume 21, Number 6, June 2013
- Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh:
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms. 989-999 - Lucas Francisco Wanner, Charwak Apte, Rahul Balani, Puneet Gupta, Mani B. Srivastava:
Hardware Variability-Aware Duty Cycling for Embedded Sensors. 1000-1012 - Young-Geun Choi, Sungjoo Yoo, Sunggu Lee, Jung Ho Ahn, Kangmin Lee:
MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache. 1013-1026 - Isaak Yang, Sung Hoon Jung, Kwang-Hyun Cho:
Self-Repairing Digital System With Unified Recovery Process Inspired by Endocrine Cellular Communication. 1027-1040 - Kyu-Nam Shim, Jiang Hu, José Silva-Martínez:
Dual-Level Adaptive Supply Voltage System for Variation Resilience. 1041-1052 - Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing:
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. 1053-1066 - Marcel Gort, Jason Helge Anderson:
Combined Architecture/Algorithm Approach to Fast FPGA Routing. 1067-1079 - Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Shreepad Panth, Sung Kyu Lim, Jongman Kim:
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures. 1080-1093 - Jingtong Hu, Chun Jason Xue, Qingfeng Zhuge, Wei-Che Tseng, Edwin Hsing-Mean Sha:
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory. 1094-1102 - Eddie Hung, Steven J. E. Wilton:
Scalable Signal Selection for Post-Silicon Debug. 1103-1115 - Ender Yilmaz, Sule Ozev, Kenneth M. Butler:
Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring. 1116-1128 - Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor:
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects. 1129-1142 - Meng-Chou Chang, Wei-Hsiang Chang:
Asynchronous Fine-Grain Power-Gated Logic. 1143-1153 - Jun-Ren Su, Te-Wen Liao, Chung-Chih Hung:
All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle. 1154-1164 - Sumit Jagdish Darak, A. Prasad Vinod, Edmund Ming-Kit Lai:
Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses. 1165-1169 - Christina C.-H. Liao, Allen W.-T. Chen, Louis Y.-Z. Lin, Charles H.-P. Wen:
Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints. 1170-1174 - Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. 1175-1179
Volume 21, Number 7, July 2013
- Yalcin Yilmaz, Pinaki Mazumder:
Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets. 1181-1188 - Jeongha Park, Saeroonter Oh, Soyoung Kim, H.-S. Philip Wong, S. Simon Wong:
Impact of III-V and Ge Devices on Circuit Performance. 1189-1200 - Himanshu Thapliyal, Nagarajan Ranganathan, Saurabh Kotiyal:
Design of Testable Reversible Sequential Circuits. 1201-1209 - Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Test Path Selection for Capturing Delay Failures Under Statistical Timing Model. 1210-1219 - Ying Zhang, Huawei Li, Xiaowei Li:
Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors. 1220-1233 - Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, Chulwoo Kim:
Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation. 1234-1245 - Ting-Chi Tong, Yun-Nan Chang:
Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer. 1246-1259 - Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu:
Write Current Self-Configuration Scheme for MRAM Yield Improvement. 1260-1270 - Wanyong Tian, Yingchao Zhao, Liang Shi, Qing'an Li, Jianhua Li, Chun Jason Xue, Minming Li, Enhong Chen:
Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory. 1271-1284 - Oguzhan Atak, Abdullah Atalar:
BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture. 1285-1298 - Vadim Smolyakov, P. Glenn Gulak, Timothy Gallagher, Curtis Ling:
Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems. 1299-1307 - Hamid Shojaei, Azadeh Davoodi, Twan Basten:
Collaborative Multiobjective Global Routing. 1308-1321 - Jienan Chen, Jianhao Hu:
Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System. 1322-1332 - Katherine Shu-Min Li, Yi-Yu Liao:
IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test. 1333-1337 - Seong-In Hwang, Hanho Lee:
Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design. 1337-1341 - Luke Pierce, Spyros Tragoudas:
Enhanced Secure Architecture for Joint Action Test Group Systems. 1342-1345 - Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede:
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. 1346-1350 - Yangyang Pan, Guiqiang Dong, Tong Zhang:
Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes. 1350-1354 - Irith Pomeranz:
Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes. 1354-1359 - Irith Pomeranz:
Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests. 1359-1363 - Naveed Imran, Jooheung Lee, Ronald F. DeMara:
Fault Demotion Using Reconfigurable Slack (FaDReS). 1364-1368 - Jung-Hyun Park, Dong-Hoon Jung, Kyungho Ryu, Seong-Ook Jung:
ADDLL for Clock-Deskew Buffer in High-Performance SoCs. 1368-1373
Volume 21, Number 8, August 2013
- Ren-Jie Lee, Hsin-Wu Hsu, Hung-Ming Chen:
Board- and Chip-Aware Package Wire Planning. 1377-1387 - Zhuo Feng:
Scalable Multilevel Vectorless Power Grid Voltage Integrity Verification. 1388-1397 - Abdullah Nazma Nowroz, Gary L. Woods, Sherief Reda:
Power Mapping of Integrated Circuits Using AC-Based Thermography. 1398-1409 - Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni:
Nanomagnetic Logic Microprocessor: Hierarchical Power Model. 1410-1420 - Arun Palaniappan, Samuel Palermo:
A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures. 1421-1431 - Jacob Postman, Tushar Krishna, Christopher Edmonds, Li-Shiuan Peh, Patrick Chiang:
SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects. 1432-1446 - Hongyi Wang, Yanzhao Ma, Jun Cheng:
Soft-Start Method With Small Capacitor Charged by Pulse Current and Gain-Degeneration Error Amplifier for On-Chip DC-DC Power Converters. 1447-1453 - Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi, Mahdi Fazeli:
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems. 1454-1468 - Minoo Mirsaeedi, Andres J. Torres, Mohab H. Anis:
Litho-Friendly Decomposition Method for Self-Aligned Double Patterning. 1469-1480 - Ching-Te Chiu, Yu-Hao Hsu, Wei-Chih Lai, Jen-Ming Wu, Shawn S. H. Hsu, Yang-Syu Lin, Fanta Chen, Min-Sheng Kao, Yarsun Hsu:
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. 1481-1495 - Richard B. Wunderlich, Farhan Adil, Paul E. Hasler:
Floating Gate-Based Field Programmable Mixed-Signal Array. 1496-1505 - Yanjie Peng, Xinming Huang, Andrew G. Klein, Kai Zhang:
Design and Implementation of a Low-Complexity Symbol Detector for Sparse Channels. 1506-1515 - Dandan Chen, Kiat Seng Yeo, Xiaomeng Shi, Manh Anh Do, Chirn Chye Boon, Wei Meng Lim:
Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission. 1516-1525 - Zhuo Feng, Peng Li:
Fast Thermal Analysis on GPU for 3D ICs With Integrated Microchannel Cooling. 1526-1539 - Li Li, Ken Choi, Haiqing Nan:
Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration. 1540-1544 - Mohammad Esmaeildoust, Dimitrios Schinianakis, Hamid Javashi, Thanos Stouraitis, Keivan Navi:
Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$. 1545-1549 - Thinh Hung Pham, Suhaib A. Fahmy, Ian Vince McLoughlin:
Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA. 1549-1553 - Bosco Leung:
Design and Analysis of Saturated Ring Oscillators Based on the Random Mid-Point Voltage Concept. 1554-1557 - Masood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha P. Chandrakasan:
Technique for Efficient Evaluation of SRAM Timing Failure. 1558-1562 - HoonSeok Kim, Chanyoun Won, Paul D. Franzon:
Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding. 1562-1567 - Milad Mehri, Mohammad Hossein Mazaheri Kouhani, Nasser Masoumi, Reza Sarvari:
New Approach to VLSI Buffer Modeling, Considering Overshooting Effect. 1568-1572
Volume 21, Number 9, September 2013
- Guoqing Deng, Chunhong Chen:
Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors. 1573-1582 - Dongsoo Lee, Kaushik Roy:
Area Efficient ROM-Embedded SRAM Cache. 1583-1595 - Chengwu Tao, Ayman A. Fayed:
PWM Control Architecture With Constant Cycle Frequency Hopping and Phase Chopping for Spur-Free Operation in Buck Regulators. 1596-1607 - Jiann-Jong Chen, Ming-Xiang Lu, Tse-Hsu Wu, Yuh-Shyan Hwang:
Sub-1-V Fast-Response Hysteresis-Controlled CMOS Buck Converter Using Adaptive Ramp Techniques. 1608-1618 - Kyu-Nam Shim, Jiang Hu:
Boostable Repeater Design for Variation Resilience in VLSI Interconnects. 1619-1631 - Yoonmyung Lee, Daeyeon Kim, Jin Cai, Isaac Lauer, Leland Chang, Steven J. Koester, David T. Blaauw, Dennis Sylvester:
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs). 1632-1643 - Won Ho Park, Chih-Kong Ken Yang:
Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors. 1644-1654 - Yanheng Zhang, Chris Chu:
RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns. 1655-1668 - Chun-Yi Lee, Niraj K. Jha:
Variable-Pipeline-Stage Router. 1669-1682 - Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown:
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. 1683-1692 - Kalarikkal Absel, Lijo Manuel, R. K. Kavitha:
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic. 1693-1704 - Irith Pomeranz:
On Test Compaction of Broadside and Skewed-Load Test Cubes. 1705-1714 - Jaeyong Chung, Jacob A. Abraham:
Concurrent Path Selection Algorithm in Statistical Timing Analysis. 1715-1726 - Chi-Ying Lee, Chih-Cheng Hsieh, Jenn-Chyou Bor:
2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems. 1727-1737 - Guoqing Deng, Chunhong Chen:
A SET/MOS Hybrid Multiplier Using Frequency Synthesis. 1738-1742 - Chia-Min Chen, Tung-Wei Tsai, Chung-Chih Hung:
Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application. 1742-1747 - Shaowei Zhen, Xiaohui Zhu, Ping Luo, Yajuan He, Bo Zhang:
Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications. 1747-1751 - Yanheng Zhang, Chris Chu:
Fast and Effective Placement Refinement for Routability. 1751-1756 - Jun Lin, Zhiyuan Yan:
Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. 1756-1761 - Samah Mohamed Saeed, Ozgur Sinanoglu, Sobeeh Almukhaizim:
Predictive Techniques for Projecting Test Data Volume Compression. 1762-1766
Volume 21, Number 10, October 2013
- Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Enhancing the Efficiency of Energy-Constrained DVFS Designs. 1769-1782 - Eun Ju Hwang, Wook Kim, Young Hwan Kim:
Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization. 1783-1796 - Ching-Te Chiu, Wen-Chih Huang, Chih-Hsing Lin, Wei-Chih Lai, Ying-Fang Tsao:
Embedded Transition Inversion Coding With Low Switching Activity for Serial Links. 1797-1810 - Rajeev Narayanan, Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation. 1811-1822 - Yiyuan Xie, Mahdi Nikdast, Jiang Xu, Xiaowen Wu, Wei Zhang, Yaoyao Ye, Xuan Wang, Zhehui Wang, Weichen Liu:
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip. 1823-1836 - Austin C.-C. Chang, Ryan H.-M. Huang, Charles H.-P. Wen:
CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate. 1837-1848 - Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors. 1849-1862 - Hyunhee Kim, Jung Ho Ahn, Jihong Kim:
Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs. 1863-1877 - Mohammad Samie, Gabriel Dragffy, Andy M. Tyrrell, Tony Pipe, Paul Bremner:
Novel Bio-Inspired Approach for Fault-Tolerant VLSI Systems. 1878-1891 - Feng Shi, Xuebin Wu, Zhiyuan Yan:
New Crosstalk Avoidance Codes Based on a Novel Pattern Classification. 1892-1902 - Siddharth Garg, Diana Marculescu:
Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits. 1903-1914 - Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Wim Vanderbauwhede:
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. 1915-1927 - Shanshan Dai, Xiaofei Cao, Ting Yi, Allyn E. Hubbard, Zhiliang Hong:
1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique. 1928-1935 - Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low:
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$. 1936-1940 - Seyed Ebrahim Esmaeili, Asim J. Al-Khalili:
Integrated Power and Clock Distribution Network. 1941-1945 - Leonel Sousa, Samuel Antao, Ricardo Chaves:
On the Design of RNS Reverse Converters for the Four-Moduli Set ${\bf\{2^{\mmb n}+1, 2^{\mmb n}-1, 2^{\mmb n}, 2^{{\mmb n}+1}+1\}}$. 1945-1949 - Kisoo Kim, Hokyu Lee, Chulwoo Kim:
366-kS/s 1.09-nJ 0.0013-${\rm mm}^{2}$ Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock. 1950-1954 - Pekka Miettinen, Mikko Honkala, Janne Roos, Martti Valtonen:
Sparsification of Dense Capacitive Coupling of Interconnect Models. 1955-1959 - Yang Sun, Joseph R. Cavallaro:
VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight. 1960-1964
Volume 21, Number 11, November 2013
- Thomas Plos, Michael Hutter, Martin Feldhofer, Maksimiljan Stiglic, Francesco Cavaliere:
Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography. 1965-1974 - Ajay N. Bhoj, Niraj K. Jha:
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. 1975-1988 - Saleh Abdel-Hafeez, Ann Gordon-Ross, Behrooz Parhami:
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree. 1989-1998 - Shiann-Rong Kuang, Jiun-Ping Wang, Kai-Cheng Chang, Huan-Wei Hsu:
Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems. 1999-2009 - Fang Cai, Xinmiao Zhang:
Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes. 2010-2023 - Nicolas Laflamme-Mayer, Walder Andre, Olivier Valorge, Yves Blaquière, Mohamad Sawan:
Configurable Input-Output Power Pad for Wafer-Scale Microelectronic Systems. 2024-2033 - Vikram Chaturvedi, Tejasvi Anand, Bharadwaj Amrutur:
An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording. 2034-2044 - Bing Shi, Yufu Zhang, Ankur Srivastava:
Dynamic Thermal Management Under Soft Thermal Constraints. 2045-2054 - Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha:
Optimized Quantum Gate Library for Various Physical Machine Descriptions. 2055-2068 - Baker Mohammad, Dirar Homouz, Hazem Elgabra:
Robust Hybrid Memristor-CMOS Memory: Modeling and Design. 2069-2079 - Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, Chulwoo Kim:
10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation. 2080-2093 - Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. 2094-2105 - Ajay Kapoor, José Pineda de Gyvez:
Architectural Analysis for Wirelessly Powered Computing Platforms. 2106-2117 - Chih-Hao Chao, Kun-Chih Chen, An-Yeu Wu:
Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit. 2118-2131 - Hing-Kit Kwan, David C. W. Ng, Victor W. K. So:
Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency Modulation. 2132-2140 - Dominic DiTomaso, Randy Morris, Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri:
Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips. 2141-2154 - Jang-Woo Lee, Hong-Jung Kim, Chun-Seok Jeong, Jae-Jin Lee, Changsik Yoo:
Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface. 2155-2159 - Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee:
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation. 2160-2164
Volume 21, Number 12, December 2013
- Dawood Alnajiar, Hiroaki Konoura, Younghun Ko, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye:
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture. 2165-2178 - Ying Wang, Xuegong Zhou, Lingli Wang, Jian Yan, Wayne Luk, Chenglian Peng, Jiarong Tong:
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model. 2179-2192 - David B. Thomas, Wayne Luk:
Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs. 2193-2205 - Hyo-Jin Kim, Tai-Ji An, Sungmeen Myung, Seung-Hoon Lee:
Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 µm CMOS Analog-to-Digital Convertor. 2206-2213 - Sangwoo Han, Byung-Su Kim, Juho Kim:
Variation-Aware Aging Analysis in Digital ICs. 2214-2225 - Hu Xu, Vasilis F. Pavlidis, Xifan Tang, Wayne P. Burleson, Giovanni De Micheli:
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise. 2226-2239 - Pei-Ying Chao, Chao-Wen Tzeng, Shi-Yu Huang, Chia-Chieh Weng, Shan-Chien Fang:
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. 2240-2249 - Wei Li, Dian Zhou, Minghua Li, Binh P. Nguyen, Xuan Zeng:
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues. 2250-2261 - Liang Liu, Johan Löfgren, Peter Nilsson, Viktor Öwall:
VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems. 2262-2273 - Yuxiang Zheng, Jin Liu, Robert Payne, Mark Morgan, Hoi Lee:
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS. 2274-2285 - Martin Omaña, Daniele Rossi, Daniele Giaffreda, Roberto Specchia, Cecilia Metra, Marcin Marzencki, Bozena Kaminska:
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection. 2286-2294 - Dusko Karaklajic, Jörn-Marc Schmidt, Ingrid Verbauwhede:
Hardware Designer's Guide to Fault Attacks. 2295-2306 - Justin S. J. Wong, Peter Y. K. Cheung:
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability. 2307-2320 - Irith Pomeranz:
Functional Broadside Templates for Low-Power Test Generation. 2321-2325 - Jun Han, Shuai Wang, Wei Huang, Zhiyi Yu, Xiaoyang Zeng:
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. 2325-2330 - Hossein Mahdizadeh, Massoud Masoumi:
Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${\rm GF}(2^{163})$. 2330-2333 - Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro:
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation. 2334-2338 - Katherine Shu-Min Li:
Oscillation and Transition Tests for Synchronous Sequential Circuits. 2338-2343 - Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan:
High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000. 2343-2348 - Ruo-Ting Ding, Shi-Yu Huang, Chao-Wen Tzeng:
Cell-Based Process Resilient Multiphase Clock Generation. 2348-2352 - Natan Krihely, Sam Ben-Yaakov, Alexander Fish:
Efficiency Optimization of a Step-Down Switched Capacitor Converter for Subthreshold. 2353-2357
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