Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDJournal of Electronic Testing, Volume 30
Volume 30, Number 1, February 2014
- Ujjwal Guin, Daniel DiMase, Mohammad Tehranipoor:
Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead. 9-23 - Ujjwal Guin, Daniel DiMase, Mohammad Tehranipoor:
A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment. 25-40 - Michele Favalli
, Marcello Dalpasso:
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits. 41-55 - Bei Zhang, Vishwani D. Agrawal:
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs. 57-75 - K. Murali Krishna, M. Sailaja:
Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers. 77-85 - Ahmed Amine Rekik, Florence Azaïs, Frédérick Mailly, Pascal Nouet:
Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers. 87-100 - Junpeng Feng, Marvin Onabajo:
Wide Dynamic Range CMOS Amplifier Design for RF Signal Power Detection via Electro-Thermal Coupling. 101-109 - Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak:
Clock Faults Induced Min and Max Delay Violations. 111-123 - Sushmita Kadiyala Rao, Ryan W. Robucci, Chintan Patel:
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay. 125-147 - Yi Ren, Anlin He, Shuting Shi, Gang Guo, Li Chen, Shi-Jie Wen, Richard Wong, N. W. van Vonno, Bharat L. Bhuva:
Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser. 149-154
Volume 30, Number 2, April 2014
- Vishwani D. Agrawal:
Editorial. 155-156 - Test Technology Newsletter. 157-158
- Arthur Ceratti, Thiago Copetti, Letícia Maria Bolzani Poehls, Fabian Vargas, Rubem Dutra Ribeiro Fagundes:
An On-Chip Sensor to Monitor NBTI Effects in SRAMs. 159-169 - Worawit Somha, Hiroyuki Yamauchi:
An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions. 171-181 - Samuel Evain, Valentin Savin, Valentin Gherman:
Error Correction Schemes with Erasure Information for Fast Memories. 183-192 - Bahman Arasteh, Seyed Ghassem Miremadi, Amir Masoud Rahmani:
Developing Inherently Resilient Software Against Soft-Errors Based on Algorithm Level Inherent Features. 193-212 - Debesh Bhatta, Aritra Banerjee, Sabyasachi Deyati, Nicholas Tzou, Abhijit Chatterjee:
Low Cost Signal Reconstruction Based Testing of RF Components using Incoherent Undersampling. 213-228 - Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal:
A Test Time Theorem and its Applications. 229-236 - Haiying Yuan, Jiaping Mei, Hongying Song, Kun Guo:
Test Data Compression for System-on-a-Chip using Count Compatible Pattern Run-Length Coding. 237-242 - Yongle Xie, Xifeng Li, Sanshan Xie, Xuan Xie, Qizhong Zhou:
Soft Fault Diagnosis of Analog Circuits via Frequency Response Function Measurements. 243-249
Volume 30, Number 3, June 2014
- Vishwani D. Agrawal:
Editorial. 251-252 - Test Technology Newsletter. 253-254
- Tze Sin Tan, Bakhtiar Affendi Rosdi:
Verilog HDL Simulator Technology: A Survey. 255-269 - Pekka Miettinen, Mikko Honkala, Janne Roos, Martti Valtonen:
Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow. 271-285 - Mingsong Chen, Xiaoke Qin, Prabhat Mishra:
Learning-oriented Property Decomposition for Automated Generation of Directed Tests. 287-306 - Paolo Rech, Christopher Frost, Luigi Carro:
GPUs Neutron Sensitivity Dependence on Data Type. 307-316 - Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan:
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test. 317-328 - Efi Arvaniti, Yiorgos Tsiatouhas:
Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique. 329-341 - Chaolong Zhang, Yigang He, Lifen Yuan, Fangming Deng:
A Novel Approach for Analog Circuit Fault Prognostics Based on Improved RVM. 343-356 - Sandeep Miryala, Matheus Oleiro, Letícia Maria Bolzani Pöhls, Andrea Calimera, Enrico Macii, Massimo Poncino:
Modeling of Physical Defects in PN Junction Based Graphene Devices. 357-370 - Guohua Wang, Qiang Li, Xiaomei Chen, Xiaofeng Meng:
Research on the Efficiency Improvement of Design for Testability Using Test Point Allocation. 371-376 - Yi Ren, Li Chen:
The Effect of Temperature-Induced Quiescent Operating Point Shift on Single-Event Transient Sensitivity in Analog/Mixed-Signal Circuits. 377-382
Volume 30, Number 4, August 2014
- Vishwani D. Agrawal:
Editorial. 383-384 - Test Technology Newsletter. 385-386
- M. Maheswari, G. Seetharaman:
Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link. 387-400 - D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. 401-413 - Cherifa Tahanout, Hakim Tahi, Boualem Djezzar, Abdelmadjid Benabdelmoumene, Mohamed Goudjil, Bécharia Nadji:
An Accurate Combination of on-the-fly Interface Trap and Threshold Voltage Methods for NBTI Degradation Extraction. 415-423 - Anees Ullah, Luca Sterpone:
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. 425-442 - Mohamed A. El-Gamal, Abdel-Karim S. O. Hassan, Ahmad A. I. Ibrahim:
Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal Classifiers. 443-455 - Stefan R. Vock, Omar Escalona, Colin Turner, Frank J. Owens:
The Use of Software Engineering Methods for Efficacious Test Program Creation: A Supportive Evidence Based Case Study. 457-467 - Stefano Di Carlo, Marco Gaudesi, Edgar E. Sánchez, Matteo Sonza Reorda:
A Functional Approach for Testing the Reorder Buffer Memory. 469-481 - Deliang Li, Kaoli Huang, Changlong Wang:
Fault Detection of Linear Analog Integrated Circuit in Network. 483-489
Volume 30, Number 5, October 2014
- Vishwani D. Agrawal:
Editorial. 491-492 - Test Technology Newsletter. 493-494
- Pulkit Bhatnagar, Sachin Garg:
Dynamic Threshold Delay Characterization Model for Improved Static Timing Analysis. 495-504 - Tao Xie, Yigang He:
Fault Diagnosis of Analog Circuit Based on High-Order Cumulants and Information Fusion. 505-514 - Sen-Wen Hsiao, Xian Wang, Abhijit Chatterjee:
Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters. 515-526 - Laura Rodríguez Gómez, Alejandro Cook, Thomas Indlekofer, Sybille Hellebrand, Hans-Joachim Wunderlich:
Adaptive Bayesian Diagnosis of Intermittent Faults. 527-540 - Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray:
Intra-Cell Defects Diagnosis. 541-555 - Stephan Eggersglüß:
Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets. 557-567 - Spencer K. Millican, Kewal K. Saluja:
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling. 569-580 - Mafalda Cortez, Gijs Roelofs, Said Hamdioui, Giorgio Di Natale:
Testing Methods for PUF-Based Secure Key Storage Circuits. 581-594 - Hoda Pahlevanzadeh, Qiaoyan Yu:
A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients. 595-609 - Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine:
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. 611-627 - Zhigang Wang, Lianping Guo, Shulin Tian, Tao Liu:
Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs. 629-635
Volume 30, Number 6, December 2014
- Vishwani D. Agrawal:
Editorial. 637-638 - 2013 JETTA-TTTC Best Paper Award. 639-640
- Test Technology Newsletter. 641-642
- Chih-Sheng Hou, Jin-Fu Li:
Testing Disturbance Faults in Various NAND Flash Memories. 643-652 - Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi:
A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. 653-663 - Yujia Peng, B. M. Farid Rahman, TengXing Wang, Guoan Wang, Xinchuan Liu, Xuejun Wen:
Characterization of a Passive Telemetric System for ISM Band Pressure Sensors. 665-671 - Wei-Cheng Lien, Kuen-Jong Lee, Tong-Yu Hsieh, Krishnendu Chakrabarty:
Efficient LFSR Reseeding Based on Internal-Response Feedback. 673-685 - Tong-Yu Hsieh, Yi-Han Peng, Kuan-Hsien Li:
Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation. 687-699 - Shakeb Ahmad Khan, Tariqul Islam, Neeraj Khera, A. K. Agarwala:
On-line Condition Monitoring and Maintenance of Power Electronic Converters. 701-709 - Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Access Port Protection for Reconfigurable Scan Networks. 711-723 - Xiaofei Guo, Ramesh Karri:
Low-Cost Concurrent Error Detection for GCM and CCM. 725-737 - Reza Omidi Gosheblagh, Karim Mohammadi:
Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators. 739-749 - Haibin Wang, Mulong Li, Li Chen, Rui Liu, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong, Rita Fung, Jinshun Bi:
Single Event Resilient Dynamic Logic Designs. 751-761 - Yu Zhang, Bei Zhang, Vishwani D. Agrawal:
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools. 763-780
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-19 20:16 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
