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2020 – today
- 2023
[j148]Zhi-Heng Kang
, Shen-Iuan Liu:
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation. IEEE J. Solid State Circuits 58(3): 806-816 (2023)- 2022
- [j147]Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu:
A Wide-Range FD for Referenceless Baud-Rate CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 60-64 (2022) - [j146]Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu:
A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 269-273 (2022) - [j145]Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu:
A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 894-898 (2022) - [j144]Jia-Rong Chang, Shen-Iuan Liu:
A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2026-2030 (2022) - [j143]Wen-Chi Huang, Shen-Iuan Liu:
A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit. IEEE Trans. Circuits Syst. II Express Briefs 69(12): 4709-4713 (2022) - [j142]Yao-Hung Tsai, Shen-Iuan Liu:
A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 30(7): 905-914 (2022) - [c56]Zhi-Heng Kang, Yu-Chi Yen, Guan-Yu Su, Shen-Iuan Liu:
An Adaptive Digital PLL Based on BBPFD Transition Probability. VLSI-DAT 2022: 1-4 - [c55]Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu:
An Injection-Locked Clock Multiplier With Injection Strength Calibration. VLSI-DAT 2022: 1-4 - 2021
- [j141]Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu:
A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4566-4575 (2021) - [j140]Shun-Chi Chang, Shen-Iuan Liu:
A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 161-165 (2021) - [j139]Yong-Ru Lu, Shen-Iuan Liu, Yu-Che Yang, Han-Chang Kang, Chih-Lung Chen, Ka-Un Chan, Ying-Hsi Lin:
A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 873-877 (2021) - [j138]Ming-Han Chou, Shen-Iuan Liu:
A Type-I PLL With Foreground Loop Bandwidth Calibration. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1103-1107 (2021) - [j137]Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu:
A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1837-1841 (2021) - [c54]Guan-Yu Su, Zhi-Heng Kang, Shen-Iuan Liu:
An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique. VLSI-DAT 2021: 1-4 - [c53]Yen-Min Tseng, Yu-Chi Yen, Shen-Iuan Liu:
A Digital Phase-Locked Loop With Background Supply Noise Cancellation. VLSI-DAT 2021: 1-4 - 2020
- [j136]Chung-Jen Kuo, Shen-Iuan Liu:
A 13.56 MHz Current-Mode Wireless Power Receiver With Energy-Investment Capability. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 205-209 (2020) - [j135]Guan-Yu Su, Shen-Iuan Liu:
A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2169-2179 (2020) - [j134]Ming-Chia Chang, Shen-Iuan Liu:
An Indoor Photovoltaic Energy Harvester Using Time-Based MPPT and On-Chip Photovoltaic Cell. IEEE Trans. Circuits Syst. 67-II(11): 2432-2436 (2020) - [j133]Kuan-Lin Fu, Shen-Iuan Liu:
A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration. IEEE Trans. Very Large Scale Integr. Syst. 28(7): 1726-1735 (2020) - [j132]Ming-Han Chou, Shen-Iuan Liu:
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2474-2478 (2020) - [c52]Ming-Chia Chang, Min-Hsuan Wu, Shen-Iuan Liu:
A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [j131]Che-Wei Tien, Shen-Iuan Liu:
A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 177-181 (2019) - [j130]Cheng-En Hsieh, Shen-Iuan Liu:
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 501-510 (2019) - [j129]Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu:
An On-Chip Relaxation Oscillator With Comparator Delay Compensation. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 969-973 (2019) - [j128]Yi-An Chang, Shen-Iuan Liu:
A 13.4-MHz Relaxation Oscillator With Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1725-1729 (2019) - [j127]Yu-Kai Chiu, Shen-Iuan Liu:
A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2698-2702 (2019) - [c51]Yuan Cheng Qian, Yen-Yu Chao, Shen-Iuan Liu:
A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time. A-SSCC 2019: 95-98 - 2018
- [j126]Che-Wei Tien, Shen-Iuan Liu:
A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1830-1839 (2018) - [c50]Ye-Sing Luo, Hsing-Hung Lin, Shen-Iuan Liu:
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control. A-SSCC 2018: 39-42 - [c49]San-Liang Lee, Jyehong Chen, Shen-Iuan Liu, Chang-Fa Yang, Hen-Wai Tsao, Shih-Hsiang Hsu, Chien-Chung Lin, Chun-Liang Yang, Zhong Jie Zhang, Kuan-Lin Fu, Lung Wei Chung, Tomas Pankra:
Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect. WOCC 2018: 1-4 - 2017
- [j125]Ye-Sing Luo, Shen-Iuan Liu:
A Voltage Multiplier With Adaptive Threshold Voltage Compensation. IEEE J. Solid State Circuits 52(8): 2208-2214 (2017) - [j124]Yen-Hsiang Tseng, Che-Wei Yeh, Shen-Iuan Liu:
A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 811-822 (2017) - [j123]Wun-Jian Su, Shen-Iuan Liu:
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 959-968 (2017) - [j122]Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu:
A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(6): 645-649 (2017) - [j121]Kuan-Yu Chen, Wei-Yung Chen, Shen-Iuan Liu:
A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS. IEEE Trans. Circuits Syst. II Express Briefs 64-II(11): 1282-1286 (2017) - [c48]Kuan-Lin Fu, Shen-Iuan Liu:
A 56Gbps PAM-4 optical receiver front-end. A-SSCC 2017: 77-80 - 2016
- [j120]Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. IEEE J. Solid State Circuits 51(2): 412-427 (2016) - [j119]Ting-Kuei Kuan, Shen-Iuan Liu:
A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques. IEEE J. Solid State Circuits 51(4): 821-831 (2016) - [j118]Liang-Jen Chen, Shen-Iuan Liu:
A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 126-130 (2016) - [j117]Chih-Lu Wei, Shen-Iuan Liu:
A Digital PLL Using Oversampling Delta-Sigma TDC. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 633-637 (2016) - [j116]Liang-Jen Chen, Shen-Iuan Liu:
A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1470-1483 (2016) - [c47]Chi-Huan Chiang, Chang-Cheng Huang, Ting-Kuei Kuan, Shen-Iuan Liu:
A digital MDLL using switched biasing technique to reduce low-frequency phase noise. A-SSCC 2016: 101-104 - [c46]Che-Wei Yeh, Cheng-En Hsieh, Shen-Iuan Liu:
19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation. ISSCC 2016: 332-333 - 2015
- [j115]Chih-Lu Wei, Ting-Kuei Kuan, Shen-Iuan Liu:
A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth. IEEE Trans. Circuits Syst. II Express Briefs 62-II(6): 548-552 (2015) - [j114]Ting-Kuei Kuan, Shen-Iuan Liu:
A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(7): 1873-1882 (2015) - [j113]Kai-Hui Zeng, Ting-Kuei Kuan, Shen-Iuan Liu:
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1033-1037 (2015) - [c45]Chi-Huan Chiang, Chang-Cheng Huang, Shen-Iuan Liu:
A digital bang-bang phase-locked loop with bandwidth calibration. A-SSCC 2015: 1-4 - [c44]Ting-Kuei Kuan, Shen-Iuan Liu:
A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction. VLSIC 2015: 138- - 2014
- [j112]I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu:
An All-Digital Despreading Clock Generator. IEEE Trans. Circuits Syst. II Express Briefs 61-II(1): 16-20 (2014) - [j111]Yu-Hsuan Chiang, Shen-Iuan Liu:
Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient. IEEE Trans. Circuits Syst. II Express Briefs 61-II(9): 661-665 (2014) - [j110]Yu-Hsun Chien, Kuan-Lin Fu, Shen-Iuan Liu:
A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 845-849 (2014) - [c43]Ting-Kuei Kuan, Yu-Hsuan Chiang, Shen-Iuan Liu:
A 0.43pJ/bit true random number generator. A-SSCC 2014: 33-36 - [c42]Ye-Sing Luo, Shen-Iuan Liu:
A low-input-swing AC-DC voltage multiplier using Schottky diodes. A-SSCC 2014: 245-248 - [c41]Yuan-Fu Lin, Chang-Cheng Huang, Jiunn-Yih Max Lee, Chih-Tien Chang, Shen-Iuan Liu:
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting. A-SSCC 2014: 273-276 - [c40]Chien-Kai Kao, Kuan-Lin Fu, Shen-Iuan Liu:
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop. A-SSCC 2014: 281-284 - [c39]Cheng-En Hsieh, Shen-Iuan Liu:
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS. A-SSCC 2014: 325-328 - [c38]Shih-Hsiang Shen, Chung-Yi Ting, Chi-Yun Liu, Hua Cheng, Shen-Iuan Liu, Chih-Ting Lin:
A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis. BHI 2014: 660-663 - 2013
- [j109]Shih-Yuan Kao, Shen-Iuan Liu:
A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection. IEEE J. Solid State Circuits 48(2): 391-404 (2013) - [j108]Pin-Hao Feng, Shen-Iuan Liu:
Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS. IEEE J. Solid State Circuits 48(2): 405-416 (2013) - [j107]Yi-Chieh Huang, Shen-Iuan Liu:
A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing. IEEE J. Solid State Circuits 48(2): 417-428 (2013) - [j106]Shih-Yuan Kao, Shen-Iuan Liu:
A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection. IEEE J. Solid State Circuits 48(11): 2815-2826 (2013) - [j105]Yan-Yu Lin, Shen-Iuan Liu:
4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation. IEEE Trans. Circuits Syst. II Express Briefs 60-II(5): 252-256 (2013) - [j104]I-Ting Lee, Kai-Hui Zeng, Shen-Iuan Liu:
A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB. IEEE Trans. Circuits Syst. II Express Briefs 60-II(9): 547-551 (2013) - [j103]Yan-Yu Lin, Shen-Iuan Liu:
4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 622-626 (2013) - [j102]I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu:
An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2813-2822 (2013) - [j101]Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu:
Ultrasonic Power/Data Telemetry and Neural Stimulator With OOK-PM Signaling. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 827-831 (2013) - [j100]Yu-Hsuan Chiang, Shen-Iuan Liu:
A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 837-841 (2013) - [j99]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 250-258 (2013) - [c37]I-Ting Lee, Yen-Jen Chen, Shen-Iuan Liu, Chewnpu Jou, Fu-Lung Hsueh, Hsieh-Hung Hsieh:
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. ISSCC 2013: 414-415 - [c36]Ye-Sing Luo, Jiun-Ru Wang, Wei-Jen Huang, Je-Yu Tsai, I-Chin Wu, Yi-Fang Liao, Wan-Ting Tseng, Chen-Tung Yen, Pai-Chi Li, Shen-Iuan Liu:
Ultrasonic telemetry and neural stimulator with FSK-PWM signaling. VLSI-DAT 2013: 1-4 - 2012
- [j98]Shen-Iuan Liu, Tsung-Hsien Lin, Woogeun Rhee:
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 47(11): 2551-2553 (2012) - [j97]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology. IEEE J. Solid State Circuits 47(11): 2693-2700 (2012) - [j96]Ke-Hou Chen, Shen-Iuan Liu:
Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(2): 305-314 (2012) - [j95]I-Ting Lee, Shen-Iuan Liu:
G-Band Injection-Locked Frequency Dividers Using π-type LC Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(2): 315-323 (2012) - [j94]Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu:
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 148-152 (2012) - [j93]I-Ting Lee, Hung-Yu Lu, Shen-Iuan Liu:
A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique. IEEE Trans. Circuits Syst. II Express Briefs 59-II(5): 267-271 (2012) - [j92]Kun-Hung Tsai, Shen-Iuan Liu:
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 80-88 (2012) - [c35]Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen:
A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. ISSCC 2012: 244-246 - [c34]Yi-Chieh Huang, Shen-Iuan Liu:
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. ISSCC 2012: 338-340 - [c33]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A fast-locking phase-locked loop using CP control and gated VCO. VLSI-DAT 2012: 1-4 - 2011
- [j91]Bo-Yu Lin, Shen-Iuan Liu:
Analysis and Design of D-Band Injection-Locked Frequency Dividers. IEEE J. Solid State Circuits 46(6): 1250-1264 (2011) - [j90]Chao-Ching Hung, Shen-Iuan Liu:
A Noise Filtering Technique for Fractional-N Frequency Synthesizers. IEEE Trans. Circuits Syst. II Express Briefs 58-II(3): 139-143 (2011) - [j89]Chao-Ching Hung, Shen-Iuan Liu:
A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 58-II(6): 321-325 (2011) - [j88]Chang-Lin Hsieh, Shen-Iuan Liu:
A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 487-491 (2011) - [j87]Wei-Jen Huang, Shigeisa Nagayasu, Shen-Iuan Liu:
A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(8): 1761-1772 (2011) - [j86]Bo-Yu Lin, Shen-Iuan Liu:
A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 617-621 (2011) - [j85]Chang-Lin Hsieh, Shen-Iuan Liu:
Decision Feedback Equalizers Using the Back-Gate Feedback Technique. IEEE Trans. Circuits Syst. II Express Briefs 58-II(12): 897-901 (2011) - [j84]Shih-Yuan Kao, Shen-Iuan Liu:
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 592-602 (2011) - [c32]I-Ting Lee, Chiao-Hsing Wang, Shen-Iuan Liu:
3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS. A-SSCC 2011: 93-96 - [c31]I-Ting Lee, Yun-Ta Tsai, Shen-Iuan Liu:
A leakage-current-recycling phase-locked loop in 65nm CMOS technology. A-SSCC 2011: 137-140 - [c30]Yi-Chieh Huang, Shen-Iuan Liu:
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization. ISSCC 2011: 356-358 - [c29]Yu-Ming Ying, Shen-Iuan Liu:
A 20Gb/s digitally adaptive equalizer/DFE with blind sampling. ISSCC 2011: 444-446 - 2010
- [j83]Jian-Hao Lu, Shen-Iuan Liu:
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers. IEEE J. Solid State Circuits 45(2): 433-446 (2010) - [j82]Mu-Chen Huang, Shen-Iuan Liu:
A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 11-15 (2010) - [j81]Shih-Yuan Kao, Shen-Iuan Liu:
A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 178-182 (2010) - [j80]Shih-Yuan Kao, Shen-Iuan Liu:
A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 319-323 (2010) - [j79]Jung-Yu Chang, Shen-Iuan Liu:
A Phase-Locked Loop With Background Leakage Current Compensation. IEEE Trans. Circuits Syst. II Express Briefs 57-II(9): 666-670 (2010)
2000 – 2009
- 2009
- [j78]Jung-Yu Chang, Shen-Iuan Liu:
A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS. IET Circuits Devices Syst. 3(6): 350-358 (2009) - [j77]Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, Shen-Iuan Liu:
A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. IEEE J. Solid State Circuits 44(3): 775-783 (2009) - [j76]Sheng-You Lin, Shen-Iuan Liu:
A 1.5 GHz All-Digital Spread-Spectrum Clock Generator. IEEE J. Solid State Circuits 44(11): 3111-3119 (2009) - [j75]Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu:
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 97-101 (2009) - [j74]Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu:
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 107-111 (2009) - [j73]Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu:
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 142-146 (2009) - [j72]Mu-Chen Huang, Shen-Iuan Liu:
A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 369-373 (2009) - [j71]Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu:
Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology". IEEE Trans. Circuits Syst. II Express Briefs 56-II(6): 519 (2009) - [j70]Chao-Ching Hung, Shen-Iuan Liu:
A Leakage-Compensated PLL in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 525-529 (2009) - [j69]I-Hsin Wang, Hwei-Yu Lee, Shen-Iuan Liu:
An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 545-549 (2009) - [j68]I-Ting Lee, Kun-Hung Tsai, Shen-Iuan Liu:
A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider. IEEE Trans. Circuits Syst. II Express Briefs 56-II(7): 555-559 (2009) - [j67]Jian-Hao Lu, Shen-Iuan Liu:
A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 56-II(10): 783-787 (2009) - [j66]Chi-Nan Chuang, Shen-Iuan Liu:
A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 850-854 (2009) - [c28]Hwei-Yu Lee, Shen-Iuan Liu:
A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage. ISCAS 2009: 976-979 - [c27]Kun-Hung Tsai, Shen-Iuan Liu:
A 43.7mW 96GHz PLL in 65nm CMOS. ISSCC 2009: 276-277 - [c26]Bo-Yu Lin, Kun-Hung Tsai, Shen-Iuan Liu:
A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS. ISSCC 2009: 282-283 - [c25]Chao-Ching Hung, Shen-Iuan Liu:
A leakage-suppression technique for phase-locked systems in 65nm CMOS. ISSCC 2009: 400-401 - 2008
- [j65]