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ORCIDSeng-Pan U
Seng-Pan U. – Ben Seng-Pan U – 余成斌
Person information
- unicode name: 余成斌
- affiliation: University of Macau, China
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2020 – today
- 2021
[j45]Yue Yin
, Syed Muhammad Abubakar, Songyao Tan, Jiahua Shi, Peilin Yang, Wendi Yang, Hanjun Jiang, Zhihua Wang, Wen Jia, Seng-Pan U:
A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device. IEEE Trans. Biomed. Circuits Syst. 15(4): 777-790 (2021)- [c96]Syed Muhammad Abubakar, Yue Yin, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia:
A 2.52 μΑ Wearable Single Lead Ternary Neural Network Based Cardiac Arrhythmia Detection Processor. ISCAS 2021: 1-4 - [c95]Denis Daly, Zeynep Lulec, Rabia Tugce Yazicigil, Alison J. Burdett, Rituparna Mandal, Matheus Moreira, Dante G. Muratore, Aisha Walcott-Bryant, Ben Seng-Pan U:
SE5: Making a Career Choice. ISSCC 2021: 546-547 - 2020
- [c94]Yue Yin, Syed Muhammad Abubakar, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia:
A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift. A-SSCC 2020: 1-4
2010 – 2019
- 2019
- [j44]Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. IEEE J. Solid State Circuits 54(4): 1161-1172 (2019) - [j43]Dezhi Xing, Yan Zhu, Chi-Hang Chan, Franco Maloberti, Seng-Pan U, Rui Paulo Martins:
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 489-501 (2019) - [j42]Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 481-485 (2019) - [c93]Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. A-SSCC 2019: 117-120 - [c92]Junhao Liang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, Hanjun Jiang:
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. A-SSCC 2019: 309-312 - 2018
- [j41]Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins:
An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator. IEEE J. Solid State Circuits 53(1): 20-34 (2018) - [j40]Chi-Hang Chan, Yan Zhu, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins:
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits 53(3): 850-860 (2018) - [j39]Wei Wei Qin, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Quick and cost-efficient A/D converter static characterization using low-precision testing signal. Microelectron. J. 74: 86-93 (2018) - [j38]Xiaofeng Yang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1819-1829 (2018) - [j37]Yan Song, Chi-Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, Rui Paulo Martins:
Passive Noise Shaping in SAR ADC With Improved Efficiency. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 416-420 (2018) - [j36]Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U:
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 572-583 (2018) - [j35]Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2279-2289 (2018) - [c91]Junmin Jiang, Yan Lu, Xun Liu, Wing-Hung Ki, Philip K. T. Mok, Seng-Pan U, Rui Paulo Martins:
A dual-output SC converter with dynamic power allocation for multicore application processors. ASP-DAC 2018: 285-286 - [c90]Wenning Jiang, Yan Zhu, Chi-Hang Chan, Boris Murmann, Seng-Pan U, Rui Paulo Martins:
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. A-SSCC 2018: 235-238 - [c89]Fangyu Mao, Yan Lu, Jie Lin, Chenchang Zhan, Seng-Pan U, Rui Paulo Martins:
A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT. ISCAS 2018: 1-4 - [c88]Fangyu Mao, Yan Lu, Seng-Pan U., Rui Paulo Martins:
A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency. ISSCC 2018: 140-142 - [c87]Fangyu Mao, Yan Lu, Seng-Pan U, Rui Paulo Martins:
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems. VLSI-DAT 2018: 1-4 - [c86]Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. VLSI Circuits 2018: 207-208 - 2017
- [j34]Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins:
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. IEEE J. Solid State Circuits 52(10): 2576-2588 (2017) - [j33]Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A sub-1V 78-nA bandgap reference with curvature compensation. Microelectron. J. 63: 35-40 (2017) - [j32]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, Seng-Pan U, Rui Paulo Martins:
Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 111-115 (2017) - [j31]Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 166-170 (2017) - [j30]Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1684-1695 (2017) - [j29]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 1966-1976 (2017) - [j28]Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(10): 2641-2654 (2017) - [j27]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 354-363 (2017) - [j26]Arshad Hussain, Sai-Weng Sin, Chi-Hang Chan, Ben Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 364-374 (2017) - [j25]Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins:
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1168-1172 (2017) - [c85]U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. A-SSCC 2017: 221-224 - [c84]Wei Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. A-SSCC 2017: 285-288 - [c83]Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. ESSCIRC 2017: 239-242 - [c82]Chi-Wa U, Chi-Seng Lam, Man-Kay Law, Sai-Weng Sin, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins:
CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. IECON 2017: 4867-4871 - [c81]Xia Du, Chi-Seng Lam, Sai-Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins:
A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. ISIE 2017: 561-564 - [c80]Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins:
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. ISSCC 2017: 282-283 - [c79]Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins:
20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. ISSCC 2017: 342-343 - [c78]Junmin Jiang, Yan Lu, Wing-Hung Ki, Seng-Pan U, Rui Paulo Martins:
20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS. ISSCC 2017: 344-345 - [c77]Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins:
22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency. ISSCC 2017: 376-377 - [c76]Kostas Doris, David Robertson, Seung-Tak Ryu, Seng-Pan U:
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. ISSCC 2017: 515-517 - 2016
- [j24]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits 51(2): 365-377 (2016) - [j23]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. IEEE J. Solid State Circuits 51(5): 1223-1234 (2016) - [j22]Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 683-687 (2016) - [j21]Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Wing-Hung Ki:
Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 903-907 (2016) - [j20]Yan Zhu, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins:
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1203-1207 (2016) - [j19]Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins:
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2603-2607 (2016) - [c75]Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins:
A digital LDO with transient enhancement and limit cycle oscillation reduction. APCCAS 2016: 25-28 - [c74]Yuan Ren, Sai-Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins:
A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. A-SSCC 2016: 57-60 - [c73]Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U:
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration. A-SSCC 2016: 77-80 - [c72]Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins:
A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. A-SSCC 2016: 145-148 - [c71]Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. ESSCIRC 2016: 169-172 - [c70]Wei Li, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. ISIC 2016: 1-4 - 2015
- [j18]Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(9): 2196-2206 (2015) - [c69]Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC 2015: 1-4 - [c68]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC 2015: 1-3 - [c67]Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. ISSCC 2015: 1-3 - 2014
- [j17]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 372-383 (2014) - [c66]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. ESSCIRC 2014: 211-214 - [c65]Da Feng, Franco Maloberti, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. ISCAS 2014: 1348-1351 - 2013
- [j16]Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. IEEE J. Solid State Circuits 48(8): 1783-1794 (2013) - [j15]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits 48(9): 2154-2169 (2013) - [c64]Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. ISCAS 2013: 373-376 - [c63]Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS 2013: 2239-2242 - [c62]Li Ding, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. MWSCAS 2013: 665-668 - 2012
- [j14]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits 47(11): 2614-2626 (2012) - [j13]He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47(11): 2763-2772 (2012) - [c61]Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. APCCAS 2012: 29-32 - [c60]Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. APCCAS 2012: 33-36 - [c59]Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. APCCAS 2012: 268-271 - [c58]Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. CICC 2012: 1-4 - [c57]Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins:
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. ESSCIRC 2012: 265-268 - [c56]Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins:
A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. ESSCIRC 2012: 377-380 - [c55]Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. ISCAS 2012: 65-68 - [c54]Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
An ELD tracking compensation technique for active-RC CT ΣΔ modulators. MWSCAS 2012: 1096-1099 - [c53]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC 2012: 86-87 - [c52]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC 2012: 90-91 - 2011
- [c51]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. A-SSCC 2011: 61-64 - [c50]Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC 2011: 73-76 - [c49]Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC 2011: 233-236 - [c48]U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC 2011: 363-366 - [c47]Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Hybrid loopfilter sigma-delta modulator with NTF zero compensation. ISOCC 2011: 76-79 - [c46]He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC 2011: 188-190 - 2010
- [j12]Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. IET Circuits Devices Syst. 4(1): 1-13 (2010) - [j11]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits 45(6): 1111-1121 (2010) - [j10]He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 57-II(1): 16-20 (2010) - [j9]U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. Circuits Syst. II Express Briefs 57-II(8): 607-611 (2010) - [j8]Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design 2010: 706548:1-706548:8 (2010) - [c45]Li Ding, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. APCCAS 2010: 208-211 - [c44]Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. APCCAS 2010: 1011-1014 - [c43]Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC 2010: 218-221 - [c42]Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. ICECS 2010: 547-550 - [c41]Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang:
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS 2010: 878-881 - [c40]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS 2010: 4061-4064
2000 – 2009
- 2008
- [j7]Pui-In Mak, Seng-Pan U., Rui Paulo Martins:
On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(2): 496-509 (2008) - [j6]Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins:
Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 648-652 (2008) - [j5]Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(8): 2188-2201 (2008) - [c39]Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins:
A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. APCCAS 2008: 276-279 - [c38]Ngai Kong, Seng-Pan U, Rui Paulo Martins:
A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller. APCCAS 2008: 396-399 - [c37]Kim-Fai Wong, Ka-Ian Lei, Seng-Pan U, Rui Paulo da Silva Martins:
A 1-V 90dB DR audio stereo DAC with embedding headphone driver. APCCAS 2008: 1160-1163 - [c36]U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins:
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS 2008: 1164-1167 - [c35]He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins:
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS 2008: 1192-1195 - [c34]Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS 2008: 642-645 - [c33]