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2020 – today
- 2020
[j132]Leibo Liu
, Jianfeng Zhu, Zhaoshi Li, Yanan Lu, Yangdong Deng, Jie Han, Shouyi Yin, Shaojun Wei:
A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy, Challenges, and Applications. ACM Comput. Surv. 52(6): 118:1-118:39 (2020)- [j131]Guiqiang Peng, Leibo Liu, Sheng Zhou, Shouyi Yin, Shaojun Wei:
A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection. IEEE J. Solid State Circuits 55(2): 505-519 (2020) - [j130]Neng Zhang, Qiao Qin, Hang Yuan, Chenggao Zhou, Shouyi Yin, Shaojun Wei, Leibo Liu:
NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication. IEEE Trans. Computers 69(4): 520-533 (2020) - [j129]Umamaheswara Rao Tida, Cheng Zhuo, Leibo Liu, Yiyu Shi:
Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 281-293 (2020) - [j128]Yibo Wu, Leibo Liu, Liang Wang, Xiaohang Wang, Jie Han, Chenchen Deng, Shaojun Wei:
Aggressive Fine-Grained Power Gating of NoC Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3177-3189 (2020) - [j127]Shixuan Zheng, Xianjue Zhang, Daoli Ou, Shibin Tang, Leibo Liu, Shaojun Wei, Shouyi Yin:
Efficient Scheduling of Irregular Network Structures on CNN Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3408-3419 (2020) - [j126]Chenchen Deng, Bo Wang, Leibo Liu, Min Zhu, Youyu Wu, Hui Li, Shouyi Yin, Shaojun Wei:
A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 375-379 (2020) - [j125]Neng Zhang, Bohan Yang, Chen Chen, Shouyi Yin, Shaojun Wei, Leibo Liu:
Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(2): 49-72 (2020) - [j124]Huiyu Mo, Leibo Liu, Wenping Zhu, Qiang Li, Hong Liu, Shouyi Yin, Shaojun Wei:
A Multi-Task Hardwired Accelerator for Face Detection and Alignment. IEEE Trans. Circuits Syst. Video Technol. 30(11): 4284-4298 (2020) - [j123]Liang Wang, Leibo Liu, Jie Han, Xiaohang Wang, Shouyi Yin, Shaojun Wei:
Achieving Flexible Global Reconfiguration in NoCs Using Reconfigurable Rings. IEEE Trans. Parallel Distributed Syst. 31(3): 611-622 (2020) - [j122]Leibo Liu, Xingchen Man, Jianfeng Zhu, Shouyi Yin, Shaojun Wei:
Pattern-Based Dynamic Compilation System for CGRAs With Online Configuration Transformation. IEEE Trans. Parallel Distributed Syst. 31(12): 2981-2994 (2020) - [j121]Leibo Liu, Guiqiang Peng, Pan Wang, Sheng Zhou, Qiushi Wei, Shouyi Yin, Shaojun Wei:
Energy- and Area-Efficient Recursive-Conjugate-Gradient-Based MMSE Detector for Massive MIMO Systems. IEEE Trans. Signal Process. 68: 573-588 (2020) - [j120]Pan Wang, Leibo Liu, Sheng Zhou, Guiqiang Peng, Shouyi Yin, Shaojun Wei:
Near-Optimal MIMO-SCMA Uplink Detection With Low-Complexity Expectation Propagation. IEEE Trans. Wirel. Commun. 19(2): 1025-1037 (2020) - [c105]Liang Wang, Leibo Liu, Xiaohang Wang, Jie Han, Chenchen Deng, Shaojun Wei:
CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology. DAC 2020: 1-6 - [c104]Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. DAC 2020: 1-6 - [c103]Ning Li, Leibo Liu, Shaojun Wei, Shouyi Yin:
A High-performance Inference Accelerator Exploiting Patterned Sparsity in CNNs. FCCM 2020: 243 - [c102]Peishuo Li, Zihang Jiang, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei:
PAGAN: A Phase-Adapted Generative Adversarial Networks for Speech Enhancement. ICASSP 2020: 6234-6238 - [c101]Yanan Lu, Leibo Liu, Jian Liu, Shouyi Yin, Shaojun Wei:
A Reconfigurable Branch Predictor for Spatial Computing Architectures. ICDSP 2020: 295-299 - [c100]Yifan Yang, Zhaoshi Li, Yangdong Deng, Zhiwei Liu, Shouyi Yin, Shaojun Wei, Leibo Liu:
GraphABCD: Scaling Out Graph Analytics with Asynchronous Block Coordinate Descent. ISCA 2020: 419-432 - [c99]Dibei Chen, Zhaoshi Li, Tianzhu Xiong, Zhiwei Liu, Jun Yang, Shouyi Yin, Shaojun Wei, Leibo Liu:
CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. MICRO 2020: 342-355 - [c98]Huiyu Mo, Leibo Liu, Wenjing Hu, Wenping Zhu, Qiang Li, Ang Li, Shouyi Yin, Jian Chen, Xiaowei Jiang, Shaojun Wei:
TFE: Energy-efficient Transferred Filter-based Engine to Compress and Accelerate Convolutional Neural Networks. MICRO 2020: 751-765 - [i2]Yihong Zhu, Min Zhu, Bohan Yang, Wenping Zhu, Chenchen Deng, Chen Chen, Shaojun Wei, Leibo Liu:
A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm. IACR Cryptol. ePrint Arch. 2020: 1037 (2020)
2010 – 2019
- 2019
- [b1]Leibo Liu, Guiqiang Peng, Shaojun Wei:
Massive MIMO Detection Algorithm and VLSI Architecture. Springer 2019, ISBN 978-981-13-6361-0, pp. 1-336 - [j119]Dawei Li, Xiaowei Xu, Leibo Liu, Li Zhang, Cheng Zhuo, Yiyu Shi:
Optimal design of a low-power, phase-switching modulator for implantable medical applications. Integr. 69: 289-300 (2019) - [j118]Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei:
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width. IEEE J. Solid State Circuits 54(4): 1120-1136 (2019) - [j117]Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han:
Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation. IEEE Trans. Computers 68(11): 1635-1646 (2019) - [j116]Hai Huang, Leibo Liu, Qihuan Huang, Yingjie Chen, Shouyi Yin, Shaojun Wei:
Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 208-219 (2019) - [j115]Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Shaojun Wei:
A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 678-691 (2019) - [j114]Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei:
A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1265-1277 (2019) - [j113]Liang Wang, Ping Lv, Leibo Liu, Jie Han, Ho-fung Leung, Xiaohang Wang, Shouyi Yin, Shaojun Wei, Terrence S. T. Mak:
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1771-1784 (2019) - [j112]Dajiang Liu, Shouyi Yin, Guojie Luo, Jiaxing Shang, Leibo Liu, Shaojun Wei, Yong Feng, Shangbo Zhou:
Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2271-2283 (2019) - [j111]Honglan Jiang, Leibo Liu, Pieter P. Jonker, Duncan G. Elliott, Fabrizio Lombardi, Jie Han:
A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 313-326 (2019) - [j110]Man Shi, Peng Ouyang, Shouyi Yin, Leibo Liu, Shaojun Wei:
A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression. IEEE Trans. Circuits Syst. II Express Briefs 66-II(11): 1870-1874 (2019) - [j109]Shixuan Zheng, Peng Ouyang, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei, Shouyi Yin:
An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4648-4661 (2019) - [j108]Fengbin Tu, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
Reconfigurable Architecture for Neural Approximation in Multimedia Computing. IEEE Trans. Circuits Syst. Video Technol. 29(3): 892-906 (2019) - [j107]Leibo Liu, Qiang Wang, Wenping Zhu, Huiyu Mo, Tianchen Wang, Shouyi Yin, Yiyu Shi, Shaojun Wei:
A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching. IEEE Trans. Circuits Syst. Video Technol. 29(8): 2467-2481 (2019) - [j106]Huiyu Mo, Leibo Liu, Wenping Zhu, Shouyi Yin, Shaojun Wei:
Face Alignment With Expression- and Pose-Based Adaptive Initialization. IEEE Trans. Multim. 21(4): 943-956 (2019) - [j105]Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu, Leibo Liu, Jishen Zhao, Cong Xu, Shuangchen Li, Yuan Xie, Shaojun Wei:
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. IEEE Trans. Parallel Distributed Syst. 30(1): 146-160 (2019) - [j104]Yidong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han:
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2213-2221 (2019) - [c97]Xi Chen, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei:
Small-Footprint Keyword Spotting with Graph Convolutional Network. ASRU 2019: 539-546 - [c96]Huiyu Mo, Leibo Liu, Wenping Zhu, Qiang Li, Hong Liu, Wenjing Hu, Yao Wang, Shaojun Wei:
A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and Alignment. DAC 2019: 80 - [c95]Hong Liu, Leibo Liu, Wenping Zhu, Qiang Li, Huiyu Mo, Shaojun Wei:
L-MPC: A LUT based Multi-Level Prediction-Correction Architecture for Accelerating Binary-Weight Hourglass Network. DAC 2019: 192 - [c94]Xingchen Man, Leibo Liu, Jianfeng Zhu, Shaojun Wei:
A General Pattern-Based Dynamic Compilation Framework for Coarse-Grained Reconfigurable Architectures. DAC 2019: 195 - [c93]Hui Yan, Zhaoshi Li, Leibo Liu, Shouyi Yin, Shaojun Wei:
Constructing Concurrent Data Structures on FPGA with Channels. FPGA 2019: 172-177 - [c92]Honglan Jiang, Francisco J. H. Santiago, Mohammad Saeed Ansari, Leibo Liu, Bruce F. Cockburn, Fabrizio Lombardi, Jie Han:
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints. ACM Great Lakes Symposium on VLSI 2019: 393-398 - [c91]Leibo Liu, Ao Luo, Guanhua Li, Jianfeng Zhu, Yong Wang, Gang Shan, Jianfeng Pan, Shouyi Yin, Shaojun Wei:
Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor. Hot Chips Symposium 2019: 1-25 - [c90]Kai Lu, Zhaoshi Li, Leibo Liu, Jiawei Wang, Shouyi Yin, Shaojun Wei:
ReDESK: A Reconfigurable Dataflow Engine for Sparse Kernels on Heterogeneous Platforms. ICCAD 2019: 1-8 - [c89]Hang Yuan, Wei Guo, Chip-Hong Chang, Yuan Cao, Shaojun Wei, Shouyi Yin, Chenchen Deng, Leibo Liu, Wei Ge, Fan Zhang:
A Reliable Physical Unclonable Function Based on Differential Charging Capacitors. ISCAS 2019: 1-5 - [c88]Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu, Weisheng Zhao:
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. ISVLSI 2019: 111-115 - [c87]Zhaoshi Li, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi Yin, Shaojun Wei:
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. MICRO 2019: 911-923 - [c86]Jianxun Yang, Leibo Liu, Jin Zhang, Shaojun Wei, Shouyi Yin:
An Energy-Efficient Architecture for Accelerating Inference of Memory-Augmented Neural Networks. NANOARCH 2019: 1-6 - [c85]Weiwei Wu, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei:
MoNA: Mobile Neural Architecture with Reconfigurable Parallel Dimensions. NEWCAS 2019: 1-4 - [c84]Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, Peng Ouyang, Win-San Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin:
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. VLSI Circuits 2019: 120- - [p1]Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han:
Approximate Arithmetic Circuits: Design and Evaluation. Approximate Circuits 2019: 67-98 - [i1]Xi Chen, Shouyi Yin, Dandan Song, Peng Ouyang, Leibo Liu, Shaojun Wei:
Small-footprint Keyword Spotting with Graph Convolutional Network. CoRR abs/1912.05124 (2019) - 2018
- [j103]Shouyi Yin, Tianyi Lu, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. IEEE Access 6: 7526-7540 (2018) - [j102]Peican Zhu, Xiaogang Song, Leibo Liu, Zhen Wang, Jie Han:
Stochastic Analysis of Multiplex Boolean Networks for Understanding Epidemic Propagation. IEEE Access 6: 35292-35304 (2018) - [j101]Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Shaojun Wei:
Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution. IEEE Comput. Archit. Lett. 17(2): 147-150 (2018) - [j100]Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei:
FP-BNN: Binarized neural network on FPGA. Neurocomputing 275: 1072-1086 (2018) - [j99]Shouyi Yin, Peng Ouyang, Shibin Tang, Fengbin Tu, Xiudong Li, Shixuan Zheng, Tianyi Lu, Jiangyuan Gu, Leibo Liu, Shaojun Wei:
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications. IEEE J. Solid State Circuits 53(4): 968-982 (2018) - [j98]Shouyi Yin, Zhicong Xie, Chenyue Meng, Peng Ouyang, Leibo Liu, Shaojun Wei:
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 431-444 (2018) - [j97]Leibo Liu, Zhuoquan Zhou, Shaojun Wei, Min Zhu, Shouyi Yin, Shengyang Mao:
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 782-795 (2018) - [j96]Leibo Liu, Chen Yang, Shouyi Yin, Shaojun Wei:
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1171-1184 (2018) - [j95]Jiale Yan, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei:
GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2519-2529 (2018) - [j94]Siting Liu, Honglan Jiang, Leibo Liu, Jie Han:
Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2530-2541 (2018) - [j93]Leibo Liu, Bo Wang, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei:
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3081-3094 (2018) - [j92]Leibo Liu, Zhaoshi Li, Chen Yang, Chenchen Deng, Shouyi Yin, Shaojun Wei:
HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 381-385 (2018) - [j91]Guiqiang Peng, Leibo Liu, Sheng Zhou, Shouyi Yin, Shaojun Wei:
A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1717-1730 (2018) - [j90]Peng Ouyang, Shouyi Yin, Leibo Liu, Youguang Zhang, Weisheng Zhao, Shaojun Wei:
A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3362-3375 (2018) - [j89]Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei:
Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration. IEEE Trans. Parallel Distributed Syst. 29(9): 2105-2120 (2018) - [j88]Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Shouyi Yin, Yiyu Shi, Shaojun Wei:
Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. 29(10): 2360-2372 (2018) - [j87]Guiqiang Peng, Leibo Liu, Sheng Zhou, Yang Xue, Shouyi Yin, Shaojun Wei:
Algorithm and Architecture of a Low-Complexity and High-Parallelism Preprocessing-Based K -Best Detector for Large-Scale MIMO Systems. IEEE Trans. Signal Process. 66(7): 1860-1875 (2018) - [j86]Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei:
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2345-2357 (2018) - [c83]Guiqiang Peng, Leibo Liu, Qiushi Wei, Yao Wang, Shouyi Yin, Shaojun Wei:
A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems. A-SSCC 2018: 191-194 - [c82]Hang Yuan, Leibo Liu, Hui Li, Shouyi Yin, Shaojun Wei:
A Full Multicast Reconfigurable Non-blocking Permutation Network. CyberC 2018 - [c81]Xinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei:
LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA. DAC 2018: 16:1-16:6 - [c80]Shixuan Zheng, Yonggang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei:
An efficient kernel transformation architecture for binary- and ternary-weight neural network inference. DAC 2018: 137:1-137:6 - [c79]Honglan Jiang, Leibo Liu, Fabrizio Lombardi, Jie Han:
Adaptive approximation in arithmetic circuits: A low-power unsigned divider design. DATE 2018: 1411-1416 - [c78]Fengbin Tu, Weiwei Wu, Shouyi Yin, Leibo Liu, Shaojun Wei:
RANA: Towards Efficient Neural Acceleration with Refresh-Optimized Embedded DRAM. ISCA 2018: 340-352 - [c77]Jianxin Guo, Shouyi Yin, Peng Ouyang, Fengbin Tu, Shibin Tang, Leibo Liu, Shaojun Wei:
Bit-width Adaptive Accelerator Design for Convolution Neural Network. ISCAS 2018: 1-5 - [c76]Zhihui Wang, Shouyi Yin, Fengbin Tu, Leibo Liu, Shaojun Wei:
An Energy Efficient JPEG Encoder with Neural Network Based Approximation and Near-Threshold Computing. ISCAS 2018: 1-5 - [c75]Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei:
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS. VLSI Circuits 2018: 37-38 - [c74]Shouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei:
A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS. VLSI Circuits 2018: 139-140 - 2017
- [j85]Weizhi Xu, Shouyi Yin, Zhen Zhang, Hao Dong, Rui Shi, Leibo Liu, Shaojun Wei:
Reconfigurable VLSI Architecture for Real-Time 2D-to-3D Conversion. IEEE Access 5: 26604-26613 (2017) - [j84]Leibo Liu, Yingjie Chen, Chenchen Deng, Shouyi Yin, Shaojun Wei:
Implementation of in-loop filter for HEVC decoder on reconfigurable processor. IET Image Process. 11(9): 685-692 (2017) - [j83]Honglan Jiang, Cong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han:
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits. ACM J. Emerg. Technol. Comput. Syst. 13(4): 60:1-60:34 (2017) - [j82]Shouyi Yin, Peng Ouyang, Xu Dai, Leibo Liu, Shaojun Wei:
An AdaBoost-Based Face Detection System Using Parallel Configurable Architecture With Optimized Computation. IEEE Syst. J. 11(1): 260-271 (2017) - [j81]Chenchen Deng, Leibo Liu, Yang Liu, Shouyi Yin, Shaojun Wei:
PMCC: Fast and Accurate System-Level Power Modeling for Processors on Heterogeneous SoC. IEEE Trans. Circuits Syst. II Express Briefs 64-II(5): 540-544 (2017) - [j80]Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Zhuoquan Zhou, Shaojun Wei:
Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks. IEEE Trans. Inf. Forensics Secur. 12(2): 309-322 (2017) - [j79]Chen Yang, Leibo Liu, Kai Luo, Shouyi Yin, Shaojun Wei:
CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays. IEEE Trans. Parallel Distributed Syst. 28(1): 29-43 (2017) - [j78]Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei:
A Multi-Objective Model Oriented Mapping Approach for NoC-based Computing Systems. IEEE Trans. Parallel Distributed Syst. 28(3): 662-676 (2017) - [j77]Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei:
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. IEEE Trans. Parallel Distributed Syst. 28(9): 2471-2485 (2017) - [j76]Guiqiang Peng, Leibo Liu, Peng Zhang, Shouyi Yin, Shaojun Wei:
Low-Computing-Load, High-Parallelism Detection Method Based on Chebyshev Iteration for Massive MIMO Systems With VLSI Architecture. IEEE Trans. Signal Process. 65(14): 3775-3788 (2017) - [j75]Fengbin Tu, Shouyi Yin, Peng Ouyang, Shibin Tang, Leibo Liu, Shaojun Wei:
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2220-2233 (2017) - [c73]Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei:
Energy-aware loops mapping on multi-vdd CGRAs without performance degradation. ASP-DAC 2017: 312-317 - [c72]Honglan Jiang, Leibo Liu, Jie Han:
An efficient hardware design for cerebellar models using approximate circuits: special session paper. CODES+ISSS 2017: 31:1-31:2 - [c71]Qiang Wang, Leibo Liu, Wenping Zhu, Huiyu Mo, Chenchen Deng, Shaojun Wei:
A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment. DAC 2017: 57:1-57:6 - [c70]Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Zhaoshi Li, Chenchen Deng, Shaojun Wei:
Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution. DAC 2017: 71:1-71:6 - [c69]Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. FCCM 2017: 31 - [c68]Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). FPGA 2017: 290 - [c67]Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei:
Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). FPGA 2017: 295 - [c66]Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei:
A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation. ACM Great Lakes Symposium on VLSI 2017: 287-292 - [c65]Zhaoshi Li, Leibo Liu, Yangdong Deng, Shouyi Yin, Yao Wang, Shaojun Wei:
Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware. ISCA 2017: 575-586 - [c64]Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS 2017: 1-4 - [c63]Shouyi Yin, Dajiang Liu, Lifeng Sun, Leibo Liu, Shaojun Wei:
DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach. ISCAS 2017: 1-4 - [c62]Shibin Tang, Shouyi Yin, Shixuan Zheng, Peng Ouyang, Fengbin Tu, Leiyue Yao, JinZhou Wu, Wenming Cheng, Leibo Liu, Shaojun Wei:
AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs. NVMSA 2017: 1-6 - [c61]Shouyi Yin, Jinjin Duan, Peng Ouyang, Leibo Liu, Shaojun Wei:
Multi-CNN and decision tree based driving behavior evaluation. SAC 2017: 1424-1429 - 2016
- [j74]Shuang Liang, Shouyi Yin, Leibo Liu, Yike Guo, Shaojun Wei:
A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration. IEEE Comput. Archit. Lett. 15(2): 69-72 (2016) - [j73]Bo Wang, Leibo Liu:
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