Google
Google Scholar
Semantic Scholar
MS Academic
CiteSeerX
ORCIDXiaoyang Zeng
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2021
[j84]Jingjing Liu, Ruijie Ma, Xiaoyang Zeng, Wanquan Liu, Mingyu Wang, Hui Chen:
An efficient non-convex total variation approach for image deblurring and denoising. Appl. Math. Comput. 397: 125977 (2021)- [j83]Yuejun Zhang, Jiawei Wang, Pengjun Wang, Xiaoyong Xue, Xiaoyang Zeng:
Orthogonal obfuscation based key management for multiple IP protection. Integr. 77: 139-150 (2021) - [j82]Keji Zhou
, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Ming-e Jing, Jing Li, Xiaoyang Zeng, Ming Liu:
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. IEEE J. Solid State Circuits 56(3): 988-1000 (2021) - [j81]Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. Microelectron. J. 110: 105007 (2021) - 2020
- [j80]Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, C.-J. Richard Shi:
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 283-294 (2020) - [j79]Yibo Fan, Leilei Huang, Kewei Chen, Xiaoyang Zeng:
A Highly Configurable 7.62GOP/s Hardware Implementation for LSTM. IEICE Trans. Electron. 103-C(5): 263-273 (2020) - [j78]Zhiyuan Chen, Man-Kay Law, Pui-In Mak, Xiaoyang Zeng, Rui Paulo Martins:
Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation. IEEE J. Solid State Circuits 55(8): 2106-2117 (2020) - [j77]Guozhu Xin, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng, Xiaoyang Zeng:
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2672-2684 (2020) - [j76]Yan Li, Xu Cheng, Chiyu Tan, Jun Han, Yuanfu Zhao, Liang Wang, Tongde Li, Mehdi B. Tahoori, Xiaoyang Zeng:
A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1619-1623 (2020) - [j75]Qichen Zhang, Yun Chen, Shixian Li, Xiaoyang Zeng, Keshab K. Parhi:
A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis. IEEE Trans. Circuits Syst. 67-I(12): 5429-5442 (2020) - [j74]Yibo Fan, Yixuan Zeng, Heming Sun, Jiro Katto, Xiaoyang Zeng:
A Pipelined 2D Transform Architecture Supporting Mixed Block Sizes for the VVC Standard. IEEE Trans. Circuits Syst. Video Technol. 30(9): 3289-3295 (2020) - [j73]Xiao Yan, Yibo Fan, Kewei Chen, Xulin Yu, Xiaoyang Zeng:
QNet: An Adaptive Quantization Table Generator Based on Convolutional Neural Network. IEEE Trans. Image Process. 29: 9654-9664 (2020) - [j72]Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng:
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1089-1093 (2020) - [j71]Jianwei Yang, Jun Han, Fan Dai, Weizhen Wang, Xiaoyang Zeng:
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1423-1434 (2020) - [c166]Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng:
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. DAC 2020: 1-6 - [c165]Minjiang Li, Mingxu Cui, Jun Chi, Xiaoyang Zeng, Ming-e Jing, Yibo Fan:
A Hardware Friendly Haze Removal Method and Its Implementation. ICCE 2020: 1-5 - [c164]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
A Learning-Based Low Complexity in-Loop Filter for Video Coding. ICME Workshops 2020: 1-6 - [c163]Xu Cheng, Jue Wang, Jun Han, Xiaoyang Zeng:
Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. ISCAS 2020: 1-5 - [c162]Jun Chi, Mingjiang Li, Zihao Meng, Yibo Fan, Xiaoyang Zeng, Ming-e Jing:
Single Image Dehazing using a Novel Histogram Tranformation Network. ISCAS 2020: 1-5 - [c161]Yujie Huang, Ming-e Jing, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng:
Directly Obtaining Matching Points without Keypoints for Image Stitching. ISCAS 2020: 1-5 - [c160]Zhen Li, Zhiyuan Chen, Qiping Wan, Qin Kuai, Junrui Liang, Philip K. T. Mok, Xiaoyang Zeng:
An Energy Harvesting System with Reconfigurable Piezoelectric Energy Harvester Array for IoT Applications. ISCAS 2020: 1-5 - [c159]Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng:
A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. ISCAS 2020: 1-5 - [c158]Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu:
A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques. VLSI Circuits 2020: 1-2 - [i6]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
A Convolutional Neural Network-Based Low Complexity Filter. CoRR abs/2009.02733 (2020) - [i5]Chao Liu, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
A QP-adaptive Mechanism for CNN-based Filter in Video Coding. CoRR abs/2010.13059 (2020)
2010 – 2019
- 2019
- [j70]Jingjing Liu, Donghui He, Xiaoyang Zeng, Mingyu Wang, Xianchao Xiu, Wanquan Liu, Wenhong Li:
ManiDec: Manifold Constrained Low-Rank and Sparse Decomposition. IEEE Access 7: 112939-112952 (2019) - [j69]Yibo Fan, Genwei Tang, Xiaoyang Zeng:
A Compact 32-Pixel TU-Oriented and SRAM-Free Intra Prediction VLSI Architecture for HEVC Decoder. IEEE Access 7: 149097-149104 (2019) - [j68]Yibo Fan, Yize Jin, Zihao Meng, Xiaoyang Zeng:
Pixels and Panoramas: An Enhanced Cubic Mapping Scheme for Video\/Image-Based Virtual-Reality Scenes. IEEE Consumer Electron. Mag. 8(2): 44-49 (2019) - [j67]Li Li, Xu Cheng, Zhang Zhang, Jianmin Zeng, Xiaoyang Zeng:
A 24-bit sigma-delta ADC with configurable chopping scheme. IEICE Electron. Express 16(10): 20190176 (2019) - [j66]Leilei Huang, Yibo Fan, Chenhao Gu, Xiaoyang Zeng:
A Micro-Code-Based IME Engine for HEVC and Its Hardware Implementation. IEICE Trans. Electron. 102-C(10): 756-765 (2019) - [j65]Tianchan Guan, Peiye Liu, Xiaoyang Zeng, Martha A. Kim, Mingoo Seok:
Recursive Binary Neural Network Training Model for Efficient Usage of On-Chip Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2593-2605 (2019) - [j64]Bingyi Zhang, Jun Han, Zhize Huang, Jianwei Yang, Xiaoyang Zeng:
A Real-Time and Hardware-Efficient Processor for Skeleton-Based Action Recognition With Lightweight Convolutional Neural Network. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 2052-2056 (2019) - [j63]Pan Xue, Yilei Shen, Dan Fang, Chenyang Wang, Haijun Shao, Ting Yi, Xiaoyang Zeng, Zhiliang Hong:
A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 47-56 (2019) - [j62]Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 757-768 (2019) - [j61]Liang Wen, Yuejun Zhang, Xiaoyang Zeng:
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1470-1474 (2019) - [c157]Jiawei Wang, Yuejun Zhang, Pengjun Wang, Zhicun Luan, Xiaoyong Xue, Xiaoyang Zeng, Qiaoyan Yu:
An Orthogonal Algorithm for Key Management in Hardware Obfuscation. AsianHOST 2019: 1-4 - [c156]Yujie Cai, Keji Zhou, Xiaoyong Xue, Mingyu Wang, Xiaoyang Zeng:
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. ASICON 2019: 1-4 - [c155]Jinfou Xie, Shixian Li, Yun Chen, Qichen Zhang, Xiaoyang Zeng:
High throughput multi-code LDPC encoder for CCSDS standard. ASICON 2019: 1-4 - [c154]Yi Zhang, Xiaoshan He, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Enhanced Recursive Residual Network for Single Image Super-Resolution. ASICON 2019: 1-4 - [c153]Riyong Zheng, Chenghao Wang, Jun Han, Xiaoyang Zeng:
A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. ASICON 2019: 1-3 - [c152]Xiaoyong Xue, Jianguo Yang, Yuejun Zhang, Mingyu Wang, Hangbing Lv, Xiaoyang Zeng, Ming Liu:
A 28nm 512Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for extremely low bit error rate of cryptographic key. A-SSCC 2019: 29-32 - [c151]Qichen Zhang, Yun Chen, Xiaoyang Zeng, Keshab K. Parhi, Borivoje Nikolic:
A 3.01 mm2 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm. A-SSCC 2019: 271-274 - [c150]Jun Yin, Jun Han, Chenghao Wang, Bingyi Zhang, Xiaoyang Zeng:
A Skeleton-based Action Recognition System for Medical Condition Detection. BioCAS 2019: 1-4 - [c149]Huan Tang, Yujie Huang, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Very Deep Residual Network for Image Matting. ICIP 2019: 4255-4259 - [c148]Jingjing Liu, Donghui He, Xiaoyang Zeng, Mingyu Wang, Xianchao Xiu, Wanquan Liu, Hui Chen, Yuyao Xiao:
Bayesian Face Recognition Approach Based on Feature Fusion. ICNC-FSKD 2019: 37-45 - [c147]Ping Zhao, Junyi Wang, Xihan Gu, Kangzhou Suo, Yun Chen, Xiaoyang Zeng:
Acoustic Frequency Division Based on Active Metamaterial: An Experimental Demonstration of Acoustic Frequency Halving. IoTaaS 2019: 61-70 - [c146]Genwei Tang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan:
A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture. ISCAS 2019: 1-5 - [c145]Zhiyuan Chen, Yang Jiang, Man-Kay Law, Pui-In Mak, Xiaoyang Zeng, Rui Paulo Martins:
A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement. ISSCC 2019: 424-426 - [c144]Chao Liu, Heming Sun, Junan Chen, Zhengxue Cheng, Masaru Takeuchi, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Dual Learning-based Video Coding with Inception Dense Blocks. PCS 2019: 1-5 - [c143]Yibo Fan, Jiro Katto, Heming Sun, Xiaoyang Zeng, Yixuan Zeng:
A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard. SoCC 2019: 176-180 - [c142]Junan Chen, Heming Sun, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Fast QTMT Partition Decision Algorithm in VVC Intra Coding based on Variance and Gradient. VCIP 2019: 1-4 - [c141]Genwei Tang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan:
Adaptive CU Split Decision with Pooling-variable CNN for VVC Intra Encoding. VCIP 2019: 1-4 - [c140]Chenhao Gu, Leilei Huang, Xiaoyang Zeng, Yibo Fan:
A Micro-Code-Based Hardware Architecture of Integer Motion Estimation for HEVC. VLSI-SoC 2019: 269-274 - [i4]Chao Liu, Heming Sun, Junan Chen, Zhengxue Cheng, Masaru Takeuchi, Jiro Katto, Xiaoyang Zeng, Yibo Fan:
Dual Learning-based Video Coding with Inception Dense Blocks. CoRR abs/1911.09857 (2019) - 2018
- [j60]Longmei Nan, Xiaoyang Zeng, Wei Li, Zhouchuang Wang, Zibin Dai:
A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications. IEICE Electron. Express 15(5) (2018) - [j59]Jianwei Yang, Fan Dai, Jielin Wang, Jianmin Zeng, Zhang Zhang, Jun Han, Xiaoyang Zeng:
Countering power analysis attacks by exploiting characteristics of multicore processors. IEICE Electron. Express 15(7): 20180084 (2018) - [j58]Chubin Wu, Guangjun Xie, Zhang Zhang, Xin Cheng, Tairan Fei, Jianmin Zeng, Xiaoyang Zeng:
A 15 W wireless power receiver with an improved full-wave synchronous rectifier. IEICE Electron. Express 15(20): 20180732 (2018) - [j57]Yibo Fan, Leilei Huang, Bei Hao, Xiaoyang Zeng:
A Hardware-Oriented IME Algorithm for HEVC and Its Hardware Implementation. IEEE Trans. Circuits Syst. Video Technol. 28(8): 2048-2057 (2018) - [c139]Keji Zhou, Xiaoyong Xue, Jianguo Yang, Xiaoxin Xu, Hangbing Lv, Mingyu Wang, Ming-e Jing, Wenjun Liu, Xiaoyang Zeng, Steve S. Chung, Jing Li, Ming Liu:
Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. A-SSCC 2018: 135-138 - [c138]Yujie Huang, Quan Zhang, Yujie Cai, Ming-e Jing, Yibo Fan, Xiaoyang Zeng:
Dynamic Task Scheduler for Real Time Requirement in Cloud Computing System. ICA3PP (4) 2018: 3-11 - [c137]Zhengzhong Tu, Tongyu Zong, Xueliang Xi, Li Ai, Yize Jin, Xiaoyang Zeng, Yibo Fan:
Content adaptive tiling method based on user access preference for streaming panoramic video. ICCE 2018: 1-4 - [c136]Tongyu Zong, Zhengzhong Tu, Li Ai, Xueliang Xi, Yize Jin, Xiaoyang Zeng, Yibo Fan:
Panoramic video delivery based on Laplace compensation and Sphere-Markov probability model. ICCE 2018: 1-4 - [c135]Shixian Li, Qichen Zhang, Yun Chen, Xiaoyang Zeng:
A High-Throughput QC-LDPC Decoder for Near-Earth Application. DSL 2018: 1-4 - [c134]Bingyi Zhang, Xin Li, Jun Han, Xiaoyang Zeng:
MiniTracker: A Lightweight CNN-based System for Visual Object Tracking on Embedded Device. DSL 2018: 1-5 - [c133]Kewei Chen, Leilei Huang, Minjiang Li, Xiaoyang Zeng, Yibo Fan:
A Compact and Configurable Long Short-Term Memory Neural Network Hardware Architecture. ICIP 2018: 4168-4172 - [c132]Ming-e Jing, Yujie Huang, Yibo Fan, Xiaoyong Xue, Xiaoyang Zeng, Zhiyi Yu:
An Automatic Task Partition Method for Multi-core System. ISCAS 2018: 1-5 - [c131]Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng:
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization. ISOCC 2018: 123-124 - [c130]Sheng Guan, Weicheng He, Wenjin Gu, Yuanzhao Hou, Yun Chen, Xiaoyang Zeng:
Multi-mode Study of Deep Learning Applications in Acoustic Signal Processing. SiPS 2018: 292-295 - 2017
- [j56]Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu:
A multi-core-based heterogeneous parallel turbo decoder. IEICE Electron. Express 14(18): 20170768 (2017) - [j55]Yibo Fan, Leilei Huang, Zheng Xie, Xiaoyang Zeng:
A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding. IEICE Trans. Electron. 100-C(6): 643-654 (2017) - [j54]Liang Wen, Haibo Wen, Xiaoyang Zeng:
Sub-threshold level converter with internal supply feedback for multi-voltage applications. IET Circuits Devices Syst. 11(2): 149-156 (2017) - [c129]Ziqiang Li, Liyu Lin, Yun Chen, Xiaoyang Zeng:
Implementation of a pipeline division-free MMSE MIMO detector that support soft-input and soft-output. APCC 2017: 1-5 - [c128]Longmei Nan, Xiaoyang Zeng, Zhouchuang Wang, Yiran Du, Wei Li:
Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure. ASICON 2017: 191-194 - [c127]Ying Zhang, Yujie Huang, Jun Han, Xiaoyang Zeng:
FPGA-based efficient implementation of SURF algorithm. ASICON 2017: 315-318 - [c126]Yujie Cai, Xin Li, Jun Han, Xiaoyang Zeng:
A configurable nonlinear operation unit for neural network accelerator. ASICON 2017: 319-322 - [c125]Yalong Pang, Ying Zhang, Jun Han, Xiaoyang Zeng:
Fp2 arithmetic acceleration based on modified Barrett modular multiplication algorithm. ASICON 2017: 561-564 - [c124]Xin Li, Yujie Cai, Jun Han, Xiaoyang Zeng:
A high utilization FPGA-based accelerator for variable-scale convolutional neural network. ASICON 2017: 944-947 - [c123]Jianwei Yang, Weizhen Wang, Zhicheng Xie, Jun Han, Zhiyi Yu, Xiaoyang Zeng:
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. ASICON 2017: 953-956 - [c122]Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Extending memory capacity of neural associative memory based on recursive synaptic bit reuse. DATE 2017: 1603-1606 - [c121]Yize Jin, Liming Wang, Qinwei Jiang, Xiaoyang Zeng, Yibo Fan:
An efficient spherical video sampling scheme based on Cube model. ICCE 2017: 211-214 - [c120]Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng:
Instruction set extension and hardware acceleration for SVM application toward a vector processor. ISOCC 2017: 42-43 - [i3]Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Recursive Binary Neural Network Learning Model with 2.28b/Weight Storage Requirement. CoRR abs/1709.05306 (2017) - 2016
- [j53]Xu Cheng, Xiaoyang Zeng, Qi Feng:
Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. Microelectron. J. 58: 23-31 (2016) - [j52]Liang Wen, Xu Cheng, Shudong Tian, Haibo Wen, Xiaoyang Zeng:
Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. IEEE Trans. Circuits Syst. II Express Briefs 63-II(4): 346-350 (2016) - [j51]Liang Wen, Xu Cheng, Keji Zhou, Shudong Tian, Xiaoyang Zeng:
Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 643-647 (2016) - [j50]Di Wu, Yun Chen, Qichen Zhang, Yeong-Luh Ueng, Xiaoyang Zeng:
Strategies for Reducing Decoding Cycles in Stochastic LDPC Decoders. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 873-877 (2016) - [j49]Jun Han, Yicheng Zhang, Shan Huang, Mengyuan Chen, Xiaoyang Zeng:
An Area-Efficient Error-Resilient Ultralow-Power Subthreshold ECG Processor. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 984-988 (2016) - [j48]Weiwei Shen, Yibo Fan, Yufeng Bai, Leilei Huang, Qing Shang, Cong Liu, Xiaoyang Zeng:
A Combined Deblocking Filter and SAO Hardware Architecture for HEVC. IEEE Trans. Multim. 18(6): 1022-1033 (2016) - [c119]Shan Huang, Jun Han, Xin Li, Zongxian Yang, Xiaoyang Zeng:
A low-cost and energy-efficient EEG processor for continuous seizure detection using wavelet transform and AdaBoost. BioCAS 2016: 344-347 - [c118]Qichen Zhang, Yun Chen, Di Wu, Xiaoyang Zeng, Yeong-Luh Ueng:
Convergence-optimized variable node structure for stochastic LDPC decoder. ICASSP 2016: 6535-6539 - [c117]Qinwei Jiang, Leilei Huang, Yibo Fan, Xiaoyang Zeng:
Quarter LCU based integer motion estimation algorithm for HEVC. ICIP 2016: 2018-2021 - [c116]Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng:
Cryptographie coprocessor design for IoT sensor nodes. ISOCC 2016: 37-38 - [c115]Tianchan Guan, Xiaoyang Zeng, Letian Huang, Tianchan Guan, Mingoo Seok:
Neural network based seizure detection system using raw EEG data. ISOCC 2016: 211-212 - 2015
- [j47]Yawei Guo, Yue Wu, Dongdong Guo, Xu Cheng, Zhiyi Yu, Xiaoyang Zeng:
Non-binary digital calibration for split-capacitor DAC in SAR ADC. IEICE Electron. Express 12(4): 20150001 (2015) - [j46]Weina Zhou, Huafeng Wu, Xiaoyang Zeng:
A low cost architecture for high performance face detection. Microprocess. Microsystems 39(6): 339-347 (2015) - [j45]Gaowei Xu, Jun Han, Yao Zou, Xiaoyang Zeng:
A 1.5-D Multi-Channel EEG Compression Algorithm Based on NLSPIHT. IEEE Signal Process. Lett. 22(8): 1118-1122 (2015) - [j44]Yao Zou, Jun Han, Sizhong Xuan, Shan Huang, Xinqian Weng, Dabin Fang, Xiaoyang Zeng:
An Energy-Efficient Design for ECG Recording and R-Peak Detection Based on Wavelet Transform. IEEE Trans. Circuits Syst. II Express Briefs 62-II(2): 119-123 (2015) - [j43]Jun Han, Renfeng Dou, Lingyun Zeng, Shuai Wang, Zhiyi Yu, Xiaoyang Zeng:
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1372-1381 (2015) - [j42]Yibo Fan, Leilei Huang, Yufeng Bai, Xiaoyang Zeng:
A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs. IEEE Trans. Circuits Syst. II Express Briefs 62-II(12): 1139-1143 (2015) - [j41]Yibo Fan, Qing Shang, Xiaoyang Zeng:
In-Block Prediction-Based Mixed Lossy and Lossless Reference Frame Recompression for Next-Generation Video Encoding. IEEE Trans. Circuits Syst. Video Technol. 25(1): 112-124 (2015) - [j40]Jun Han, Yang Li, Zhiyi Yu, Xiaoyang Zeng:
A 65 nm Cryptographic Processor for High Speed Pairing Computation. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 692-701 (2015) - [j39]Xiaoyang Zeng, Yi Li, Yuejun Zhang, Shujie Tan, Jun Han, Xingxing Zhang, Zhang Zhang, Xu Cheng, Zhiyi Yu:
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1365-1369 (2015) - [c114]Tianchan Guan, Jun Han, Xiaoyang Zeng:
Exploration for energy-efficient ECC decoder of WBAN. ASICON 2015: 1-4 - [c113]Leilei Huang, Wei Cheng, Xiaoyang Zeng, Yibo Fan:
A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders. ASICON 2015: 1-4 - [c112]Ziqiang Li, Yun Chen, Xiaoyang Zeng:
OFDM synchronization implementation based on Chisel platform for 5G research. ASICON 2015: 1-4 - [c111]YanHeng Lu, Wei Cheng, Leilei Huang, Xiaoyang Zeng, Yibo Fan:
A flexible HEVC intra mode decision hardware for 8kx4k real time encoder. ASICON 2015: 1-4 - [c110]Yi Ren, Jun Han, Zhiyi Yu, Sizhong Xuan, Xiaoyang Zeng:
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. ASICON 2015: 1-4 - [c109]Shudong Tian, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
Motion artifact removal based on ICA for ambulatory ECG monitoring. ASICON 2015: 1-4 - [c108]Weizhen Wang, Jun Han, Jielin Wang, Xiaoyang Zeng:
A SIMD multiplier-accumulator design for pairing cryptography. ASICON 2015: 1-4 - [c107]Jielin Wang, Weizhen Wang, Jianwei Yang, Zhiyi Yu, Jun Han, Xiaoyang Zeng:
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. ASICON 2015: 1-4 - [c106]Liang Wen, Li Li, Haibo Wen, Xiaoyang Zeng:
Energy-efficient sub-threshold level shifter. ASICON 2015: 1-4 - [c105]Zhicheng Xie, Jun Han, Jianwei Yang, Lijun Zhou, Xiaoyang Zeng:
A low-cost SoC implementation of AES algorithm for bio-signals. ASICON 2015: 1-4 - [c104]Sizhong Xuan, Jun Han, Zhiyi Yu, Yi Ren, Xiaoyang Zeng:
A configurable SoC design for information security. ASICON 2015: 1-4 - [c103]Zhi Hu, Yibo Fan, Xiaoyang Zeng:
Iterative disparity voting based stereo matching algorithm and its hardware implementation. ASP-DAC 2015: 196-201 - [c102]Qichen Zhang, Yun Chen, Di Wu, Xiaoyang Zeng, Yeong-Luh Ueng:
An area-efficient architecture for stochastic LDPC decoder. DSP 2015: 244-247 - [c101]Wei Cheng, Yibo Fan, YanHeng Lu, Yize Jin, Xiaoyang Zeng:
A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application. ISCAS 2015: 605-608 - [c100]Di Wu, Yun Chen, Qichen Zhang, Li-Rong Zheng, Xiaoyang Zeng, Yeong-Luh Ueng:
Latency-optimized stochastic LDPC decoder for high-throughput applications. ISCAS 2015: 3044-3047 - [c99]