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ORCIDSungho Kang 0001
Person information
- affiliation: Yonsei University, Department of Electrical and Electronic Engineering, Computer Systems Reliable SoC Laboratory, Seoul, Korea
- affiliation: Motorola Inc., Austin, Semiconductor Systems Design Technology, TX, USA
- affiliation: Schlumberger Inc., Schlumberger Laboratory for Computer Science, Austin, TX, USA
- affiliation (PhD): University of Texas at Austin, TX, USA
Other persons with the same name
- Sungho Kang — disambiguation page
- Sungho Kang 0002
![[0009-0008-5829-4503]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0009-0008-5829-4503")
— Sungkyunkwan University, Department of Electrical and Computer Engineering, Seoul, South Korea
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2020 – today
- 2024
[j109]Hayoung Lee, Sooryeong Lee, Sungho Kang:
A New Fail Address Memory Architecture for Cost-Effective ATE. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1260-1273 (2024)- [j108]Hyeonchan Lim, Tae-Hyun Kim, Sungho Kang:
Reconfigurable Multi-Bit Scan Flip-Flop for Cell-Aware Diagnosis. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2024-2028 (2024) - [j107]Sangjun Lee, Jongho Park, Sungwhan Park, Hyemin Kim, Sungho Kang:
A New Zero-Overhead Test Method for Low-Power AI Accelerators. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2649-2653 (2024) - [j106]Hayoung Lee, Sooryeong Lee, Sungho Kang:
RA-Aware Fail Data Collection Architecture for Cost Reduction. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1136-1149 (2024) - 2023
- [j105]Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang:
Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 308-321 (2023) - [j104]Hayoung Lee, Seung Ho Shin, Younwoo Yoo, Sungho Kang:
TRUST: Through-Silicon via Repair Using Switch Matrix Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2377-2390 (2023) - [j103]Sunghoon Kim, Seokjun Jang, Sungho Kang:
Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(8): 2717-2727 (2023) - [j102]Hayoung Lee, Jihye Kim, Jongho Park, Sungho Kang:
STRAIT: Self-Test and Self-Recovery for AI Accelerator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3092-3104 (2023) - [j101]Yong Lee, Seokjun Jang, Sungho Kang:
Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a Chip. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1580-1584 (2023) - [j100]Youngkwang Lee, Donghyun Han, Sungho Kang:
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 578-590 (2023) - [c84]Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang:
GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair. ISOCC 2023: 1-2 - [c83]Sunghoon Kim, Donghyun Han, Seokjun Jang, Sungho Kang:
LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture. ISOCC 2023: 289-290 - [c82]Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
Redundancy Analysis Simplification Scheme for High-Speed Memory Repair. ISOCC 2023: 339-340 - [c81]Hyojoon Yun, Tae-Hyun Kim, Sungho Kang:
Machine Learning based Scan Chain Diagnosis for Double Faults. ISOCC 2023: 341-342 - [c80]Hyemin Kim, Sangjun Lee, Jongho Park, Sungwhan Park, Sungho Kang:
A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design. ISOCC 2023: 343-344 - 2022
- [j99]Youngkwang Lee, Young-Woo Lee, Sungyoul Seo, Sungho Kang:
Reduced-Pin-Count BOST for Test-Cost Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(3): 750-761 (2022) - [j98]Sangmin Park, Minho Cheong, Donghyun Han, Sungho Kang:
Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1142-1153 (2022) - [j97]Hogyeong Kim, Hayoung Lee, Donghyun Han, Sungho Kang:
Multibank Optimized Redundancy Analysis Using Efficient Fault Collection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2739-2752 (2022) - [j96]Gyungbin Kim, Minho Cheong, Sungho Kang:
SPAR: A New Test-Point Insertion Using Shared Points for Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4939-4951 (2022) - [j95]Hyeonchan Lim, Hyojoon Yun, Sungho Kang:
A Hybrid Test Scheme for Automotive IC in Multisite Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5671-5680 (2022) - [j94]Hyeonchan Lim, Hyojoon Yun, Sungho Kang:
Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4498-4502 (2022) - [j93]Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM. IEEE Trans. Very Large Scale Integr. Syst. 30(6): 781-793 (2022) - [c79]Seung Ho Shin, Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Sungho Kang:
An Improved Early Termination Methodology Using Convolutional Neural Network. ISOCC 2022: 21-22 - [c78]Sooryeong Lee, Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
PROG: Per-Row Output Generator for BOST. ISOCC 2022: 23-24 - [c77]Sunghoon Kim, Seokjun Jang, Youngki Moon, Sungho Kang:
Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis. ISOCC 2022: 25-26 - [c76]Hayoung Lee, Sooryeong Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
FAME: Fault Address Memory Structure for Repair Time Reduction. ISOCC 2022: 31-32 - [c75]Jongho Park, Sangjun Lee, Inhwan Lee, Sungwhan Park, Sungho Kang:
Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST. ISOCC 2022: 53-54 - [c74]Hyeonchan Lim, Hyojoon Yun, Juyong Lee, Sungho Kang:
Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset. ISOCC 2022: 121-122 - [c73]Jihye Kim, Hayoung Lee, Jongho Park, Sungho Kang:
ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator. ISOCC 2022: 360-361 - [c72]Tae Hyun Kim, Hyeonchan Lim, Minho Cheong, Hyojoon Yun, Sungho Kang:
Logic Diagnosis Based on Deep Learning for Multiple Faults. ISOCC 2022: 366-367 - 2021
- [j92]Jaewon Park, Jae Hoon Lee, Sang-Kil Park, Ki Chul Chun, Kyomin Sohn, Sungho Kang:
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process. IEEE Access 9: 33487-33497 (2021) - [j91]Hayoung Lee, Hyunggoy Oh, Sungho Kang:
On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug. IEEE Access 9: 56443-56456 (2021) - [j90]Donghyun Han, Hayoung Lee, Sungho Kang:
Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory. IEEE Access 9: 76716-76729 (2021) - [j89]Hyungil Woo, Seokjun Jang, Sungho Kang:
A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key. IEEE Access 9: 102161-102176 (2021) - [j88]Kwonhyoung Lee, Sangjun Lee, Jongho Park, Inhwan Lee, Sungho Kang:
A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs. IEEE Access 9: 116115-116132 (2021) - [j87]Seokjun Jang, Jihye Kim, Sungho Kang:
Reconfigurable Scan Architecture for High Diagnostic Resolution. IEEE Access 9: 120537-120550 (2021) - [j86]Donghyun Han, Hayoung Lee, Seungtaek Lee, Sungho Kang:
ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory. IEEE Access 9: 133274-133288 (2021) - [j85]Sangjun Lee, Kyunghwan Cho, Jihye Kim, Jongho Park, Inhwan Lee, Sungho Kang:
Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks. Sensors 21(18): 6111 (2021) - [j84]Jungil Mok, Hyeonchan Lim, Sungho Kang:
Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1164-1177 (2021) - [c71]Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang:
A Circular-based TSV Repair Architecture. ISOCC 2021: 1-2 - [c70]Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang:
Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC. ISOCC 2021: 101-102 - [c69]Sangjun Lee, Jongho Park, Inhwan Lee, Kwonhyoung Lee, Sungho Kang:
Hybrid Test Access Mechanism for Multiple Identical Cores. ISOCC 2021: 365-366 - [c68]Seokjun Jang, Hyungil Woo, Sunghoon Kim, Sungho Kang:
Secure Scan Design through Pseudo Fault Injection. ISOCC 2021: 425-426 - [c67]Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang:
Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory. ISOCC 2021: 427-428 - [c66]Seung Ho Shin, Hayoung Lee, Younwoo Yoo, Sungho Kang:
An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA. ISOCC 2021: 429-430 - [c65]Youngki Moon, Hyunho Yoo, Donghyun Han, Sungho Kang:
Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. ISOCC 2021: 431-432 - 2020
- [j83]Jihye Kim, Hayoung Lee, Seokjun Jang, Sungho Kang:
Fine-Grained Defect Diagnosis for CMOL FPGA Circuits. IEEE Access 8: 163140-163151 (2020) - [j82]Hyunyul Lim, Minho Cheong, Sungho Kang:
Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks. Sensors 20(17): 4771 (2020) - [j81]Minho Cheong, Ingeol Lee, Sungho Kang:
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1925-1934 (2020) - [j80]Young-Woo Lee, Hyeonchan Lim, Youngkwang Lee, Sungho Kang:
Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3023-3034 (2020) - [j79]Sangjun Lee, Kyunghwan Cho, Sungki Choi, Sungho Kang:
A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction. IEEE Trans. Circuits Syst. 67-II(12): 3432-3436 (2020) - [j78]Tae Hyun Kim, Hayoung Lee, Sungho Kang:
GPU-Based Redundancy Analysis Using Concurrent Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 805-817 (2020) - [c64]Hayoung Lee, Donghyun Han, Hogyeong Kim, Sungho Kang:
Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair. ISOCC 2020: 51-52 - [c63]Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang:
Diagnosis of Scan Chain Faults Based-on Machine-Learning. ISOCC 2020: 57-58 - [c62]Jihye Kim, Hayoung Lee, Seokjun Jang, Hogyeong Kim, Sungho Kang:
Memory-like Defect Diagnosis for CMOL FPGAs. ISOCC 2020: 139-140 - [c61]Hayoung Lee, Keewon Cho, Sungho Kang, Wooheon Kang, Seungtaek Lee, Woosik Jeong:
Fail Memory Configuration Set for RA Estimation. ITC 2020: 1-9 - [c60]Hayoung Lee, Donghyun Han, Hogyeong Kim, Sungho Kang:
W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction. ITC-Asia 2020: 94-99
2010 – 2019
- 2019
- [j77]Jaewon Jang, Minho Cheong, Sungho Kang:
TSV Repair Architecture for Clustered Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 190-194 (2019) - [j76]Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang:
An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(3): 551-561 (2019) - [j75]Ingeol Lee, Minho Cheong, Sungho Kang:
Highly Reliable Redundant TSV Architecture for Clustered Faults. IEEE Trans. Reliab. 68(1): 237-247 (2019) - [j74]Jihye Kim, Sangjun Lee, Sungho Kang:
Test-Friendly Data-Selectable Self-Gating (DSSG). IEEE Trans. Very Large Scale Integr. Syst. 27(8): 1972-1976 (2019) - [j73]Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang:
Dynamic Built-In Redundancy Analysis for Memory Repair. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2365-2374 (2019) - [c59]Minho Cheng, Hyunyul Lim, Tae Hyun Kim, Sungho Kang:
A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology. ISOCC 2019: 63-64 - [c58]Jihye Kim, Sangjun Lee, Minho Moon, Sungho Kang:
Transition-delay Test Methodology for Designs with Self-gating. ISOCC 2019: 93-94 - [c57]Young-Woo Lee, Youngkwang Lee, Minho Moon, Sungho Kang:
Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks. ISOCC 2019: 115-116 - [c56]Kyunghwan Cho, Jihye Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang:
A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density. ISOCC 2019: 134-135 - [c55]Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang:
Redundancy Analysis based on Fault Distribution for Memory with Complex Spares. ISOCC 2019: 235-236 - 2018
- [j72]Sungyoul Seo, Keewon Cho, Young-Woo Lee, Sungho Kang:
A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 391-403 (2018) - [j71]Inhyuk Choi, Hyunggoy Oh, Young-Woo Lee, Sungho Kang:
Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost. IEEE Trans. Computers 67(12): 1835-1839 (2018) - [j70]Jaeil Lim, Hyunggoy Oh, Heetae Kim, Sungho Kang:
Thermal Aware Test Scheduling for NTV Circuit. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 906-910 (2018) - [j69]Hayoung Lee, Kiwon Cho, Donghyun Kim, Sungho Kang:
Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1473-1482 (2018) - [j68]Hayoung Lee, Jooyoung Kim, Keewon Cho, Sungho Kang:
Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation. IEEE Trans. Reliab. 67(1): 264-273 (2018) - [j67]Donghyun Kim, Hayoung Lee, Sungho Kang:
An Area-Efficient BIRA With 1-D Spare Segments. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 206-210 (2018) - [c54]Hyunggoy Oh, Heetae Kim, Sangjun Lee, Sungho Kang:
Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. ISOCC 2018: 7-8 - [c53]Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang:
2-D Failure Bitmap Compression Using Line Fault Marking Method. ISOCC 2018: 21-22 - [c52]Hyeonchan Lim, Seokjun Jang, Sungho Kang:
A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain. ISOCC 2018: 265-266 - [c51]Heetae Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang:
Low Power Scan Chain Architecture Based on Circuit Topology. ISOCC 2018: 267-268 - [c50]Donghyun Han, Hayoung Lee, Seungtaek Lee, Minho Moon, Sungho Kang:
3D Memory Formed of Unrepairable Memory Dice and Spare Layer. TENCON 2018: 1362-1366 - [c49]Dongsu Lee, Hyunyul Lim, Tae Hyun Kim, Sungho Kang:
Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU. TENCON 2018: 2281-2286 - 2017
- [j66]Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang:
Reconfigurable scan architecture for test power and data volume reduction. IEICE Electron. Express 14(13): 20170415 (2017) - [j65]Heetae Kim, Hyunggoy Oh, Jaeil Lim, Sungho Kang:
A novel X-filling method for capture power reduction. IEICE Electron. Express 14(23): 20171093 (2017) - [j64]Younsun Kim, Hyunggoy Oh, Sungho Kang:
Proof of Concept of Home IoT Connected Vehicles. Sensors 17(6): 1289 (2017) - [j63]Hyunggoy Oh, Taewoo Han, Inhyuk Choi, Sungho Kang:
An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time. IEEE Trans. Computers 66(1): 38-44 (2017) - [j62]Hyunggoy Oh, Inhyuk Choi, Sungho Kang:
DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores. IEEE Trans. Computers 66(9): 1504-1517 (2017) - [j61]Jaeseok Park, Hyunyul Lim, Sungho Kang:
FRESH: A New Test Result Extraction Scheme for Fast TSV Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 336-345 (2017) - [j60]Young-Woo Lee, Hyeonchan Lim, Sungho Kang:
Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(10): 1759-1763 (2017) - [j59]Jaeseok Park, Minho Cheong, Sungho Kang:
R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies. IEEE Trans. Reliab. 66(2): 458-466 (2017) - [j58]Jooyoung Kim, Woosung Lee, Keewon Cho, Sungho Kang:
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 844-856 (2017) - [j57]Jaewon Jang, Minho Cheong, Jin-Ho Ahn, Sung Kyu Lim, Sungho Kang:
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1178-1182 (2017) - [c48]Donghyun Han, Hayoung Lee, Donghyun Kim, Sungho Kang:
A new repair scheme for TSV-based 3D memory using base die repair cells. ISOCC 2017: 11-12 - [c47]Hyunyul Lim, Tae Hyun Kim, Dongsu Lee, Sungho Kang:
LARECD: Low area overhead and reliable error correction DMR architecture. ISOCC 2017: 27-28 - [c46]Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang:
An efficient built-in self-repair scheme for area reduction. ISOCC 2017: 105-106 - [c45]Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang:
A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. ISOCC 2017: 121-122 - [c44]Hyeonchan Lim, Junghwan Kim, Soyeon Kang, Sungho Kang:
Test data reduction method based on berlekamp-massey algorithm. ISOCC 2017: 123-124 - [c43]Sungyoul Seo, Hyeonchan Lim, Soyeon Kang, Sungho Kang:
Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. ISQED 2017: 191-195 - [c42]Hyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang:
Broadcast scan compression based on deterministic pattern generation algorithm. ISQED 2017: 449-453 - 2016
- [j56]Keewon Cho, Wooheon Kang, Hyungjun Cho, Changwook Lee, Sungho Kang:
A Survey of Repair Analysis Algorithms for Memories. ACM Comput. Surv. 49(3): 47:1-47:41 (2016) - [j55]Sungyoul Seo, Yong Lee, Sungho Kang:
Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 274-284 (2016) - [j54]Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang:
Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1219-1223 (2016) - [j53]Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang:
A New 3-D Fuse Architecture to Improve Yield of 3-D Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1763-1767 (2016) - [j52]Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang:
Optimized Built-In Self-Repair for Multiple Memories. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2174-2183 (2016) - [c41]Hyunggoy Oh, Inhyuk Choi, Sungho Kang:
A new online test and debug methodology for automotive camera image processing system. APCCAS 2016: 370-371 - [c40]Inhyuk Choi, Hyunggoy Oh, Sungho Kang:
Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. APCCAS 2016: 522-525 - [c39]Soyeon Kang, Inhyuk Choi, Hyeonchan Lim, Sungyoul Seo, Sungho Kang:
Software-based embedded core test using multi-polynomial for test data reduction. ISOCC 2016: 39-40 - [c38]Keewon Cho, Jooyoung Kim, Hayoung Lee, Sungho Kang:
Discussion of cost-effective redundancy architectures. ISOCC 2016: 97-98 - [c37]Tae Hyun Kim, Hyunyul Lim, Sungho Kang:
P-backtracking: A new scan chain diagnosis method with probability. ISOCC 2016: 141-142 - [c36]Heetae Kim, Inhyuk Choi, Jaeil Lim, Hyunggoy Oh, Sungho Kang:
Process variation-aware bridge fault analysis. ISOCC 2016: 147-148 - 2015
- [j51]Hyejeong Hong, Jaeil Lim, Hyunyul Lim, Sungho Kang:
Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability. ACM Comput. Surv. 48(1): 9:1-9:25 (2015) - [j50]HyeonUk Son, Jaewon Jang, Heetae Kim, Sungho Kang:
Reduced-code test method using sub-histograms for pipelined ADCs. IEICE Electron. Express 12(12): 20150417 (2015) - [j49]Jaeil Lim, Hyunyul Lim, Sungho Kang:
3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1455-1466 (2015) - [j48]Haksong Kim, Yong Lee, Sungho Kang:
A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability. IEEE Trans. Reliab. 64(1): 486-496 (2015) - [j47]Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang:
A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories. IEEE Trans. Reliab. 64(2): 586-595 (2015) - [j46]Taewoo Han, Inhyuk Choi, Sungho Kang:
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1439-1447 (2015) - [c35]Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang:
Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction. ATS 2015: 1-6 - [c34]Sungyoul Seo, Yong Lee, Joohwan Lee, Sungho Kang:
A scan shifting method based on clock gating of multiple groups for low power scan testing. ISQED 2015: 162-166 - [c33]Hyunyul Lim, Wooheon Kang, Sungyoul Seo, Yong Lee, Sungho Kang:
Low power scan bypass technique with test data reduction. ISQED 2015: 173-176 - [c32]Woosung Lee, Keewon Cho, Jooyoung Kim, Sungho Kang:
Near optimal repair rate built-in redundancy analysis with very small hardware overhead. ISQED 2015: 435-439 - 2014
- [j45]Hyejeong Hong, Jaeil Lim, Sungho Kang:
Recovery-enhancing task scheduling for multicore processors under NBTI impact. IEICE Electron. Express 11(11): 20140324 (2014) - [j44]Changwook Lee, Wooheon Kang, Donkoo Cho, Sungho Kang:
A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(5): 786-797 (2014) - [j43]Wooheon Kang, Hyungjun Cho, Joohwan Lee, Sungho Kang:
A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2336-2349 (2014) - [j42]Hyungsu Sung, Keewon Cho, Kunsang Yoon, Sungho Kang:
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2380-2387 (2014) - [c31]Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang:
A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System. ATS 2014: 81-86 - 2013
- [j41]Hyejeong Hong, Jaeil Lim, Hyunyul Lim, Sungho Kang:
Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations. IEICE Electron. Express 10(14): 20130463 (2013) - [j40]Hyejeong Hong, Jaeil Lim, Hyunyul Lim, Sungho Kang:
Dynamic thermal management for 3D multicore processors under process variations. IEICE Electron. Express 10(23): 20130800 (2013) - [c30]Wooheon Kang, Changwook Lee, Keewon Cho, Sungho Kang:
A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories. Asian Test Symposium 2013: 301-306 - 2012
- [j39]Yoseop Lim, Jaeseok Park, Sungho Kang:
A method for the fast diagnosis of multiple defects using an efficient candidate selection algorithm. IEICE Electron. Express 9(9): 834-839 (2012) - [j38]Yoseop Lim, Jaeseok Park, Sungho Kang:
An accurate diagnosis of transition fault clusters based on single fault simulation. IEICE Electron. Express 9(19): 1528-1533 (2012) - [c29]Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang:
Integration of dual channel timing formatter system for high speed memory test equipment. ISOCC 2012: 185-187 - 2011
- [j37]HyeonUk Son, Incheol Kim, Sang-Goog Lee, Jin-Ho Ahn, Jeong-Do Kim, Sungho Kang:
Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach. IEICE Trans. Electron. 94-C(8): 1344-1347 (2011) - [j36]Hyunjin Kim, Sungho Kang:
Communication-aware task scheduling and voltage selection for total energy minimization in a multiprocessor system using Ant Colony Optimization. Inf. Sci. 181(18): 3995-4008 (2011) - [j35]Hong-Sik Kim, Joohong Lee, Hyunjin Kim, Sungho Kang, Woo-Chan Park:
A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC. IEEE Trans. Circuits Syst. Video Technol. 21(11): 1581-1587 (2011) - [j34]Hyunjin Kim, Hong-Sik Kim, Sungho Kang:
A Memory-Efficient Bit-Split Parallel String Matching Using Pattern Dividing for Intrusion Detection Systems. IEEE Trans. Parallel Distributed Syst. 22(11): 1904-1911 (2011) - 2010
- [j33]Hyunjin Kim, Sungho Kang:
A Pattern Group Partitioning for Parallel String Matching using a Pattern Grouping Metric. IEEE Commun. Lett. 14(9): 878-880 (2010) - [j32]Hyunjin Kim, Hyejeong Hong, Dongmyoung Baek, Jin-Ho Ahn, Sungho Kang:
A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection. IEICE Electron. Express 7(5): 377-382 (2010) - [j31]Hong-Sik Kim, Young H. Jung, Hyunjin Kim, Jin-Ho Ahn, Woo-Chan Park, Sungho Kang:
A high performance network-on-chip scheme using lossless data compression. IEICE Electron. Express 7(11): 791-796 (2010) - [j30]YongJoon Kim, Jaeseok Park, Sungho Kang:
A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption. IEICE Trans. Inf. Syst. 93-D(1): 193-196 (2010) - [j29]YongJoon Kim, Jaeseok Park, Sungho Kang:
Selective Scan Slice Grouping Technique for Efficient Test Data Compression. IEICE Trans. Inf. Syst. 93-D(2): 380-383 (2010) - [j28]Hyunjin Kim, Hong-Sik Kim, Jung-Hee Lee, Jin-Ho Ahn, Sungho Kang:
A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection. IEICE Trans. Commun. 93-B(2): 396-398 (2010) - [j27]Hyuntae Park, Hyunjin Kim, Hong-Sik Kim, Sungho Kang:
A Fast IP Address Lookup Algorithm Based on Search Space Reduction. IEICE Trans. Commun. 93-B(4): 1009-1012 (2010) - [j26]Hyunjin Kim, Hyejeong Hong, Dongmyong Baek, Sungho Kang:
A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection. IEICE Trans. Commun. 93-B(6): 1612-1614 (2010) - [j25]Seongyong Ahn, Hyejeong Hong, Hyunjin Kim, Jin-Ho Ahn, Dongmyong Baek, Sungho Kang:
A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection. IEICE Trans. Commun. 93-B(9): 2440-2442 (2010) - [j24]Myung-Hoon Yang, Hyungjun Cho, Wooheon Kang, Sungho Kang:
EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1130-1135 (2010)
2000 – 2009
- 2009
- [j23]Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Sungho Kang:
A memory-efficient parallel string matching for intrusion detection systems. IEEE Commun. Lett. 13(12): 1004-1006 (2009) - [j22]YongJoon Kim, Jaeseok Park, Sungho Kang:
Selective scan slice repetition for simultaneous reduction of test power consumption and test data volume. IEICE Electron. Express 6(20): 1432-1437 (2009) - [j21]YongJoon Kim, Myung-Hoon Yang, Jaeseok Park, Eunsei Park, Sungho Kang:
Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time. IEICE Trans. Inf. Syst. 92-D(7): 1462-1465 (2009) - [j20]Youngkyu Park, Jaeseok Park, Taewoo Han, Sungho Kang:
An Effective Programmable Memory BIST for Embedded Memory. IEICE Trans. Inf. Syst. 92-D(12): 2508-2511 (2009) - [c28]Seung Ho Ok, Woo-Jin Seo, Jin-Ho Ahn, Sungho Kang, Byung In Moon:
An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search. FGIT-FGCN 2009: 539-546 - [c27]Woo-Jin Seo, Seung Ho Ok, Jin-Ho Ahn, Sungho Kang, Byung In Moon:
An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine. NCM 2009: 1499-1502 - [c26]Younsun Kim, Hong-Sik Kim, R. Lee, Sungho Kang:
FPGA-based verification methodology of SoC-type CMOS image signal processor. SoCC 2009: 231-234 - [c25]Sunghoon Chun, YongJoon Kim, Taejin Kim, Sungho Kang:
A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections. VTS 2009: 152-157 - 2008
- [j19]Hong-Sik Kim, Sungho Kang, Michael S. Hsiao:
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. J. Electron. Test. 24(4): 365-378 (2008) - [j18]Myung-Hoon Yang, YongJoon Kim, Sunghoon Chun, Sungho Kang:
An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR. J. Electron. Test. 24(6): 591-595 (2008) - [j17]Hong-Sik Kim, Hyunjin Kim, Sungho Kang:
Ant colony based efficient triplet calculation methodology for arithmetic built-in self test. IEICE Electron. Express 5(20): 877-881 (2008) - [j16]Kicheol Kim, Youbean Kim, Incheol Kim, HyeonUk Son, Sungho Kang:
A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters. IEICE Trans. Electron. 91-C(4): 670-672 (2008) - [j15]DongSup Song, Jin-Ho Ahn, Taejin Kim, Sungho Kang:
MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs. IEICE Trans. Inf. Syst. 91-D(4): 1197-1200 (2008) - [j14]Hyunjin Kim, Hyejeong Hong, Hong-Sik Kim, Jin-Ho Ahn, Sungho Kang:
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11): 2088-2092 (2008) - [c24]Sunghoon Chun, YongJoon Kim, Taejin Kim, Myung-Hoon Yang, Sungho Kang:
XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults. ATS 2008: 83-88 - [c23]Taejin Kim, Sunghoon Chun, YongJoon Kim, Myung-Hoon Yang, Sungho Kang:
An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme. ATS 2008: 151-156 - [c22]Sunghoon Chun, Taejin Kim, YongJoon Kim, Sungho Kang:
An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation. VTS 2008: 73-78 - 2007
- [j13]Sunghoon Chun, YongJoon Kim, Sungho Kang:
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs. J. Electron. Test. 23(4): 357-362 (2007) - [j12]Incheol Kim, Kicheol Kim, Youbean Kim, HyeonUk Son, Sungho Kang:
A New Analog-to-Digital Converter BIST Considering a Transient Zone. IEICE Trans. Electron. 90-C(11): 2161-2163 (2007) - [c21]Sunghoon Chun, YongJoon Kim, Sungho Kang:
High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects. ATS 2007: 115-120 - 2006
- [j11]Sunghoon Chun, Sangwook Kim, Hong-Sik Kim, Sungho Kang:
An Efficient Dictionary Organization for Maximum Diagnosis. J. Electron. Test. 22(1): 37-48 (2006) - [j10]Hong-Sik Kim, Sungho Kang:
Increasing encoding efficiency of LFSR reseeding-based test compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 913-917 (2006) - [j9]Sunghoon Chun, YongJoon Kim, Jung-Been Im, Sungho Kang:
MICRO: a new hybrid test data compression/decompression scheme. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 649-654 (2006) - [c20]YongJoon Kim, Myung-Hoon Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang:
An Effective Test Pattern Generation for Testing Signal Integrity. ATS 2006: 279-286 - [c19]Jin-Ho Ahn, Hyunjin Kim, Byung In Moon, Sungho Kang:
System on a Chip Implementation of Social Insect Behavior for Adaptive Network Routing. ICIC (2) 2006: 530-535 - [c18]Jin-Ho Ahn, Sungho Kang:
SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing. ICIC (2) 2006: 655-660 - [c17]Hyuntae Park, Byung In Moon, Sungho Kang:
Improved Reinforcement Computing to Implement AntNet-Based Routing Using General NPs for Ubiquitous Environments. ICUCT 2006: 242-251 - 2005
- [c16]DongSup Song, Sungho Kang:
Increasing Embedding Probabilities of RPRPs in RIN Based BIST. Asia-Pacific Computer Systems Architecture Conference 2005: 600-613 - [c15]Jin-Ho Ahn, Byung In Moon, Sungho Kang:
A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture. Asia-Pacific Computer Systems Architecture Conference 2005: 614-624 - [c14]Youbean Kim, Myung-Hoon Yang, Yong Lee, Sungho Kang:
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture. Asian Test Symposium 2005: 230-235 - 2004
- [j8]Cheong Ghil Kim, Hong-Sik Kim, Sungho Kang, Shin-Dug Kim, Gunhee Han:
An Acceleration Processor for Data Intensive Scientific Computing. IEICE Trans. Inf. Syst. 87-D(7): 1766-1773 (2004) - [j7]YongJoon Kim, Hyun-Don Kim, Sungho Kang:
A new maximal diagnosis algorithm for interconnect test. IEEE Trans. Very Large Scale Integr. Syst. 12(5): 532-537 (2004) - [c13]Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang:
RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test. Asian Test Symposium 2004: 242-247 - [c12]Jae Seuk Oh, Sung-il Bae, Jin-Ho Ahn, Sungho Kang:
Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm. ICOIN 2004: 342-349 - [c11]Byung In Moon, Hongil Yoon, Ilgu Yun, Sungho Kang:
An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications. PDCAT 2004: 539-544 - 2003
- [j6]Sungho Kang, Stephen A. Szygenda:
Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem. Simul. 79(2): 59-68 (2003) - [j5]Hong-Sik Kim, YongJoon Kim, Sungho Kang:
Test-decompression mechanism using a variable-length multiple-polynomial LFSR. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 687-690 (2003) - [c10]YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang:
A New Maximal Diagnosis Algorithm for Bus-structured Systems. ITC 2003: 349-357 - 2002
- [c9]Hong-Sik Kim, Sungho Kang:
DPSC SRAM Transparent Test Algorithm. Asian Test Symposium 2002: 145-150 - 2001
- [c8]Hong-Sik Kim, Jin-kyue Lee, Sungho Kang:
A Heuristic for Multiple Weight Set Generation. ICCD 2001: 513-514 - [c7]Hong-Sik Kim, Jin-kyue Lee, Sungho Kang:
A new multiple weight set calculation algorithm. ITC 2001: 878-884
1990 – 1999
- 1999
- [c6]Jongchul Shin, Hyunjin Kim, Sungho Kang:
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks. DATE 1999: 473- - [c5]Hyunjin Kim, Jongchul Shin, Sungho Kang:
An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. ICCD 1999: 328-329 - 1996
- [j4]Sungho Kang, Youngmin Hur, Stephen A. Szygenda:
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. VLSI Design 4(2): 119-133 (1996) - 1995
- [c4]Youngmin Hur, Stephen A. Szygenda, E. Scott Fehr, Granville E. Ott, Sungho Kang:
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. HPCA 1995: 340-347 - 1994
- [j3]Sungho Kang, Stephen A. Szygenda:
Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling. IEEE Des. Test Comput. 11(1): 18-26 (1994) - [j2]Sungho Kang, Stephen A. Szygenda:
Automatic Simulator Generation System. Simul. 63(6): 360-368 (1994) - [j1]Sungho Kang, Stephen A. Szygenda:
The simulation automation system (SAS); concepts, implementation, and results. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 89-99 (1994) - 1993
- [c3]Sungho Kang, Stephen A. Szygenda:
Automatic VHDL Model Generation System. CHDL 1993: 353-360 - 1992
- [c2]Sungho Kang, Stephen A. Szygenda:
New design error modeling and metrics for design validation. EURO-DAC 1992: 472-477 - [c1]Sungho Kang, Stephen A. Szygenda:
Modeling and Simulation of Design Errors. ICCD 1992: 443-446
Coauthor Index
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