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ORCIDDavid Boland
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2020 – today
- 2024
[j13]Carol Jingyi Li
, Richard Rademacher, David Boland, Craig T. Jin, Chad M. Spooner, Philip H. W. Leong:
S$^{3}$CA: A Sparse Strip Spectral Correlation Analyzer. IEEE Signal Process. Lett. 31: 646-650 (2024)- [i6]Binglei Lou, Richard Rademacher, David Boland, Philip H. W. Leong:
PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs. CoRR abs/2406.04910 (2024) - [i5]Binglei Lou, David Boland, Philip H. W. Leong:
fSEAD: a Composable FPGA-based Streaming Ensemble Anomaly Detection Library. CoRR abs/2406.05999 (2024) - 2023
- [j12]Xiangwei Li, Douglas L. Maskell, Carol Jingyi Li, Philip H. W. Leong, David Boland:
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. ACM Trans. Reconfigurable Technol. Syst. 16(1): 9:1-9:24 (2023) - [j11]Carol Jingyi Li, Xiangwei Li, Binglei Lou, Craig T. Jin, David Boland, Philip H. W. Leong:
Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis. ACM Trans. Reconfigurable Technol. Syst. 16(3): 41:1-41:28 (2023) - [j10]Binglei Lou, David Boland, Philip H. W. Leong:
fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library. ACM Trans. Reconfigurable Technol. Syst. 16(3): 42:1-42:27 (2023) - [c34]Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong:
Single-Batch CNN Training using Block Minifloats on FPGAs. FPGA 2023: 53 - [c33]Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao:
ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration. FPGA 2023: 209-219 - [c32]Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland, Philip H. W. Leong, Cheng Zhuo:
BOOST: Block Minifloat-Based On-Device CNN Training Accelerator with Transfer Learning. ICCAD 2023: 1-9 - [c31]Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler:
On-Board Federated Learning in Orbital Edge Computing. ICPADS 2023: 1045-1052 - [c30]Mohammad Reza Jabbarpour, Bahman Javadi, Philip H. W. Leong, Rodrigo N. Calheiros, David Boland, Chris Butler:
Performance Analysis of Federated Learning in Orbital Edge Computing. UCC 2023: 15 - 2022
- [j9]Seyedramin Rasoulinezhad, Esther Roorda, Steve Wilton, Philip H. W. Leong, David Boland:
Rethinking Embedded Blocks for Machine Learning Applications. ACM Trans. Reconfigurable Technol. Syst. 15(1): 9:1-9:30 (2022) - [c29]Wenjie Zhou, Haoyan Qi, David Boland, Philip H. W. Leong:
FPGA Implementation of N-BEATS for Time Series Forecasting Using Block Minifloat Arithmetic. APCCAS 2022: 546-550 - 2021
- [c28]Seyedramin Rasoulinezhad, David Boland, Philip H. W. Leong:
MLBlocks: FPGA Blocks for Machine Learning Applications. FPGA 2021: 228 - [c27]Sean Fox, Seyedramin Rasoulinezhad, Julian Faraone, David Boland, Philip H. W. Leong:
A Block Minifloat Representation for Training Deep Neural Networks. ICLR 2021 - 2020
- [j8]Joseph Prinable, Peter Jones, David Boland, Alistair Lee McEwan, Cindy Thamrin:
Derivation of Respiratory Metrics in Health and Asthma. Sensors 20(24): 7134 (2020) - [j7]Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong:
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(1): 115-128 (2020) - [c26]Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. FPGA 2020: 161-171 - [c25]Stephen Tridgell, David Boland, Philip H. W. Leong, Ryan Kastner, Alireza Khodamoradi, Siddhartha:
Real-time Automatic Modulation Classification using RFSoC. IPDPS Workshops 2020: 82-89 - [i4]Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. CoRR abs/2002.12900 (2020) - [i3]Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. CoRR abs/2003.03043 (2020)
2010 – 2019
- 2019
- [j6]Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong:
Unrolling Ternary Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 12(4): 22:1-22:23 (2019) - [j5]Duncan J. M. Moss, David Boland, Philip H. W. Leong:
A Two-Speed, Radix-4, Serial-Parallel Multiplier. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 769-777 (2019) - [c24]Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong:
Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs. FPT 2019: 1-9 - [c23]Stephen Tridgell, David Boland, Philip H. W. Leong, Siddhartha:
Real-Time Automatic Modulation Classification. FPT 2019: 299-302 - [c22]Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. FPT 2019: 339-342 - [i2]Stephen Tridgell, Martin Kumm, Martin Hardieck, David Boland, Duncan J. M. Moss, Peter Zipf, Philip H. W. Leong:
Unrolling Ternary Neural Networks. CoRR abs/1909.04509 (2019) - [i1]Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong:
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. CoRR abs/1911.08097 (2019) - 2018
- [c21]Sean Fox, David Boland, Philip Heng Wai Leong:
FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method. FPGA 2018: 279-284 - [c20]Julian Faraone, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Philip H. W. Leong, David Boland:
Customizing Low-Precision Deep Neural Networks for FPGAs. FPL 2018: 97-100 - [c19]Siddhartha, Steven J. E. Wilton, David Boland, Barry Flower, Perry Blackmore, Philip H. W. Leong:
Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques. FPT 2018: 306-309 - [c18]Duncan J. M. Moss, David Boland, Peyam Pourbeik, Philip Heng Wai Leong:
Real-time FPGA-based Anomaly Detection for Radio Frequency Signals. ISCAS 2018: 1-5 - [c17]Siddhartha, Yee Hui Lee, Duncan J. M. Moss, Julian Faraone, Perry Blackmore, Daniel Salmond, David Boland, Philip H. W. Leong:
Long Short-Term Memory for Radio Frequency Spectral Prediction and its Real-Time FPGA Implementation. MILCOM 2018: 1-9 - 2017
- [c16]Simon Joel Schmidt, David Boland:
Dynamic bitwidth assignment for efficient dot products. FPL 2017: 1-8 - [c15]Josh Weberruss, Lindsay Kleeman, David Boland, Tom Drummond:
FPGA acceleration of multilevel ORB feature extraction for computer vision. FPL 2017: 1-8 - [c14]Qibing Wang, Binhuang Song, Bill Corcoran, David Boland, Leimeng Zhuang, Yiwei Xie, Arthur James Lowery:
FPGA-based layered/enhanced ACO-OFDM transmitter. OFC 2017: 1-3 - 2016
- [c13]David Boland:
Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination. FPGA 2016: 244-253 - 2015
- [j4]Kan Shi, David Boland, George A. Constantinides:
Imprecise Datapath Design: An Overclocking Approach. ACM Trans. Reconfigurable Technol. Syst. 8(2): 6:1-6:23 (2015) - 2014
- [c12]Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides:
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. DAC 2014: 190:1-190:6 - [c11]Kan Shi, David Boland, George A. Constantinides:
Efficient FPGA implementation of digit parallel online arithmetic operators. FPT 2014: 115-122 - 2013
- [j3]David Boland, George A. Constantinides:
A Scalable Precision Analysis Framework. IEEE Trans. Multim. 15(2): 242-256 (2013) - [c10]Kan Shi, David Boland, George A. Constantinides:
Accuracy-Performance Tradeoffs on an FPGA through Overclocking. FCCM 2013: 29-36 - [c9]David Boland, George A. Constantinides:
Word-length optimization beyond straight line code. FPGA 2013: 105-114 - [c8]David Boland, George A. Constantinides:
Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation. FPT 2013: 410-413 - [c7]Kan Shi, David Boland, George A. Constantinides:
Overclocking datapath for latency-error tradeoff. ISCAS 2013: 2537-2540 - 2012
- [b1]David Boland:
Precision analysis for hardware acceleration of numerical algorithms. Imperial College London, UK, 2012 - [c6]Xuan You Tan, David Boland, George A. Constantinides:
FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores. ARC 2012: 290-301 - [c5]David Boland, George A. Constantinides:
A scalable approach for automated precision analysis. FPGA 2012: 185-194 - 2011
- [j2]David Boland, George A. Constantinides:
Bounding Variable Values and Round-Off Effects Using Handelman Representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1691-1704 (2011) - [j1]David Boland, George A. Constantinides:
Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods. ACM Trans. Reconfigurable Technol. Syst. 4(3): 22:1-22:14 (2011) - [c4]Christophe Le Lann, David Boland, George A. Constantinides:
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA. ARC 2011: 287-295 - 2010
- [c3]David Boland, George A. Constantinides:
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. ARC 2010: 169-181 - [c2]David Boland, George A. Constantinides:
Automated Precision Analysis: A Polynomial Algebraic Approach. FCCM 2010: 157-164
2000 – 2009
- 2008
- [c1]David Boland, George A. Constantinides:
An FPGA-based implementation of the MINRES algorithm. FPL 2008: 379-384
Coauthor Index
aka: Philip Heng Wai Leong
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