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ORCIDZahid Ullah 0001
Person information
- affiliation: Pak-Austria Fachhochschule, Institute of Applied Sciences and Technology, Department of Electrical and Computer Engineering, Haripur, Pakistan
- affiliation: CECOS University of IT & Emerging Sciences, Department of Electrical Engineering, Peshawar, Pakistan
- affiliation: City University of Hong Kong, Department of Electronic Engineering, Hong Kong
Other persons with the same name
- Zahid Ullah — disambiguation page
- Zahid Ullah 0002
![[0000-0002-7330-6129]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-7330-6129")
— University of Management and Technology Lahore, Department of Electrical Engineering, Sialkot, Pakistan (and 1 more) - Zahid Ullah 0003 — Institute of Management Sciences, Centre of Excellence in IT, Peshawar, Pakistan
- Zahid Ullah 0004 — King Abdulaziz University, Department of Information Systems, Faculty of Computing and Information Technology, Jeddah, Saudi Arabia (and 1 more)
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2020 – today
- 2023
[j19]Fahad Malook, Omer Mujahid, Zahid Ullah, Tama Fouzder:
On Enhancing the Performance of IEEE 802.11ah by Employing a Dynamic Raw Approach in IoT Networks. Wirel. Pers. Commun. 129(3): 1983-1997 (2023)- 2022
- [j18]Muhammad Irfan, Hasan Erdem Yantir, Zahid Ullah, Ray C. C. Cheung:
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs. IEEE Embed. Syst. Lett. 14(2): 63-66 (2022) - [j17]Muhammad Irfan, Abdurrashid Ibrahim Sanka, Zahid Ullah, Ray C. C. Cheung:
Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey. Future Gener. Comput. Syst. 128: 451-465 (2022) - 2021
- [j16]Muhammad Bilal, Zahid Ullah, Ihtesham Ul Islam:
Fast Codebook Generation Using Pattern Based Masking Algorithm for Image Compression. IEEE Access 9: 98904-98915 (2021) - [j15]Muhammad Ibrahim, Omer Mujahid, Najib Ur Rehman, Azhar Qazi, Zahid Ullah, Tama Fouzder:
An FPGA-Based Accelerated Mutation Detection System for the Tumor Suppressor Gene. IEEE Access 9: 164542-164550 (2021) - [j14]Muhammad Irfan, Zahid Ullah, Abdurrashid Ibrahim Sanka, Ray C. C. Cheung:
Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory. IEEE Embed. Syst. Lett. 13(2): 37-40 (2021) - [j13]Khalid Rehman, Zahid Ullah:
PackeX: Low-Power High-Performance Packet Classifier Using Memory on FPGAs. Wirel. Commun. Mob. Comput. 2021: 5544435:1-5544435:9 (2021) - 2020
- [j12]Omer Mujahid, Zahid Ullah:
High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA. IEEE Embed. Syst. Lett. 12(3): 87-90 (2020) - [j11]Muhammad Irfan, Zahid Ullah, Mehdi Hasan Chowdhury, Ray C. C. Cheung:
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1925-1929 (2020)
2010 – 2019
- 2019
- [j10]Muhammad Irfan, Zahid Ullah, Ray C. C. Cheung:
D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs. IEEE Access 7: 96060-96069 (2019) - [j9]Hassan Mahmood, Zahid Ullah, Omer Mujahid, Inayat Ullah, Abdul Hafeez:
Beyond the Limits of Typical Strategies: Resources Efficient FPGA-Based TCAM. IEEE Embed. Syst. Lett. 11(3): 89-92 (2019) - [j8]Inayat Ullah, Zahid Ullah, Umar Afzaal, Jeong-A Lee:
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1298-1307 (2019) - [c6]Muhammad Irfan, Ray C. C. Cheung, Zahid Ullah:
Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs. ASAP 2019: 288-291 - [c5]Najib Ur Rehman, Omer Mujahid, Muhammad Irfan, Abdul Hafeez, Zahid Ullah:
Low Power Pre-comparison Configuration Strategy for a Logic-based Binary CAM on FPGA. INTELLECT 2019: 1-5 - [c4]Omer Mujahid, Zahid Ullah, Abdul Hafeez, Tama Fouzder:
Design Exploration of LH-CAM with Updating Mechanism. IJCCI 2019: 477-486 - [c3]Muhammad Irfan, Zahid Ullah, Ray C. C. Cheung:
High Performance Power-Efficient Gate-Based CAM for Reconfigurable Computing. MSN 2019: 327-331 - 2018
- [j7]Omer Mujahid, Zahid Ullah, Hassan Mahmood, Abdul Hafeez:
Fast Pattern Recognition Through an LBP Driven CAM on FPGA. IEEE Access 6: 39525-39531 (2018) - [j6]Farkhanda Syed, Zahid Ullah, Manish Kumar Jaiswal:
Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA. IEEE Embed. Syst. Lett. 10(3): 73-76 (2018) - [j5]Muhammad Riaz, Miraj M. Khan, Zahid Ullah:
A Three-Dimensional Geometrical Scattering Model for Cellular Communication Environment. Wirel. Pers. Commun. 98(4): 3443-3454 (2018) - 2017
- [j4]Muhammad Irfan, Zahid Ullah:
G-AETCAM: Gate-Based Area-Efficient Ternary Content-Addressable Memory on FPGA. IEEE Access 5: 20785-20790 (2017) - [j3]Zahid Ullah:
LH-CAM: Logic-Based Higher Performance Binary CAM Architecture on FPGA. IEEE Embed. Syst. Lett. 9(2): 29-32 (2017) - 2015
- [j2]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung:
Z-TCAM: An SRAM-based Architecture for TCAM. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 402-406 (2015) - 2014
- [j1]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung:
E-TCAM: An Efficient SRAM-Based Architecture for TCAM. Circuits Syst. Signal Process. 33(10): 3123-3144 (2014) - 2013
- [c2]Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung:
Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). FPL 2013: 1-4 - 2012
- [c1]Zahid Ullah, Manish Kumar Jaiswal, Y. C. Chan, Ray C. C. Cheung:
FPGA Implementation of SRAM-based Ternary Content Addressable Memory. IPDPS Workshops 2012: 383-389
Coauthor Index
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