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2020 – today
- 2024
[c20]V. Mahboubi, Á. Gómez, Antonio Calomarde, Daniel Arumí, R. Rodríguez, Salvador Manich:
On the Fine Tuning of RRAM Resistance Under Variability Using Current Pulses at SET. IOLTS 2024: 1-7- 2023
- [j11]Maryam Akbari
, Sattar Mirzakuchaki, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Francesca Campabadal, Mireia Bargallo González, Rosa Rodríguez-Montañés:
True Random Number Generator Based on the Variability of the High Resistance State of RRAMs. IEEE Access 11: 66682-66693 (2023) - 2022
- [j10]Antonio Calomarde, Salvador Manich, Antonio Rubio, Francisco Gámiz:
Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact. IEEE Access 10: 47169-47178 (2022) - [c19]V. Mahboubi, Daniel Arumí, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Salvador Manich:
On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental Data. DCIS 2022: 1-6 - 2021
- [c18]P. Albiol, Salvador Manich, Daniel Arumí, Rosa Rodríguez-Montañés, Álvaro Gómez-Pau:
Low Cost AES Protection Against DPA Using Rolling Codes. DCIS 2021: 1-6 - [c17]Binbin Yang, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Rosa Rodríguez-Montañés, Juan Bautista Roldán, Mireia Bargallo González, Francesca Campabadal, Liang Fang:
Simulation of serial RRAM cell based on a Verilog-A compact model. DCIS 2021: 1-6
2010 – 2019
- 2019
- [j9]Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich:
A Calibratable Detector for Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1067-1079 (2019) - 2018
- [j8]Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl:
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 392-403 (2018) - 2017
- [j7]Madalin Neagu, Salvador Manich:
Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis. Microelectron. J. 62: 85-98 (2017) - 2016
- [c16]Daniel Arumí, Salvador Manich, Rosa Rodríguez-Montañés:
RRAM based cell for hardware security applications. IVSW 2016: 1-6 - 2015
- [j6]Madalin-Ioan Neagu, Liviu Miclea, Salvador Manich:
Improving security in cache memory by power efficient scrambling technique. IET Comput. Digit. Tech. 9(6): 283-292 (2015) - 2014
- [c15]Madalin Neagu, Liviu Miclea, Salvador Manich:
Interleaved scrambling technique: A novel low-power security layer for cache memories. ETS 2014: 1-2 - [c14]Michael Weiner, Salvador Manich, Georg Sigl:
A Low Area Probing Detector for Power Efficient Security ICs. RFIDSec 2014: 185-197 - 2013
- [j5]Salvador Manich, Martin Strasser:
A Highly Time Sensitive XOR Gate for Probe Attempt Detectors. IEEE Trans. Circuits Syst. II Express Briefs 60-II(11): 786-790 (2013) - [c13]Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl:
Differential scan-path: A novel solution for secure design-for-testability. ITC 2013: 1-9 - 2012
- [c12]Salvador Manich, Markus S. Wamser, Georg Sigl:
Detection of probing attempts in secure ICs. HOST 2012: 134-139 - 2010
- [c11]S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich:
Design and implementation of Automatic Test Equipment IP module. ETS 2010: 244
2000 – 2009
- 2007
- [j4]Salvador Manich, Lucas Garcia-Deiros, Joan Figueras:
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2046-2058 (2007) - 2004
- [j3]Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras:
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electron. Test. 20(4): 345-355 (2004) - [c10]Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
BIST Technique by Equally Spaced Test Vector Sequences. VTS 2004: 206-216 - 2003
- [c9]Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras:
On the selection of efficient arithmetic additive test pattern generators [logic test]. ETW 2003: 9-14 - [c8]Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez:
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. PATMOS 2003: 80-89 - 2002
- [c7]Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras:
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC 2002: 814-823 - [c6]Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Luz Balado, Joan Figueras:
On High-Quality, Low Energy BIST Preparation at RT-Level. LATW 2002: 52-57 - 2000
- [j2]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low Power BIST by Filtering Non-Detecting Vectors. J. Electron. Test. 16(3): 193-202 (2000)
1990 – 1999
- 1999
- [c5]Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, João Paulo Teixeira, Marcelino B. Santos:
Low power BIST by filtering non-detecting vectors. ETW 1999: 165-170 - [c4]Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, João Paulo Teixeira, Marcelino B. Santos:
Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113 - 1997
- [j1]Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras:
Fault-Secure Parity Prediction Arithmetic Operators. IEEE Des. Test Comput. 14(2): 60-71 (1997) - [c3]Salvador Manich, Joan Figueras:
Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. ED&TC 1997: 597-602 - 1996
- [c2]Michael Nicolaidis, Salvador Manich, Joan Figueras:
Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and Implementations. ED&TC 1996: 186-194 - [c1]Salvador Manich, Michael Nicolaidis, Joan Figueras:
Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring. VTS 1996: 124-129
Coauthor Index
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