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ORCIDNuno Miguel Cardanha Paulino
Person information
- affiliation: University of Porto, Department of Informatics Engineering, Portugal
Other persons with the same name
- Nuno Paulino 0002
![[0000-0001-8053-902X]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-8053-902X")
(aka: Nuno F. Paulino) — Universidade NOVA de Lisboa, Caparica, Portugal - Nuno Paulino 0003 (aka: Nuno M. G. Paulino) — University of Warwick, Coventry, UK (and 3 more)
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2020 – today
- 2024
[c18]Manuel Cerqueira da Silva, Luís Miguel Sousa, Nuno Paulino, João Bispo:
A DSL and MLIR Dialect for Streaming and Vectorisation. ARC 2024: 181-190- [c17]Rafael A. Aguiar, Nuno Paulino, Luís M. Pessoa:
A Deep Learning Approach in RIS-based Indoor Localization. EuCNC/6G Summit 2024: 523-528 - [c16]Filipe B. Teixeira, Manuel Ricardo, André Coelho, Hélder P. Oliveira, Paula Viana, Nuno Paulino, Helder Fontes, Paulo Marques, Rui Campos, Luís M. Pessoa:
CONVERGE: A Vision-Radio Research Infrastructure Towards 6G and Beyond. EuCNC/6G Summit 2024: 1015-1020 - [c15]Mariana Oliveira, Francisco M. Ribeiro, Nuno Paulino, Okan Yurduseven, Luís M. Pessoa:
SpecRF-Posture: Exploring Specular Reflections for Human Posture Recognition. MeditCom 2024: 227-232 - [c14]Miguel Henriques, João Bispo, Nuno Paulino:
Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-Study. RAPIDO@HiPEAC 2024: 42-50 - [i6]Filipe B. Teixeira, Manuel Ricardo, André Coelho, Hélder P. Oliveira, Paula Viana, Nuno Paulino, Helder Fontes, Paulo Marques, Rui Campos, Luís M. Pessoa:
Vision-Radio Experimental Infrastructure Architecture Towards 6G. CoRR abs/2402.19416 (2024) - 2023
- [j9]Nuno Paulino, Luís M. Pessoa:
Self-Localization via Circular Bluetooth 5.1 Antenna Array Receiver. IEEE Access 11: 365-395 (2023) - [c13]Luís Miguel Sousa, João Bispo, Nuno Paulino:
Retargeting Applications for Heterogeneous Systems with the Tribble Source-to-Source Framework. PACT 2023: 329-331 - [c12]Rafael A. Aguiar, Nuno Paulino, Luís M. Pessoa:
Enhancing NLoS RIS-Aided Localization with Optimization and Machine Learning. GLOBECOM (Workshops) 2023: 1898-1903 - [c11]João Bispo, Nuno Paulino, Luís Miguel Sousa:
Challenges and Opportunities in C/C++ Source-To-Source Compilation (Invited Paper). PARMA-DITAM 2023: 2:1-2:15 - 2022
- [c10]Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves:
Design and Experimental Evaluation of a Bluetooth 5.1 Antenna Array for Angle-of-Arrival Estimation. CSNDSP 2022: 625-630 - [d2]Nuno Paulino:
A Dataset of Phase Samples using an 8-Element Uniform Circular Antenna Array and a Bluetooth Low Energy 5.1 Nordic nRF52811 Based Receiver. IEEE DataPort, 2022
- [d1]Nuno Paulino:
A Batch of Integer Data Sets for Clustering Algorithms. IEEE DataPort, 2022 - 2021
- [j8]Nuno Paulino, João Canas Ferreira, João M. P. Cardoso:
Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey. ACM Comput. Surv. 53(1): 6:1-6:36 (2021) - [j7]Nuno Paulino, João Bispo, João Canas Ferreira, João M. P. Cardoso:
A Binary Translation Framework for Automated Hardware Generation. IEEE Micro 41(4): 15-23 (2021) - [c9]Nuno Paulino, Luís M. Pessoa, André Branquinho, Edgar Gonçalves:
Evaluating a Novel Bluetooth 5.1 AoA Approach for Low-Cost Indoor Vehicle Tracking via Simulation. EuCNC/6G Summit 2021: 259-264 - [c8]Tiago Santos, Nuno Paulino, João Bispo, João M. P. Cardoso, João Canas Ferreira:
On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators. FPT 2021: 1-4 - [c7]Pedro Filipe Silva, João Bispo, Nuno Paulino:
FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example. FPT 2021: 1-4 - [i5]Pedro Filipe Silva, João Bispo, Nuno Miguel Cardanha Paulino:
Building Beyond HLS: Graph Analysis and Others. CoRR abs/2104.02676 (2021) - [i4]Hélder Campos, Nuno Paulino:
Augmentation of base classifier performance via HMMs on a handwritten character data set. CoRR abs/2111.10204 (2021) - [i3]Hélder F. S. Campos, Nuno Paulino:
Multiple target tracking with interaction using an MCMC MRF Particle Filter. CoRR abs/2111.13184 (2021) - [i2]Nuno Miguel Cardanha Paulino, Luís M. Pessoa, André Branquinho, Rafael Tavares, Igor Ferreira:
Optimizing Packet Reception Rates for Low Duty-Cycle BLE Relay Nodes. CoRR abs/2111.13414 (2021) - [i1]Luís Miguel Sousa, Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo:
A Flexible HLS Hoeffding Tree Implementation for Runtime Learning on FPGA. CoRR abs/2112.01875 (2021) - 2020
- [j6]Nuno Paulino, João Canas Ferreira, João M. P. Cardoso:
Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets. IEEE Access 8: 152286-152304 (2020) - [c6]Nuno Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso:
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. FPL 2020: 367
2010 – 2019
- 2019
- [j5]Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 116-125 (2019) - 2017
- [j4]Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 21-34 (2017) - [c5]Nuno Paulino, Luís Reis, João M. P. Cardoso:
On Coding Techniques for Targeting FPGAs via OpenCL. PARCO 2017: 652-663 - 2016
- [b1]Nuno Miguel Cardanha Paulino:
Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration. University of Porto, Portugal, 2016 - 2015
- [j3]Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses. ACM Trans. Reconfigurable Technol. Syst. 7(4): 29:1-29:20 (2015) - [c4]Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Bispo, João M. P. Cardoso:
Transparent acceleration of program execution using reconfigurable hardware. DATE 2015: 1066-1071 - 2014
- [c3]Nuno Miguel Cardanha Paulino, João Canas Ferreira, João Manuel Paiva Cardoso:
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support. ISPA 2014: 158-165 - 2013
- [j2]João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira:
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units. Int. J. Reconfigurable Comput. 2013: 340316:1-340316:20 (2013) - [j1]João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira:
Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems. IEEE Trans. Ind. Informatics 9(3): 1625-1634 (2013) - [c2]Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
Architecture for Transparent Binary Acceleration of Loops with Memory Accesses. ARC 2013: 122-133 - 2011
- [c1]João Bispo, Nuno Miguel Cardanha Paulino, João M. P. Cardoso, João Canas Ferreira:
From Instruction Traces to Specialized Reconfigurable Arrays. ReConFig 2011: 386-391
Coauthor Index
aka: João Manuel Paiva Cardoso
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