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Roland Dobai
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2010 – 2019
- 2019
- [j7]Vojtech Mrazek
, Lukás Sekanina, Roland Dobai, Marek Sýs
, Petr Svenda:
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2734-2744 (2019) - 2017
- [j6]Roland Dobai, Jan Korenek, Lukás Sekanina:
Evolutionary design of hash function pairs for network filters. Appl. Soft Comput. 56: 173-181 (2017) - [c13]Marek Kidon, Roland Dobai:
Evolutionary design of hash functions for IP address hashing using genetic programming. CEC 2017: 1720-1727 - [c12]Jakub Husa, Roland Dobai:
Designing bent boolean functions with parallelized linear genetic programming. GECCO (Companion) 2017: 1825-1832 - 2016
- [c11]Roland Dobai, Jan Korenek, Lukás Sekanina:
Adaptive development of hash functions in FPGA-based network routers. SSCI 2016: 1-8 - 2015
- [j5]Roland Dobai, Lukás Sekanina:
Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware. ACM Trans. Reconfigurable Technol. Syst. 8(3): 20:1-20:24 (2015) - [c10]Roland Dobai, Jan Korenek:
Evolution of Non-Cryptographic Hash Function Pairs for FPGA-Based Network Applications. SSCI 2015: 1214-1219 - 2014
- [c9]Roland Dobai:
Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems. FPL 2014: 1-6 - [c8]Roland Dobai, Kyrre Glette, Jim Tørresen, Lukás Sekanina:
Evolutionary digital circuit design with fast candidate solution establishment in field programmable gate arrays. ICES 2014: 85-92 - 2013
- [j4]Roland Dobai, Marcel Baláz:
Compressed Skewed-Load Delay Test Generation Based on Evolution and Deterministic Initialization of Populations. Comput. Informatics 32(2): 251-272 (2013) - [j3]Roland Dobai, Marcel Baláz:
SAT-based generation of compressed skewed-load tests for transition delay faults. Microprocess. Microsystems 37(2): 196-205 (2013) - [c7]Roland Dobai, Lukás Sekanina:
Image filter evolution on the Xilinx Zynq Platform. AHS 2013: 164-171 - [c6]Roland Dobai, Lukás Sekanina:
Towards evolvable systems based on the Xilinx Zynq platform. ICES 2013: 89-95 - 2012
- [c5]Roland Dobai, Marcel Baláz:
Genetic method for compressed skewed-load delay test generation. DDECS 2012: 242-247 - [c4]Roland Dobai, Marcel Baláz, Mária Fischerová:
Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores. DSD 2012: 73-78 - 2011
- [j2]Roland Dobai, Elena Gramatová:
A novel automatic test pattern generator for asynchronous sequential digital circuits. Microelectron. J. 42(3): 501-508 (2011) - [c3]Roland Dobai, Marcel Baláz:
SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults. DSD 2011: 191-196 - 2010
- [j1]Roland Dobai, Elena Gramatová:
Deductive Fault Simulation Technique for Asynchronous Circuits. Comput. Informatics 29(6): 1025-1043 (2010) - [c2]Roland Dobai, Elena Gramatová:
Test pattern generation for the combinational representation of asynchronous circuits. DDECS 2010: 323-328
2000 – 2009
- 2009
- [c1]Roland Dobai, Elena Gramatová:
Deductive Fault Simulation for Asynchronous Sequential Circuits. DSD 2009: 459-464
Coauthor Index
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