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ORCIDShahar Kvatinsky
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2020 – today
- 2021
[j28]Dalibor Biolek, Zdenek Kolka, Viera Biolková, Zdenek Biolek, Shahar Kvatinsky:
(V)TEAM for SPICE Simulation of Memristive Devices With Improved Numerical Performance. IEEE Access 9: 30242-30255 (2021)- [j27]Nicolás Wainstein
, Gina C. Adam, Eilam Yalon, Shahar Kvatinsky:
Radiofrequency Switches Based on Emerging Resistive Memory Technologies - A Survey. Proc. IEEE 109(1): 77-95 (2021) - 2020
- [j26]Hanna Abo Hanna, Loai Danial, Shahar Kvatinsky, Ramez Daniel:
Cytomorphic Electronics With Memristors for Modeling Fundamental Genetic Circuits. IEEE Trans. Biomed. Circuits Syst. 14(3): 386-401 (2020) - [j25]Rotem Ben Hur, Ronny Ronen, Ameer Haj Ali, Debjyoti Bhattacharjee, Adi Eliahu, Natan Peled, Shahar Kvatinsky:
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2434-2447 (2020) - [c37]Loai Danial, V. Gupta, Evgeny Pikhay, Yakov Roizin, Shahar Kvatinsky:
Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing. DATE 2020: 472-477 - [c36]Vishal Gupta, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi:
Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. DFT 2020: 1-6 - [c35]Loai Danial, Shahar Kvatinsky:
Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters. ECCTD 2020: 1-4 - [c34]Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky:
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. ICCAD 2020: 150:1-150:9 - [c33]Loai Danial, Kanishka Sharma, Shahar Kvatinsky:
A Pipelined Memristive Neural Network Analog-to-Digital Converter. ISCAS 2020: 1-5 - [c32]Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator using STT-MTJ. ISCAS 2020: 1 - [c31]Adi Eliahu, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. VLSI-SOC 2020: 28-33 - [c30]Natan Peled, Rotem Ben Hur, Ronny Ronen, Shahar Kvatinsky:
X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. VLSI-SOC 2020: 64-69 - [i5]Debjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky:
CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. CoRR abs/2009.00881 (2020)
2010 – 2019
- 2019
- [j24]Nishil Talati, Heonjae Ha, Ben Perach, Ronny Ronen, Shahar Kvatinsky:
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. IEEE Micro 39(1): 33-43 (2019) - [j23]Nimrod Wald, Shahar Kvatinsky:
Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic. Microelectron. J. 86: 22-33 (2019) - [j22]Misbah Ramadan, Nicolás Wainstein, Ran Ginosar, Shahar Kvatinsky:
Adaptive programming in multi-level cell ReRAM. Microelectron. J. 90: 169-180 (2019) - [j21]Edouard Giacomin, Tzofnat Greenberg-Toledo, Shahar Kvatinsky, Pierre-Emmanuel Gaillardon:
A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 643-654 (2019) - [j20]Tzofnat Greenberg-Toledo, Roee Mazor, Ameer Haj Ali, Shahar Kvatinsky:
Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1571-1583 (2019) - [j19]Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2473-2484 (2019) - [c29]Shahar Kvatinsky:
Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU). ASAP 2019: 142-148 - [c28]Loai Danial, Kanishka Sharma, Shivansh Dwivedi, Shahar Kvatinsky:
Logarithmic Neural Network Data Converters using Memristors for Biomedical Applications. BioCAS 2019: 1-4 - [c27]Ben Perach, Shahar Kvatinsky:
STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ. DATE 2019: 264-267 - [c26]Jeffry Louis, Barak Hoffer, Shahar Kvatinsky:
Performing Memristor-Aided Logic (MAGIC) using STT-MRAM. ICECS 2019: 787-790 - [c25]Marco Ottavi, Vishal Gupta, Saurabh Khandelwal, Shahar Kvatinsky, Jimson Mathew, Eugenio Martinelli, Abusaleh M. Jabir:
The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors. IOLTS 2019: 159-164 - [c24]Loai Danial, Sidharth Thomas, Shahar Kvatinsky:
Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks. ISCAS 2019: 1-5 - [c23]Nicolás Wainstein, Tamir Tsabari, Yarden Goldin, Eilam Yalon, Shahar Kvatinsky:
A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors. ISVLSI 2019: 290-295 - [c22]Shahar Kvatinsky:
Real Processing-In-Memory with Memristive Memory Processing Unit. SPACE 2019: 5-8 - [c21]João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. VLSI-SoC 2019: 160-165 - [c20]João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. VLSI-SoC (Selected Papers) 2019: 257-278 - [p1]John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks 2019: 1065-1099 - [i4]Kunal Korgaonkar, Ronny Ronen, Anupam Chattopadhyay, Shahar Kvatinsky:
The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. CoRR abs/1910.10234 (2019) - [i3]Tzofnat Greenberg-Toledo, Ben Perach, Daniel Soudry, Shahar Kvatinsky:
MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks. CoRR abs/1912.12636 (2019) - 2018
- [j18]Loai Danial, Nicolás Wainstein, Shraga Kraus, Shahar Kvatinsky:
DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(1): 146-158 (2018) - [j17]Alexander Dozortsev, Israel Goldshtein, Shahar Kvatinsky:
Analysis of the row grounding technique in a memristor-based crossbar array. Int. J. Circuit Theory Appl. 46(1): 122-137 (2018) - [j16]Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky:
Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. IEEE Micro 38(5): 13-21 (2018) - [j15]Nicolás Wainstein, Shahar Kvatinsky:
TIME - Tunable Inductors Using MEmristors. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(5): 1505-1515 (2018) - [j14]Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Shahar Kvatinsky:
IMAGING: In-Memory AlGorithms for Image processiNG. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4258-4271 (2018) - [j13]Loai Danial, Nicolás Wainstein, Shraga Kraus, Shahar Kvatinsky:
Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture. IEEE Trans. Emerg. Top. Comput. Intell. 2(5): 396-409 (2018) - [c19]Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Practical challenges in delivering the promises of real processing-in-memory machines. DATE 2018: 1628-1633 - [c18]Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Shahar Kvatinsky:
Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC. ISCAS 2018: 1-5 - [c17]Loai Danial, Shahar Kvatinsky:
Real-Time Trainable Data Converters for General Purpose Applications. NANOARCH 2018: 34-36 - 2017
- [j12]Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. IEEE Des. Test 34(2): 39-50 (2017) - [c16]Hanna Abo Hanna, Loai Danial, Shahar Kvatinsky, Ramez Daniel:
Modeling biochemical reactions and gene networks with memristors. BioCAS 2017: 1-4 - [c15]Said Hamdioui, Shahar Kvatinsky, Gert Cauwenberghs, Lei Xie, Nimrod Wald, Siddharth Joshi, Hesham Mostafa Elsayed, Henk Corporaal, Koen Bertels:
Memristor for computing: Myth or reality? DATE 2017: 722-731 - [c14]Leonid Azriel, Shahar Kvatinsky:
Towards a memristive hardware secure hash function (MemHash). HOST 2017: 51-55 - [c13]Rotem Ben Hur, Nimrod Wald, Nishil Talati, Shahar Kvatinsky:
Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic. ICCAD 2017: 225-232 - [c12]Nishil Talati, Zhiying Wang, Shahar Kvatinsky:
Rate-compatible and high-throughput architecture designs for encoding LDPC codes. ISCAS 2017: 1-4 - [c11]Nicolás Wainstein, Shahar Kvatinsky:
An RF memristor model and memristive single-pole double-throw switches. ISCAS 2017: 1-4 - [c10]John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Memristive logic: A framework for evaluation and comparison. PATMOS 2017: 1-8 - 2016
- [j11]Amir Morad, Leonid Yavits, Shahar Kvatinsky, Ran Ginosar:
Resistive GP-SIMD Processing-In-Memory. ACM Trans. Archit. Code Optim. 12(4): 57:1-57:22 (2016) - [j10]Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi:
Information-Theoretic Sneak-Path Mitigation in Memristor Crossbar Arrays. IEEE Trans. Inf. Theory 62(9): 4801-4813 (2016) - [c9]Eyal Rosenthal, Sergey Greshnikov, Daniel Soudry, Shahar Kvatinsky:
A fully analog memristor-based neural network with online gradient training. ISCAS 2016: 1394-1397 - [c8]Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi:
Write sneak-path constraints avoiding disturbs in memristor crossbar arrays. ISIT 2016: 950-954 - [c7]Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Improving energy efficiency of DRAM by exploiting half page row access. MICRO 2016: 27:1-27:12 - [c6]Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz:
Evaluating programmable architectures for imaging and vision applications. MICRO 2016: 52:1-52:13 - [c5]Rotem Ben Hur, Shahar Kvatinsky:
Memory Processing Unit for in-memory processing. NANOARCH 2016: 171-172 - [c4]Elad Amrani, Avishay Drori, Shahar Kvatinsky:
Logic design with unipolar memristors. VLSI-SoC 2016: 1-5 - [c3]Nimrod Wald, Elad Amrani, Avishay Drori, Shahar Kvatinsky:
Logic with Unipolar Memristors - Circuits and Design Methodology. VLSI-SoC (Selected Papers) 2016: 24-40 - [i2]Ardavan Pedram, Stephen Richardson, Sameh Galal, Shahar Kvatinsky, Mark Horowitz:
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. CoRR abs/1602.04183 (2016) - [i1]Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz:
A Systematic Approach to Blocking Convolutional Neural Networks. CoRR abs/1606.04209 (2016) - 2015
- [j9]Leonid Yavits, Shahar Kvatinsky, Amir Morad, Ran Ginosar:
Resistive Associative Processor. IEEE Comput. Archit. Lett. 14(2): 148-151 (2015) - [j8]Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny:
VTEAM: A General Model for Voltage-Controlled Memristors. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 786-790 (2015) - [j7]Daniel Soudry, Dotan Di Castro, Asaf Gal, Avinoam Kolodny, Shahar Kvatinsky:
Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training. IEEE Trans. Neural Networks Learn. Syst. 26(10): 2408-2421 (2015) - [j6]Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny:
Multistate Register Based on Resistive RAM. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1750-1759 (2015) - 2014
- [j5]Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Multithreading. IEEE Comput. Archit. Lett. 13(1): 41-44 (2014) - [j4]Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky:
Logic operations in memory using a memristive Akers array. Microelectron. J. 45(11): 1429-1437 (2014) - [j3]Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
MAGIC - Memristor-Aided Logic. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 895-899 (2014) - [j2]Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2054-2066 (2014) - 2013
- [j1]Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser:
TEAM: ThrEshold Adaptive Memristor Model. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 211-221 (2013) - [c2]Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi:
Sneak-path constraints in memristor crossbar arrays. ISIT 2013: 156-160 - 2011
- [c1]Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman:
Memristor-based IMPLY logic design procedure. ICCD 2011: 142-147
Coauthor Index
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