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Dondee Navarro
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2020 – today
- 2021
- [j9]Abhishek Kar
, Mitiko Miura-Mattausch
, Mainak Sengupta
, Dondee Navarro
, Hideyuki Kikuchihara, Takahiro Iizuka
, Hafizur Rahaman
, Hans Jürgen Mattausch
:
Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation. IEEE Access 9: 23786-23794 (2021) - 2020
- [j8]Kenshiro Sato, Dondee Navarro, Shinya Sekizaki
, Yoshifumi Zoka, Naoto Yorino
, Hans Jürgen Mattausch, Mitiko Miura-Mattausch:
Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model. IEICE Trans. Electron. 103-C(3): 119-126 (2020)
2010 – 2019
- 2019
- [j7]Arnab Mukhopadhyay
, Tapas Kumar Maiti
, Sandip Bhattacharya
, Takahiro Iizuka, Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Hafizur Rahaman
, Sadayuki Yoshitomi, Dondee Navarro, Hans Jürgen Mattausch:
Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs. IEICE Trans. Electron. 102-C(6): 487-494 (2019) - [j6]Nezam Rohbani, Hiroaki Gau, Sara Mohammadinejad, Tapas Kumar Maiti
, Dondee Navarro
, Mitiko Miura-Mattausch
, Hans Jürgen Mattausch
, Hirotaka Takatsuka:
Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1675-1684 (2019) - [c7]Nezam Rohbani, Tapas Kumar Maiti
, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka:
NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache. ICCD 2019: 264-272 - [c6]Takao Yamamoto, Yukiya Fukunaga, Daisaku Ikoma, Mitiko Miura-Mattausch, Dondee Navarro, Hans Jürgen Mattausch:
Analysis of Embedded-Diode Performance in MOSFET under Switching Condition. ISDCS 2019: 1-4 - 2018
- [j5]Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Tapas K. Maiti
, Nezam Rohbani, Dondee Navarro, Hans Jürgen Mattausch:
Compact modeling of dynamic trap density evolution for predicting circuit-performance aging. Microelectron. Reliab. 80: 164-175 (2018) - [c5]Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Tahahiro Kajiwara, Yuta Tanimoto, Atsushi Saito, Takahiro Iizuka, Dondee Navarro, Hans Jürgen Mattausch:
Compact Modeling for Power Efficient Circuit Design. ESSDERC 2018: 234-237 - [c4]Sunandan Dutta
, Tapas K. Maiti
, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya
, Dondee Navarro, Naoto Yorino
, Hans Jürgen Mattausch:
Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces. SIMPAR 2018: 137-143 - 2017
- [c3]Tapas K. Maiti
, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch:
Compact modeling approach for electro-mechanical system simulation. ASICON 2017: 981-984 - [c2]Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Dondee Navarro, Tapas K. Maiti
, Nezam Rohbani, C. Ma, Hans Jürgen Mattausch, A. Schiffmann, Alexander Steinmair, Ehrenfried Seebacher:
Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits. ESSDERC 2017: 192-195
2000 – 2009
- 2009
- [j4]Ryosuke Inagaki, Norio Sadachika, Dondee Navarro, Mitiko Miura-Mattausch, Yasuaki Inoue:
A GIDL-Current Model for Advanced MOSFET Technologies without Binning. IPSJ Trans. Syst. LSI Des. Methodol. 2: 93-102 (2009) - 2008
- [j3]Tatsuya Ezaki, Dondee Navarro, Youichi Takeda, Norio Sadachika, Gaku Suzuki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto:
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. Math. Comput. Simul. 79(4): 1096-1106 (2008) - 2007
- [j2]Yoshioki Isobe, Kiyohito Hara, Dondee Navarro, Youichi Takeda, Tatsuya Ezaki, Mitiko Miura-Mattausch:
Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition. IEICE Trans. Electron. 90-C(4): 885-894 (2007) - 2005
- [j1]Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. IEICE Trans. Electron. 88-C(5): 1079-1086 (2005) - [c1]Youichi Takeda, Dondee Navarro, Shingo Chiba, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto:
MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. CICC 2005: 827-830
Coauthor Index
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