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ORCIDIEEE Journal of Solid-State Circuits, Volume 54
Volume 54, Number 1, January 2019
- Yohan Frans
, Wim Dehaene, Masato Motomura, Seung-Jun Bae:
Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). 3-5
- Emanuele Depaoli, Hongyang Zhang, Marco Mazzini, Walter Audoglio, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Enrico Temporiti, Andrea Mazzanti:
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS. 6-17 - Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang:
A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. 18-28 - Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Dan Shi, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET. 29-42 - John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. 43-54 - Kyeongha Kwon, Jong-Hyeok Yoon, Younho Jeon, Hanho Choi, Sejun Jeon, Hyeon-Min Bae:
An Electronic Dispersion Compensation Transceiver for 10- and 28-Gb/s Directly Modulated Lasers-Based Optical Links. 55-64 - Karim M. Megawer, Ahmed Elkholy, Mostafa Gamal Ahmed, Ahmed Elmallah, Pavan Kumar Hanumolu:
Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers. 65-74 - Anvesha Amaravati, Saad Bin Nasir, Justin Ting, Insik Yoon, Arijit Raychowdhury:
A 55-nm, 1.0-0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots. 75-87 - Shiheng Yang, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs. 88-98 - Minseob Lee, Shinwoong Kim, Hong-June Park, Jae-Yoon Sim:
A 0.0043-mm2 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC. 99-108 - Somnath Kundu, Muqing Liu, Shi-Jie Wen, Richard Wong, Chris H. Kim:
A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer. 109-120 - Christopher J. Berry, David Wolpert, Christos Vezyrtzis, Richard F. Rizzolo, Sean M. Carey, Yaniv Maroz, Hunter F. Shi, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Thomas Strach, Alper Buyuktosunoglu, Preetham Lobo, Pierce Chuang, Pawel Owczarczyk, Ramon Bertran, Tobias Webel, Phillip J. Restle:
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. 121-132 - Thomas Burd, Noah Beck, Sean White, Milam Paraschou, Nathan Kalyanasundharam, Gregg Donley, Alan Smith, Larry Hewitt, Samuel Naffziger:
"Zeppelin": An SoC for Multichip Architectures. 133-143 - Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. 144-157 - Daniel Bankman, Lita Yang, Bert Moons, Marian Verhelst, Boris Murmann:
An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS. 158-172 - Jinmook Lee, Changhyeon Kim, Sanghoon Kang, Dongjoo Shin, Sangyeob Kim, Hoi-Jun Yoo:
UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision. 173-185 - Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura:
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. 186-196 - Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, ChanYong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. 197-209 - Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl:
A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications. 210-216 - Avishek Biswas, Anantha P. Chandrakasan:
CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks. 217-230 - Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Mahmut E. Sinangil, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester:
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. 231-239 - Yue Chen, Yao-Hong Liu, Zhirui Zong, Johan Dijkhuis, Guido Dolmans, Robert Bogdan Staszewski, Masoud Babaie:
A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation. 240-252 - Saifullah Amir, Ronan A. R. van der Zee, Bram Nauta:
A Self-Oscillating Boosting Amplifier With Adaptive Soft Switching Control for Piezoelectric Transducers. 253-265 - Muhammad Abrar Akram, Wook Hong, In-Chul Hwang:
Capacitorless Self-Clocked All-Digital Low-Dropout Regulator. 266-276 - Moon Hyung Jang, Changuk Lee, Youngcheol Chae:
Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R Assisted Integrator. 277-287 - Dong-Ryeol Oh, Jong-In Kim, Dong-Shin Jo, Woo-Chul Kim, Dong-Jin Chang, Seung-Tak Ryu:
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. 288-297 - Albert Yen-Chih Chiou, Chih-Cheng Hsieh:
An ULV PWM CMOS Imager With Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting. 298-306 - Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu Wu:
A 232-1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring. 307-317
Volume 54, Number 2, February 2019
- Yuanching Lien, Eric A. M. Klumperink, Bernard Tenbroek, Jon Strange, Bram Nauta:
High-Linearity Bottom-Plate Mixing Technique With Switch Sharing for N-path Filters/Mixers. 323-335 - Yining Zhang, Meng Ni, Xiaohua Huang, Woogeun Rhee, Zhihua Wang:
A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation. 336-345 - Bo Zhao, Yong Lian, Ali M. Niknejad, Chun-Huat Heng:
A Low-Power Compact IEEE 802.15.6 Compatible Human Body Communication Transceiver With Digital Sigma-Delta IIR Mask Shaping. 346-357 - Zhiqiang Huang, Howard C. Luong:
An 82-107.6-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC. 358-367 - Chang Yang, Ping Gui:
85-110-GHz CMOS Magnetic-Free Nonreciprocal Components for Full-Duplex Transceivers. 368-379 - Kaizhe Guo, Yang Zhang, Patrick Reynaert:
A 0.53-THz Subharmonic Injection-Locked Phased Array With 63-µW Radiated Power in 40-nm CMOS. 380-391 - Shao-Yung Lu, Yu-Te Liao:
A Low-Power, Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18-µm CMOS. 392-402 - Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. 403-416 - Maoqiang Liu, Arthur H. M. van Roermund, Pieter Harpe:
A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver. 417-427 - Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun:
A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer. 428-440 - Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu:
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS. 441-451 - Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone:
A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET. 452-462 - Yeonho Lee, Yoonjae Choi, Junyoung Song, Sewook Hwang, Sang-Geun Bae, Jaehun Jun, Chulwoo Kim:
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. 463-475 - Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Xavier Aragonès, Enrique Barajas, Diego Mateo, Francisco V. Fernández, Montserrat Nafría:
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI. 476-488 - Chih-Lung Lin, Po-Chun Lai, Li-Wei Shih, Chia-Che Hung, Po-Cheng Lai, Tsu-Yuan Lin, Kuang-Hsiang Liu, Tsang-Hong Wang:
Compensation Pixel Circuit to Improve Image Quality for Mobile AMOLED Displays. 489-500 - Henna Ruokamo, Lauri Hallman, Juha Kostamovaara:
An 80×25 Pixel CMOS Single-Photon Sensor With Flexible On-Chip Time Gating of 40 Subarrays for Solid-State 3-D Range Imaging. 501-510 - Maximilian Marx, Stefan Rombach, Sebastian Nessler, Daniel De Dorigo, Yiannos Manoli:
A 141-µW High-Voltage MEMS Gyroscope Drive Interface Circuit Based on Flying Capacitors. 511-523 - Junwon Jeong, Seokhyeon Jeong, Dennis Sylvester, David T. Blaauw, Chulwoo Kim:
A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries. 524-537 - Jaeeun Jang, Jihee Lee, Kyoung-Rog Lee, Jiwon Lee, Minseo Kim, Yongsu Lee, Joonsung Bae, Hoi-Jun Yoo:
A Four-Camera VGA-Resolution Capsule Endoscope System With 80-Mb/s Body Channel Communication Transceiver and Sub-Centimeter Range Capsule Localization. 538-549 - Yunpeng Cai, Anand Savanth, Pranay Prabhat, James Myers, Alex S. Weddell, Tom J. Kazmierski:
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS. 550-559 - Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish:
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. 560-568 - Arvind Singh, Monodeep Kar, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering. 569-583 - Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Meng-Fan Chang:
A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation. 584-595 - Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino:
A 7T-SRAM With Data-Write Technique by Capacitive Coupling. 596-605
Volume 54, Number 3, March 2019
- Samuel Palermo, Nan Sun:
Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference. 611-612 - Teruki Someya, A. K. M. Mahfuzul Islam, Takayasu Sakurai, Makoto Takamiya:
An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage. 613-622 - Tzu-Fan Wu, Mike Shuo-Wei Chen:
A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing. 623-635 - Pieter Harpe:
A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter. 636-645 - Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. 646-658 - Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. 659-671 - Ashkan Roshan-Zamir, Takayuki Iwai, Yang-Hang Fan, Ankur Kumar, Hae-Woong Yang, Lee Sledjeski, John Hamilton, Soumya Chandramouli, Arlo Aude, Samuel Palermo:
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS. 672-684 - Dongwook Kim, Woo-Seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar Hanumolu:
A 15-Gb/s Sub-Baud-Rate Digital CDR. 685-695 - Fei Wang, Hua Wang:
A Noise Circulating Oscillator. 696-708 - Yun Yin, Yiting Zhu, Liang Xiong, Wei Luo, Bowen Chen, Tong Li, Na Yan, Hongtao Xu:
A Compact Transformer-Combined Polar/Quadrature Reconfigurable Digital Power Amplifier in 28-nm Logic LP CMOS. 709-719 - Sally Safwat Amin, Patrick P. Mercier:
A Fully Integrated Li-Ion-Compatible Hybrid Four-Level DC-DC Converter in 28-nm FDSOI. 720-732 - Yongjun Li, Mervin John, Yogesh Ramadass, Seth R. Sanders:
AC-Coupled Stacked Dual-Active-Bridge DC-DC Converter for Integrated Lithium-Ion Battery Power Delivery. 733-744 - Toshiki Nakamura, Yoshiaki Deguchi, Ken Takeuchi:
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories. 745-754 - Zhirui Zong, Peng Chen, Robert Bogdan Staszewski:
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications. 755-767 - Farooq Amin, Sanjay Raman, Kwang-Jin Koh:
Integrated Synthetic Fourth-Order $Q$ -Enhanced Bandpass Filter With High Dynamic Range, Tunable Frequency, and Fractional Bandwidth Control. 768-784 - Yao-Hong Liu, Vijaya Kumar Purushothaman, Christian Bachmann, Robert Bogdan Staszewski:
Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications. 785-795 - Hao Wu, David Murphy, Hooman Darabi:
A Harmonic-Selective Multi-Band Wireless Receiver With Digital Harmonic Rejection Calibration. 796-807 - Vivek Mangal, Peter R. Kinget:
A Wake-Up Receiver With a Multi-Stage Self-Mixer and With Enhanced Sensitivity When Using an Interferer as Local Oscillator. 808-820 - Kexu Sun, Guanhua Wang, Qing Zhang, Salam Elahmadi, Ping Gui:
A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS. 821-833 - Mostafa Gamal Ahmed, Tam N. Huynh, Christopher Williams, Yong Wang, Pavan Kumar Hanumolu, Alexander V. Rylyakov:
34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers. 834-844 - László Szilágyi, Jan Plíva, Ronny Henker, David Schoeniger, Jaroslaw P. Turkiewicz, Frank Ellinger:
A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS. 845-855 - Hui Jiang, Stoyan N. Nihtianov, Kofi A. A. Makinwa:
An Energy-Efficient 3.7-nV/ $\surd$ Hz Bridge Readout IC With a Stable Bridge Offset Compensation Scheme. 856-864 - Jin-Gyu Kang, Jeongpyo Park, Min-Gyu Jeong, Changsik Yoo:
A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range. 865-873 - Hesam Sadeghi Gougheri, Mehdi Kiani:
An Inductive Voltage-/Current-Mode Integrated Power Management With Seamless Mode Transition and Energy Recycling. 874-884 - Yongpan Liu, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Huazhong Yang:
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System. 885-895 - Hanwool Jeong, Se Hyeok Oh, Tae Woo Oh, Hoonki Kim, Changnam Park, Woojin Rim, Taejoong Song, Seong-Ook Jung:
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving. 896-906
Volume 54, Number 4, April 2019
- Ken Chang, Ken Takeuchi:
Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits. 911-913 - Cheng Wang, Xiang Yi, James Mawdsley, Mina Kim, Zhi Hu, Yaqing Zhang, Bradford Perkins, Ruonan Han:
Chip-Scale Molecular Clock. 914-926 - Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi:
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. 927-936 - Junhua Shen, Akira Shikata, Anping Liu, Baozhen Chen, Frederick Chalifoux:
A 12-Bit 31.1- $\mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance. 937-947 - Nandish Mehta, Johan H. Huijsing, Vladimir Stojanovic:
A 1-mW Class-AB Amplifier With -101 dB THD+N for High-Fidelity 16 $\Omega$ Headphones in 65-nm CMOS. 948-958 - Yeunhee Huh, Sung-Wan Hong, Gyu-Hyeong Cho:
A Hybrid Structure Dual-Path Step-Down Converter With 96.2% Peak Efficiency Using 250-m $\Omega$ Large-DCR Inductor. 959-967 - Zhaoming Ding, Xiong Zhou, Qiang Li:
A 0.5-1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator. 968-977 - Chen Cao, Yuya Shirakawa, Leyi Tan, Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Sung-Wook Jun, Tomohiko Kosugi, Satoshi Aoyama, Nobukazu Teranishi, Norimichi Tsumura, Shoji Kawahito:
A Time-Resolved NIR Lock-In Pixel CMOS Image Sensor With Background Cancelling Capability for Remote Heart Rate Detection. 978-991 - Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. 992-1002 - Jiacheng Pan, Asad A. Abidi, Wenlong Jiang, Dejan Markovic:
Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils. 1003-1016 - Aoyang Zhang, Mike Shuo-Wei Chen:
A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement. 1017-1028 - Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time. 1029-1038 - Nicolas Butzen, Michiel Steyaert:
Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched- Capacitor DC-DC Converters. 1039-1047 - Ziyun Li, Jingcheng Wang, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim:
A 1920 $\times$ 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching. 1048-1058 - Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. 1059-1073 - Sudhir Satpathy, Sanu K. Mathew, Raghavan Kumar, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram K. Krishnamurthy, Vivek De:
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS. 1074-1085 - Yuta Tsubouchi, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi:
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems. 1086-1095 - Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Lamine Benaissa, Edouard Deschaseaux, Edith Beigné, Karim Ben Chehida, Maria Lepecq, Mehdi Darouich, Fabrice Guellec, Thomas Dombek, Marc Duranton:
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing. 1096-1105 - Amr Suleiman, Zhengdong Zhang, Luca Carlone, Sertac Karaman, Vivienne Sze:
Navion: A 2-mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones. 1106-1119 - Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei:
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width. 1120-1136 - Chao Zhang, Scott Lindner, Ivan Michel Antolovic, Juan Mata Pavia, Martin Wolf, Edoardo Charbon:
A 30-frames/s, $252\times144$ SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming. 1137-1151 - Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang:
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell. 1152-1160 - Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. 1161-1172 - Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. 1173-1184 - Jaehyuk Lee, Kyoung-Rog Lee, Unsoo Ha, Ji-Hoon Kim, Kwonjoon Lee, Surin Gweon, Jaeeun Jang