default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDFPGA 2025: Monterey, CA, USA
- Andrew Putnam, Jing Li:
Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2025, Monterey, CA, USA, 27 February 2025 - 1 March 2025. ACM 2025, ISBN 979-8-4007-1396-5
Keynote I
- Steven K. Reinhardt
:
Architectures for AI. 1
Session: AI for FPGAs
- Jun Liu, Shulin Zeng, Li Ding, Widyadewi Soedarmadji, Hao Zhou, Zehao Wang, Jinhao Li, Jintao Li, Yadong Dai, Kairui Wen, Shan He, Yaqi Sun, Yu Wang, Guohao Dai:
FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs. 2-13 - Alireza Khataei, Kia Bazargan:
TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees. 14-24 - Olivia Weng, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas J. Fraser, Javier Mauricio Duarte, Ryan Kastner:
Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT. 25-35 - Oliver Cassidy, Marta Andronic, Samuel Coward, George A. Constantinides:
ReducedLUT: Table Decomposition with "Don't Care" Conditions. 36-42
Poster Session I
- Benjamin Hawks, Dennis Plotnikov, Nhan Tran, Karla Tame-Narvaez, Mohammad Mehdi Rahimifar, Hamza Ezzaoui Rahali, Audrey C. Therrien, Giuseppe Di Guglielmo, Javier Duarte, Vladimir Loncar:
wa-hls4ml and lui-gnn: A Benchmark and GNN based Surrogate Model for hls4ml Resource and Latency Estimation. 43 - Zifan He, Hersh Gupta, Huifeng Ke, Jason Cong:
InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs. 44 - Guoyu Li, Pengbo Zheng, Jian Weng, Enshan Yang:
DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP. 45 - Kaustubh Manohar Mhatre, Venkata Guru Prasanth Mulleti, Curt John Bansil, Endri Taka, Aman Arora:
Performance Analysis of GEMM Workloads on the AMD Versal Platform. 46 - Yun-Chen Yang, Hsuan-Wei Yu, Bo-Cheng Lai, Shih-Chieh Hsu, Mark S. Neubauer, Santosh Parajuli:
HiGTR: High-Performance FPGA Implementation of Complete GNN-based Trajectory Reconstruction for HEP. 47 - Edgard Cansio:
FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals. 48 - Tim Oberschulte, Enno Sievers, Holger Blume:
RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library. 49 - Suyash Vardhan Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin R. J. Downey, Jason D. Bakos:
Resource Scheduling for Real-Time Machine Learning. 50 - LingChi Yang, Chi-Jui Chen, Trung Le, Bo-Cheng Lai, Scott Hauck, Shih-Chieh Hsu:
BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA. 51 - Linus Jungemann, Bjarne Wintermann, Heinrich Riebler, Christian Plessl:
Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable Accelerators. 52 - Fan Cui, Youwei Xiao, Kexing Zhou, Yun Liang:
An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis. 53 - Hugo Le Blevec, Mathieu Léonardon, Stefan Weithoffer, Matthieu Arzel:
FPGA-Oriented Design Space Exploration of a Real-Time Road Scene Semantic Segmentation Deep Neural Network. 54 - Wenheng Ma, Xinhao Yang, Shulin Zeng, Tengxuan Liu, Libo Shen, Hongyi Wang, Shiyao Li, Jiewen Wang, Yuhan Zhang, Hao Guo, Jintao Li, Ziming Zhang, Zhenhua Zhu, Xuefei Ning, Tsung-Yi Ho, Guohao Dai, Yu Wang:
FMC-LLM: Enabling FPGAs for Efficient Batched Decoding of 70B+ LLMs with a Memory-Centric Streaming Architecture. 55
Session: CAD
- Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi:
Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. 56-66 - Wenwei Chen, Lin Ye, XiaoTong Zhao, Tongshu Ding, Jian Wang, Jinmei Lai:
An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing. 67-77 - Xianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang:
Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization. 78-84 - Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang:
TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. 85-91
Session: High-Level Synthesis I
- Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou:
ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. 92-102 - Suhail Basalama, Jason Cong:
Stream-HLS: Towards Automatic Dataflow Acceleration. 103-114
Session: Security
- Zhihan Xu, Tian Ye, Rajgopal Kannan, Viktor K. Prasanna:
FAST: FPGA Acceleration of Fully Homomorphic Encryption with Efficient Bootstrapping. 115-126 - Yang Yang, Rajgopal Kannan, Viktor K. Prasanna:
OLA: An FPGA-based Overlay Accelerator for Privacy Preserving Machine Learning with Homomorphic Encryption. 127-138 - Yu Feng, Zhaoqi Wang, Christophe Bobda:
CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers. 139-145
Keynote II
- John Wawrzynek:
Lessons from 40 Years of Reconfigurable Computing. 146
Session: Architecture
- Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne:
FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. 147-158 - Endri Taka, Ning-Chi Huang, Chi-Chih Chang, Kai-Chiang Wu, Aman Arora, Diana Marculescu:
Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration. 159-171 - Zhenyu Xu, Miaoxiang Yu, Yazhe Zhang, Jillian Cai, Qing Yang, Tao Wei:
Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines. 172-178
Poster Session II
- Archit Gajjar, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Rand Jean, Xia Sheng, Giacomo Pedretti, Paolo Faraboschi, Jim Ignowski, Luca Buonanno:
Enhancing FPGAs with Analog In-Memory Computing Macros. 179 - Andy Gean Ye, Anas Razzaq:
Measuring the Minimum Power Requirement of FPGA Architectural Specifications. 180 - Shixin Ji, Xingzhen Chen, Wei Zhang, Zhuoping Yang, Jinming Zhuang, Sarah Schultz, Yukai Song, Jingtong Hu, Alex K. Jones, Zheng Dong, Peipei Zhou:
Towards Accelerator Customization in Real-time Safety-critical Systems. 181 - Rui Li, Rajit Manohar:
PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis. 182 - Muhammad Ali Farooq, Abid Rafique, Suhaib A. Fahmy, Aman Arora:
High Throughput Low Latency Network Intrusion Detection on FPGAs: A Raw Packet Approach. 183 - Antian Wang, Weihang Tan, Zhenyu Xu, Tao Wei, Caiwen Ding, Keshab K. Parhi, Yingjie Lao:
HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With HiGh-Speed Fixed-Point Approximation. 184 - Nick Brown, Gabriel Rodriguez-Canal:
Seamless Acceleration of Fortran Intrinsics via AMD AI Engines. 185 - Ismail Erbas, Aporva Amarnath, Vikas Pandey, Karthik Swaminathan, Naigang Wang, Xavier Intes:
No Time to Lose: Enabling Real-Time Fluorescence Lifetime Imaging on Resource-constrained FPGAs Through Efficient Scheduling. 186
Session: High-Level Synthesis II
- Stéphane Pouget, Louis-Noël Pouchet, Jason Cong:
A Unified Framework for Automated Code Transformation and Pragma Insertion. 187-198 - Jianyi Cheng, Lianghui Wang, Zijian Jiang, Yungang Bao, Kan Shi:
Latency Insensitivity Testing for Dataflow HLS Designs. 199-210 - Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede:
Dynamic Loop Fusion in High-Level Synthesis. 211-222
Session: Applications
- Amirreza Movahedin, Lennart P. L. Landsmeer, Christos Strydis:
HUMA: Heterogeneous, Ultra Low-Latency Model Accelerator for The Virtual Brain on a Versal Adaptive SoC. 223-233 - Michael Lo, Mau-Chung Frank Chang, Jason Cong:
SAT-Accel: A Modern SAT Solver on a FPGA. 234-246 - Jun Yeon Won, Shinki Jeong, Seongkwan Lee, Minho Kang, Insu Yang, Jaemoo Choi:
FPGA-Only Implementation of MIPI C-PHY Receiver Using Blind Oversampling CDR for CMOS Image Sensors. 247-256
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-16 11:44 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
