default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 12
Volume 12, Number 1, January 1993
- Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu:
HS: a hierarchical search package for CAD data. 1-5 - Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga:
Variable ordering algorithms for ordered binary decision diagrams and their evaluation. 6-12 - Kwang-Ting Cheng
:
Redundancy removal for sequential circuits without reset states. 13-24 - Derek C. Wong, Giovanni De Micheli, Michael J. Flynn:
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. 25-46 - Carlo H. Séquin, Heloisa da Silva Facanha:
Corner-stitched tiles with curved boundaries [circuit layout]. 47-58 - Kjell O. Jeppson, Sven Christensson, Nils Hedenstierna:
Formal definitions of edge-based geometric design rules. 59-69 - Jason Cong, Moazzem Hossain, Naveed A. Sherwani:
A provably good multilayer topological planar routing algorithm in IC layout designs. 70-78 - Vwani P. Roychowdhury, Jonathan W. Greene, Abbas El Gamal:
Segmented channel routing. 79-95 - Shiuh-Wuu Lee:
A proposed method for determining a MOSFET gate electrode's bottom dimension and the on-state fringing capacitance. 96-101 - Benjamin R. Epstein, Martin H. Czigler, Steven R. Miller:
Fault detection and classification in linear integrated circuits: an application of discrimination analysis and hypothesis testing. 102-113 - Niraj K. Jha, Abha Ahuja:
Easily testable nonrestoring and restoring gate-level cellular array dividers. 114-123 - Pinaki Mazumder, Jih-Shyr Yih:
A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. 124-136 - Fadi Maamari, Janusz Rajski:
The dynamic reduction of fault simulation. 137-148 - Wen-Ben Jone, Patrick H. Madden:
Multiple fault testing using minimal single fault test set for fanout-free circuits. 149-157 - Hervé J. Touati, Robert K. Brayton:
Computing the initial states of retimed circuits. 157-162 - Alan Rotman, Ran Ginosar:
Control unit synthesis from a high-level language. 162-167 - Kyunrak Chong, Sartaj Sahni:
Minimizing total wire length by flipping modules. 167-175 - Jan-Ming Ho, Atsushi Suzuki, Majid Sarrafzadeh:
An exact algorithm for single-layer wire length minimization. 175-180 - Nils Hedenstierna, Kjell O. Jeppson:
Comments on 'A module generator for optimized CMOS buffers'. 180-181
Volume 12, Number 2, February 1993
- Hsi-Chuan Chen, David Hung-Chang Du, Li-Ren Liu:
Critical path selection for performance optimization. 185-195 - Hsi-Chuan Chen, David Hung-Chang Du:
Path sensitization in critical path problem [logic circuit design]. 196-207 - Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli:
Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits. 208-224 - Richard Burch, Ping Yang, Paul F. Cox, Kartikeya Mayaram:
A new matrix solution technique for general circuit simulation. 225-241 - Ren-Song Tsay:
An exact zero-skew clock routing algorithm. 242-249 - Bin Zhu, Xinya Wu, Wenjun Zhuang, Wai-Kai Chen:
A new one-and-half layer channel routing algorithm based on assigning resources for CMOS gate array. 250-264 - Nils Hedenstierna, Kjell O. Jeppson:
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits. 265-272 - Keumog Ahn, Sartaj Sahni:
Constrained via minimization. 273-282 - D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas:
The CDB/HCDB semiconductor wafer representation server. 283-295 - ShaoWei Pan, Yu Hen Hu:
PYFS-a statistical optimization method for integrated circuit yield enhancement. 296-309 - Farid N. Najm:
Transition density: a new measure of activity in digital circuits. 310-323 - Ahmadreza Rofougaran, Asad A. Abidi:
A table lookup FET model for accurate analog circuit simulation. 324-335 - Wen-Ben Jone:
Defect level estimation of circuit testing using sequential statistical analysis. 336-348 - Dwight D. Hill, Nam Sung Woo:
The benefits of flexibility in lookup table-based FPGAs. 349-353 - Wolfgang Rülling, Thomas Schilz:
A new method for hierarchical compaction [VLSI]. 353-360
Volume 12, Number 3, March 1993
- Maurizio Damiani, Giovanni De Micheli:
Don't care set specifications in combinational and synchronous logic circuits. 365-388 - Tai A. Ly, Jack T. Mowchenko:
Applying simulated evolution to high level synthesis. 389-409 - Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. 410-424 - Giovanni Ghione, Fabio Filicori:
A computationally efficient unified approach to the numerical analysis of the sensitivity and noise of semiconductor devices. 425-438 - Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr.:
Universal MOSFET hole mobility degradation models for circuit simulation. 439-445 - Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham:
VLSI logic and fault simulation on general-purpose parallel computers. 446-460
Volume 12, Number 4, April 1993
- Donald A. Joy, Maciej J. Ciesielski:
Clock period minimization with wave pipelining. 461-472 - Anurag P. Gupta, William P. Birmingham, Daniel P. Siewiorek:
Automating the design of computer systems. 473-487 - Gwo-Haur Hwang, Wen-Zen Shen:
Restructuring and logic minimization for testable PLA. 488-496 - Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli:
Constraint-based channel routing for analog and mixed analog/digital circuits. 497-510 - Jozef C. Mitros:
Empirical model of MOSFET breakdown voltages. 511-515 - Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj:
Switch-level timing simulation of bipolar ECL circuits. 516-530 - Janusz Rajski, Jerzy Tyszer:
Test responses compaction in accumulators with rotate carry adders. 531-539 - Geetani Edirisooriya, John P. Robinson:
Test generation to minimize error masking. 540-549 - Hassan A. Farhat, Steven G. From:
A beta model for estimating the testability and coverage distributions of a VLSI circuit. 550-554
Volume 12, Number 5, May 1993
- Krishna P. Belkhale, Randall J. Brouwer, Prithviraj Banerjee:
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms. 557-567 - Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. 568-578 - Abhijit Ghosh, Srinivas Devadas, A. Richard Newton:
Sequential test generation and synthesis for testability at the register-transfer and logic levels. 579-598 - Frédéric Mailhot, Giovanni De Micheli:
Algorithms for technology mapping based on binary decision diagrams and on Boolean operations. 599-620 - Tsutomu Sasao:
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions. 621-632 - Michael C. McFarland:
Formal verification of sequential hardware: a tutorial. 633-654 - Liliana Díaz-Olavarrieta, K. Illanko, Safwat G. Zaky:
Goal-oriented decomposition of switching functions. 655-665 - Hamid Z. Fardi:
Simulation and modeling of p-n-p-n optical switches. 666-671 - Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska:
Stepwise equivalent conductance circuit simulation technique. 672-683 - Wolfgang Kunz, Dhiraj K. Pradhan:
Accelerated dynamic learning for test pattern generation in combinational circuits. 684-694 - Adit D. Singh, C. Mani Krishna:
On optimizing VLSI testing for product quality using die-yield prediction. 695-709 - Donald L. Dietmeyer:
Generating minimal covers of symmetric functions. 710-713 - Martine D. F. Schlag, Pak K. Chan, Jackson Kong:
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. 713-722 - Srinivas Devadas:
Comparing two-level and ordered binary decision diagram representations of logic functions. 722-723 - Jason Cong, Bryan Preas, C. L. Liu:
Physical models and efficient algorithms for over-the-cell routing in standard cell design. 723-734 - O. Y. Song, Bong-Hee Park, Prem R. Menon:
Divergence and scheduling in functional level concurrent fault simulation. 734-736
Volume 12, Number 6, June 1993
- Ruchir Puri, Jun Gu:
An efficient algorithm to search for minimal closed covers in sequential machines. 737-745 - Meinhard Paffrath, Karl Steger:
Method of temporary coordinate domains for moving boundary value problems [semiconductor processing simulation]. 746-756 - Yang Cai, Martin D. F. Wong:
On minimizing the number of L-shaped channels in building-block layout [VLSI]. 757-769 - Nobuo Funabiki, Yoshiyasu Takefuji:
A neural network approach to topological via-minimization problems. 770-779 - Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh:
Utilization of vacant terminals for improved over-the-cell channel routing. 780-792 - Kyunrak Chong, Sartaj Sahni:
Optimal realizations of floorplans [VLSI layout]. 793-801 - Thomas Lengauer, Rolf Müller:
Robust and accurate hierarchical floorplanning with integrated global wiring. 802-809 - Ming-Jiang Zhou, Herbert De Smet, Anita De Bruycker, André Van Calster:
A 2-D boundary element method approach to the simulation of DMOS transistors. 810-816 - Khalid Rahmat, Jacob K. White, Dimitri A. Antoniadis:
Computation of drain and substrate currents in ultra-short-channel nMOSFET's using the hydrodynamic model. 817-824 - Colin C. McAndrew, Bijan K. Bhattacharyya, Omar Wing:
A Cinfinity-continuous depletion capacitance model. 825-828 - Lawrence P. Huang, Randal E. Bryant:
Intractability in linear switch-level simulation. 829-836 - Venkata S. Rangavajjhala, Bharat L. Bhuva, Sherra E. Kerns:
Statistical degradation analysis of digital CMOS IC's. 837-844 - Peter Saviz, Omar Wing:
Circuit simulation by hierarchical waveform relaxation. 845-860 - Robert C. Melville, Ljiljana Trajkovic, San-Chin Fang, Layne T. Watson:
Artificial parameter homotopy methods for the DC operating point problem. 861-877 - Niraj K. Jha, Sying-Jyan Wang:
Design and synthesis of self-checking VLSI circuits. 878-887 - Marcel Jacomet, Walter Guggenbühl:
Layout-dependent fault analysis and test synthesis for CMOS circuits. 888-899 - Neven Orhanovic, Paul Wang, Vijay K. Tripathi:
Time-domain simulation of uniform and nonuniform multiconductor lossy lines by the method of characteristics. 900-904 - Anastasios Vergis:
On the multiple-fault testability of generalized counters. 905-909 - Noriyuki Iwamuro, Saburo Tagami:
Two-dimensional power device simulator considering an integral external circuit equation. 909-912
Volume 12, Number 7, July 1993
- Pierre Abouzeid, Belgacem Babba, Michel Crastes de Paulet, Gabriele Saucier:
Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs. 913-925 - Cheng-Tsung Hwang, Yu-Chin Hsu:
Zone scheduling. 926-934 - Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi:
Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration. 935-945 - Stella N. Batalama, Dimitrios A. Pados, Theodore S. Papatheodorou:
A heuristic single-row router minimizing interstreet crossings. 946-955 - Stephen T. Frezza, Steven P. Levitan:
SPAR: a schematic place and route system. 956-973 - Tai-Tsung Ho:
A density-based greedy router. 974-981 - Mahesh S. Sharma, Narain D. Arora:
OPTIMA: A nonlinear model parameter extraction program with statistical confidence region algorithms. 982-987 - Shigetaka Kumashiro, Ronald A. Rohrer, Andrzej J. Strojwas:
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures. 988-996 - Denis Martin, Nicholas C. Rumin:
Delay prediction from resistance-capacitance models of general MOS circuits. 997-1003 - Lean Peterson, Sven Marrisson:
The design and implementation of a concurrent circuit simulation program for multicomputers. 1004-1014 - Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler:
A transitive closure algorithm for test generation. 1015-1028 - Hyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers:
Hierarchical test pattern generation: a cost model and implementation. 1029-1039 - Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
COMPACTEST: a method to generate compact test sets for combinational circuits. 1040-1049 - Irith Pomeranz, Sudhakar M. Reddy:
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. 1050-1058 - Kuo-En Chang:
Efficient algorithms of wiring channels with movable terminals. 1059-1063 - Lori E. Lucke, Keshab K. Parhi:
Data-flow transformations for critical path time reduction in high-level DSP synthesis. 1063-1068 - Slawomir Pilarski, Tiko Kameda, André Ivanov:
Sequential faults and aliasing. 1068-1074
Volume 12, Number 8, August 1993
- Andrea Casotto, Alberto L. Sangiovanni-Vincentelli:
Automated design management using traces. 1077-1095 - Per Andersson, Lars H. Philipson:
Interaction semantics of a symbolic layout editor for parameterized modules. 1096-1106 - John A. Nestor, Ganesh Krishnamoorthy:
SALSA: a new approach to scheduling with timing constraints. 1107-1122 - Irith Pomeranz, Kwang-Ting Cheng:
STOIC: state assignment based on output/input functions. 1123-1131 - Karem A. Sakallah, Trevor N. Mudge, Timothy M. Burks, Edward S. Davidson:
Synchronization of pipelines. 1132-1146 - Wing Ning Li, Andrew Lim, Prathima Agrawal, Sartaj Sahni:
On the circuit implementation problem. 1147-1156 - Jason Cong, Andrew B. Kahng, Gabriel Robins:
Matching-based methods for high-performance clock routing. 1157-1169 - Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne:
Post-layout timing simulation of CMOS circuits. 1170-1177 - Jack A. Feldman, Israel A. Wagner, Shmuel Wimer:
An efficient algorithm for some multirow layout problems. 1178-1185 - Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli:
Area routing for analog layout. 1186-1197 - D. Sreenivasa Rao, Fadi J. Kurdahi:
On clustering for maximal regularity extraction. 1198-1208 - Chih-Chuan Lin, Mark E. Law, Rex E. Lowther:
Automatic grid refinement and higher order flux discretization for diffusion modeling. 1209-1216 - Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer:
Delay-fault test generation and synthesis for testability under a standard scan design methodology. 1217-1231 - Jacob Savir, Srinivas Patil:
Scan-based transition test. 1232-1241 - M. A. Styblinski, Min Huang:
Drift reliability optimization in IC design: generalized formulation and practical examples. 1242-1252
Volume 12, Number 9, September 1993
- Pinaki Mazumder, Jih-Shyr Yih:
Restructuring of square processor arrays by built-in self-repair circuit. 1255-1265 - Catherine H. Gebotys, Mohamed I. Elmasry:
Global optimization approach for architectural synthesis. 1266-1278 - Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
PLS: a scheduler for pipeline synthesis. 1279-1286 - Elke A. Rundensteiner, Daniel D. Gajski, Lubomir Bic:
Component synthesis from functional descriptions. 1287-1299 - D. I. Carson:
On O(p2) algorithms for planarization. 1300-1302 - Sy-Yen Kuo:
YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias. 1303-1311 - Sundarar Mohan, Pinaki Mazumder:
Wolverines: standard cell placement on a network of workstations. 1312-1326 - Antonio Abramo, Franco Venturi, Enrico Sangiorgi, Jack M. Higman, Bruno Riccò:
A numerical method to compute isotropic band models from anisotropic semiconductor band structures. 1327-1336 - Shan-Ping Chin, Ching-Yuan Wu:
A new grid-generation method for 2-D simulation of devices with nonplanar semiconductor surface. 1337-1344 - Edward W. Scheckler, Nelson N. Tam, Anton K. Pfau, Andrew R. Neureuther:
An efficient volume-removal algorithm for practical three-dimensional lithography simulation with experimental verification. 1345-1356 - J. Will Specks, Walter L. Engl:
Computer-aided design and scaling of deep submicron CMOS. 1357-1367 - David T. Zweidinger, Sang-Gug Lee, Robert M. Fox:
Compact modeling of BJT self-heating in SPICE. 1368-1375 - Valentino Liberali, Victor da Fonte Dias, M. Ciapponi, Franco Maloberti:
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters. 1376-1386 - Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang:
ILLIADS: a fast timing and reliability simulator for digital MOS circuits. 1387-1402 - Marcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò:
Fault simulation of parametric bridging faults in CMOS IC's. 1403-1410 - Peter M. Maurer:
The shadow algorithm: a scheduling technique for both compiled and interpreted simulation. 1411-1413 - Ohyoung Song, Premachandran R. Menon:
Acceleration of trace-based fault simulation of combinational circuits. 1413-1419 - Ohyoung Song, Premachandran R. Menon:
3-valued trace-based fault simulation of synchronous sequential circuits. 1419-1424
Volume 12, Number 10, October 1993
- Wim De Pauw:
Multitrees with internal storage. 1428-1436 - In-Cheol Park, Chong-Min Kyung:
FAMOS: an efficient scheduling algorithm for high-level synthesis. 1437-1448 - Ruchir Puri, Jun Gu:
Microword length minimization in microprogrammed controller synthesis. 1449-1457 - Yosinori Watanabe, Robert K. Brayton:
Heuristic minimization of multiple-valued relations. 1458-1472 - Steven T. Healey:
An improved model for solving the optimal placement for river-routing problem. 1473-1480 - Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin:
An adaptive timing-driven placement for high performance VLSIs. 1488-1498 - Datong Chen, Satoshi Sugino, Zhiping Yu, Robert W. Dutton:
Modeling of the charge balance condition on floating gates and simulation of EEPROMs. 1499-1502 - Ferenc Kovács, Gábor Hosszú:
A proposed method for dynamic fitting of MOS model parameters. 1503-1507 - Kenji Harafuji, Akio Misaka, Noboru Nomura, Masahiro Kawamoto, Hirohiko Yamashita:
A novel hierarchical approach for proximity effect correction in electron beam lithography. 1508-1514 - Arlynn W. Smith, Ajeet Rohatgi:
Non-isothermal extension of the Scharfetter-Gummel technique for hot carrier transport in heterostructure simulations. 1515-1523 - Robert H. Tu, Elyse Rosenbaum, Wilson Y. Chan, Chester C. Li, Eric R. Minami, Khandker N. Quader, Ping K. Ko, Chenming Hu:
Berkeley reliability tools-BERT. 1524-1534 - He Yie, Teng Zhimeng:
Nonoscillatory streamline upwind formulations for drift-diffusion equation. 1535-1541 - C. Patrick Yue, Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr.:
Improved universal MOSFET electron mobility degradation models for circuit simulation. 1542-1546 - Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich:
Clock suppression techniques for synchronous circuits. 1547-1556 - Maria Cristina Vecchi, Massimo Rudan, Giovanni Soncini:
Numerical simulation of optical devices. 1557-1569 - Jacek Wojciechowski, Jirí Vlach:
Ellipsoidal method for design centering and yield estimation. 1570-1579 - Thyagaraju R. Damarla, Avinash Sathaye:
Applications of one-dimensional cellular automata and linear feedback shift registers for pseudo-exhaustive testing. 1580-1591 - Lih-Der Chang, Pei-Yung Hsiao, Jin-Tai Yan, Paul-Waie Shew:
A robust over-the-cell channel router. 1592-1599 - Kwang-Ting Cheng, Hi-Keung Tony Ma:
On the over-specification problem in sequential ATPG algorithms. 1599-1604 - Hideo Fujiwara, Akihiro Yamamoto:
Parity-scan design to reduce the cost of test application. 1604-1611 - Yu Hen Hu, ShaoWei Pan:
SaPOSM: an optimization method applied to parameter extraction of MOSFET models. 1481-1487 - Manjote S. Haworth, William P. Birmingham, Daniel E. Haworth:
Optimal part selection. 1611-1617 - Olgierd A. Palusinski, Dongjin Lee, Lozios Vakanas:
Comments on 'Simulation of lossless symmetrical three conductor systems' by W. Guggenbuhl et al. 1617-1619
Volume 12, Number 11, November 1993
- Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang:
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. 1621-1634 - Daniel Brand:
Exhaustive simulation need not require an exponential number of tests. 1635-1641 - Gabriele Saucier, Pierre Abouzeid:
Lexicographical expressions of Boolean functions with application to multilevel synthesis. 1642-1654 - Ingo Schäfer, Marek A. Perkowski:
Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's. 1655-1664 - Andrew Lumsdaine, Luís Miguel Silveira, Jacob K. White:
Massively parallel simulation algorithms for grid-based analog signal processors. 1665-1678 - Doowon Paik, Sartaj Sahni:
Optimal folding of bit sliced stacks. 1679-1685 - Chan-Ik Park, Yun-Bo Park:
An efficient algorithm for VLSI network partitioning problem using a cost function with balancing factor. 1686-1694 - Kaushik Roy:
A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues. 1695-1705 - Antonio Gnudi, Davide Ventura, Giorgio Baccarani:
Modeling impact ionization in a BJT by means of spherical harmonics expansion of the Boltzmann transport equation. 1706-1713 - Nancy Hitschfeld-Kahler, Paolo Conti, Wolfgang Fichtner:
Mixed element trees: a generalization of modified octrees for the generation of meshes for the simulation of complex 3-D semiconductor device structures. 1714-1725 - Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang:
Algorithms for transient three-dimensional mixed-level circuit and device simulation. 1726-1733 - Peter W. Rambo, Jacques Denavit:
Time stability of Monte Carlo device simulation. 1734-1741 - Alexei D. Sadovnikov, David J. Roulston:
Quasi-three-dimensional modeling of bipolar transistor characteristics. 1742-1748 - Motoaki Tanizawa, Mikio Ikeda, Norihiko Kotani, Katsuhiro Tsukamoto, Kazuo Horie:
A complete substrate current model including band-to-band tunneling current for circuit simulation. 1749-1757 - Tahui Wang, Sheng-Jyh Wu, Chimoon Huang:
Device and circuit simulation of anomalous DX trap effects in DCFL and SCFL HEMT inverters. 1758-1761 - Gih-Guang Hung, Yen-Cheng Wen, Kyle A. Gallivan, Resve A. Saleh:
Improving the performance of parallel relaxation-based circuit simulators. 1762-1774 - M. A. Styblinski, Syed A. Aftab:
Combination of interpolation and self-organizing approximation techniques-a new approach to circuit performance modeling. 1775-1785 - Rudi C. Vankemmel, Wim Schoenmaker, Rudi Cartuyvels, Kristin M. De Meyer:
Scaling considerations of the constitutive equations in a 2-D finite element heterojunction simulator PRISM. 1786-1797 - Dong H. Xie, Michel S. Nakhla:
Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations. 1798-1811
Volume 12, Number 12, December 1993
- Chuan-Jin Shi, Janusz A. Brzozswski:
An efficient algorithm for constrained encoding and its applications. 1813-1826 - Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A stochastic model to predict the routability of field-programmable gate arrays. 1827-1838 - Chun-Yeh Liu, Kewal K. Saluja:
An efficient algorithm for bipartite PLA folding. 1839-1847 - Yang Cai, Martin D. F. Wong:
Efficient via shifting algorithms in channel compaction. 1848-1857 - Gary K. H. Yeap, Majid Sarrafzadeh:
A unified approach to floorplan sizing and enumeration. 1858-1867 - Peter Feldmann, Stephen W. Director:
Integrated circuit quality optimization using surface integrals. 1868-1879 - Mark G. Graham, John J. Paulos:
Interpolation of MOSFET table data in width, length, and temperature. 1880-1884 - Sundarar Mohan, Pinaki Mazumder:
Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors. 1885-1896 - Peter J. Wright, Yung-Che Albert Shih:
Capacitance of top leads metal - comparison between formula, simulation, and experiment. 1897-1902 - Mary L. Bailey:
A delay-based model for circuit parallelism. 1903-1912 - Srinivas Devadas, Kurt Keutzer, Sharad Malik:
Computation of floating mode delay in combinational circuits: theory and algorithms. 1913-1923 - Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Computation of floating mode delay in combinational circuits: practice and implementation. 1924-1936 - Ahmet N. Parlakbilek, David M. Lewis:
A multiple-strength multiple-delay compiled-code logic simulator. 1937-1946 - Filip Van Aelten, Jonathan Allen, Srinivas Devadas:
Verification of relations between synchronous machines. 1947-1959 - Chung-Hsing Chen, Daniel G. Saab:
A novel behavioral testability measure. 1960-1970 - Kwang-Ting Cheng:
Transition fault testing for sequential circuits. 1971-1983
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-31 20:18 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
