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ORCIDChen Dong 0003
Person information
- affiliation: University of Illinois, Urbana-Champaign, Department of Electrical and Computer Engineering, IL, USA
- affiliation: Purdue University at Indianapolis, Department of Electrical and Computer Engineering, IN, USA
Other persons with the same name
- Chen Dong — disambiguation page
- Chen Dong 0001
![[0000-0002-3443-1453]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-3443-1453")
— Beijing University of Posts and Telecommunications, China (and 1 more) - Chen Dong 0002 — Fuzhou University, College of Mathematics and Computer Science, China
- Chen Dong 0004 — Adobe, Inc., San Jose, CA , USA
- Chen Dong 0005 — Nanjing University, School of Electronic Science and Engineering, China
- Chen Dong 0006 — Lanzhou University of Technology, School of Computer and Communication, China
- Chen Dong 0007 — Guangdong Commerce and Industry College, College of Electronic and Information Engineering, China
- Chen Dong 0008 — Zhejiang Wanli University, School of Computer Science And Information Technology, China
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2010 – 2019
- 2012
[j5]Lu Wan, Chen Dong, Deming Chen:
A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance. Int. J. Reconfigurable Comput. 2012: 163542:1-163542:17 (2012)- 2011
- [c9]Chi-Chen Peng, Chen Dong, Deming Chen:
SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power. ASP-DAC 2011: 388-393 - [c8]Chen Dong, Chen Chen, Subhasish Mitra, Deming Chen:
Architecture and performance evaluation of 3D CMOS-NEM FPGA. SLIP 2011: 1-8 - 2010
- [b1]Chen Dong:
Architecture and CAD for Nanoscale and Three-Dimensional FPGA. University of Illinois Urbana-Champaign, USA, 2010 - [j4]Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng:
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1709-1722 (2010) - [j3]Gregory Lucas, Chen Dong, Deming Chen:
Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1818-1822 (2010) - [c7]Ying-Yu Chen, Chen Dong, Deming Chen:
Clock tree synthesis under aggressive buffer insertion. DAC 2010: 86-89 - [c6]Gregory Lucas, Chen Dong, Deming Chen:
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis. FPGA 2010: 177-180
2000 – 2009
- 2009
- [j2]Scott Chilstedt, Chen Dong, Deming Chen:
Design and Evaluation of a Carbon Nanotube-Based Programmable Architecture. Int. J. Parallel Program. 37(4): 389-416 (2009) - [c5]Chen Dong, Scott Chilstedt, Deming Chen:
Reconfigurable circuit design with nanomaterials. DATE 2009: 442-447 - [c4]Chen Dong, Scott Chilstedt, Deming Chen:
FPCNA: a field programmable carbon nanotube array. FPGA 2009: 161-170 - [c3]Chen Dong, Scott Chilstedt, Deming Chen:
Variation Aware Routing for Three-Dimensional FPGAs. ISVLSI 2009: 298-303 - 2007
- [j1]Chen Dong, Deming Chen, S. Haruehanroengra, Wei Wang:
3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2489-2501 (2007) - [c2]Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei Wang:
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture. ICCAD 2007: 758-764 - 2006
- [c1]Chen Dong, S. Haruehanroengra, Wei Wang:
Exploring carbon nanotubes and NiSi nanowires as on-chip interconnections. ISCAS 2006
Coauthor Index
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