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ORCIDPuneet Gupta 0001
Person information
- affiliation: University of California Los Angeles, Department of Electrical Engineering, CA, USA
Other persons with the same name
- Puneet Gupta — disambiguation page
- Puneet Gupta 0002
![[0000-0003-3586-9315]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-3586-9315")
— Indian Institute of Technology Kanpur, India
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2020 – today
- 2025
[j57]Egor Glukhov, Tianmu Li, Vaibhav Gupta, Puneet Gupta:
Learned Approximate Computing: Algorithm Hardware Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(3): 858-866 (2025)- [j56]Zhichao Chen, Ali H. Hassan, Rhesa Ramadhan, Yingheng Li, Chih-Kong Ken Yang, Sudhakar Pamarti, Puneet Gupta:
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation. IEEE Trans. Very Large Scale Integr. Syst. 33(1): 102-113 (2025) - [i13]Alexander Graening, Jonti Talukdar, Saptadeep Pal, Krishnendu Chakrabarty, Puneet Gupta:
CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems. CoRR abs/2503.15753 (2025) - [i12]Shurui Li, Puneet Gupta:
CIMPool: Scalable Neural Network Acceleration for Compute-In-Memory using Weight Pools. CoRR abs/2503.22044 (2025) - 2024
- [j55]Irina Alam, Puneet Gupta:
Achieving DRAM-Like PCM by Trading Off Capacity for Latency. IEEE Trans. Computers 73(4): 1180-1189 (2024) - [j54]Wojciech Romaszkan, Jiyue Yang, Alexander Graening, Vinod Kurian Jacob, Jishnu Sen, Sudhakar Pamarti, Puneet Gupta:
SCIMITAR: Stochastic Computing In-Memory In-Situ Tracking ARchitecture for Event-Based Cameras. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 4214-4225 (2024) - [j53]Newsha Ardalani, Saptadeep Pal, Puneet Gupta:
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems. ACM Trans. Design Autom. Electr. Syst. 29(2): 30:1-30:20 (2024) - [c101]Soumitra Pal, Jiyue Yang, Stephen Bauer, Puneet Gupta, Sudhakar Pamarti:
Novel Energy-Efficient and Latency-Improved PVT Tolerant Read Scheme for SRAM Design in Video Processing and Machine Learning Applications. MWSCAS 2024: 460-463 - [c100]Ali H. Hassan, Puneet Gupta, Sudhakar Pamarti, Chih-Kong Ken Yang:
Cryogenic Alternative: CMOS Versus Dynamic-Based Logic. MWSCAS 2024: 1007-1010 - [c99]Jiyue Yang, Alexander Graening, Wojciech Romaszkan, Vinod K. Jacob, Puneet Gupta, Sudhakar Pamarti:
A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j52]Irina Alam, Tianmu Li, Sean Brock, Puneet Gupta:
DRDebug: Automated Design Rule Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 606-615 (2023) - [j51]Tianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta:
REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4423-4435 (2023) - [c98]Alexander Graening, Saptadeep Pal, Puneet Gupta:
Chiplets: How Small is too Small? DAC 2023: 1-6 - [c97]Shurui Li, Hangbo Yang, Chee Wei Wong, Volker J. Sorger, Puneet Gupta:
PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator. HPCA 2023: 15-28 - [c96]Shurui Li, Hangbo Yang, Chee Wei Wong, Volker J. Sorger, Puneet Gupta:
ReFOCUS: Reusing Light for Efficient Fourier Optics-Based Photonic Neural Network Accelerator. MICRO 2023: 569-583 - [i11]Tianmu Li, Shurui Li, Puneet Gupta:
Training Neural Networks for Execution on Approximate Hardware. CoRR abs/2304.04125 (2023) - [i10]Ravit Sharma, Wojciech Romaszkan, Feiqian Zhu, Puneet Gupta, Ankur Mehta:
Cost-Driven Hardware-Software Co-Optimization of Machine Learning Pipelines. CoRR abs/2310.07940 (2023) - 2022
- [j50]Wojciech Romaszkan, Tianmu Li, Puneet Gupta:
SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4169-4180 (2022) - [c95]Vaibhav Gupta, Tianmu Li, Puneet Gupta:
LAC: Learned Approximate Computing. DATE 2022: 1169-1172 - [c94]Irina Alam, Puneet Gupta:
COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors. DSN 2022: 124-136 - [c93]Shurui Li, Puneet Gupta:
Bit-serial Weight Pools: Compression and Arbitrary Precision Execution of Neural Networks on Resource Constrained Processors. MLSys 2022 - [i9]Shurui Li, Puneet Gupta:
Bit-serial Weight Pools: Compression and Arbitrary Precision Execution of Neural Networks on Resource Constrained Processors. CoRR abs/2201.11651 (2022) - [i8]Newsha Ardalani, Saptadeep Pal, Puneet Gupta:
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems. CoRR abs/2211.03309 (2022) - [i7]Shurui Li, Hangbo Yang, Chee Wei Wong, Volker J. Sorger, Puneet Gupta:
PhotoFourier: A Photonic Joint Transform Correlator-Based Neural Network Accelerator. CoRR abs/2211.05276 (2022) - 2021
- [j49]Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Puneet Gupta:
Adaptive MRAM Write and Read with MTJ Variation Monitor. IEEE Trans. Emerg. Top. Comput. 9(1): 402-413 (2021) - [c92]Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta:
Designing a 2048-Chiplet, 14336-Core Waferscale Processor. DAC 2021: 1183-1188 - [c91]Tianmu Li, Wojciech Romaszkan, Sudhakar Pamarti, Puneet Gupta:
GEO: Generation and Execution Optimized Stochastic Computing Accelerator for Neural Networks. DATE 2021: 689-694 - [c90]Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L. Wang, Sudhakar Pamarti:
A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. ESSCIRC 2021: 115-118 - [c89]Jiyue Yang, Di Wu, Albert Lee, Seyed Armin Razavi, Puneet Gupta, Kang L. Wang, Sudhakar Pamarti:
A Calibration-Free In-Memory True Random Number Generator Using Voltage-Controlled MRAM. ESSDERC 2021: 115-118 - [i6]Shurui Li, Wojciech Romaszkan, Alexander Graening, Puneet Gupta:
SWIS - Shared Weight bIt Sparsity for Efficient Neural Network Acceleration. CoRR abs/2103.01308 (2021) - [i5]Zibo Hu, Shurui Li, Russell L. T. Schwartz, Maria Solyanik-Gorgone, Mario Miscuglio, Puneet Gupta, Volker J. Sorger:
Batch Processing and Data Streaming Fourier-based Convolutional Neural Network Accelerator. CoRR abs/2112.12297 (2021) - 2020
- [j48]Wei-Che Wang, Yizhang Wu, Puneet Gupta:
Reverse Engineering for 2.5-D Split Manufactured ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3128-3133 (2020) - [j47]Wojciech Romaszkan, Tianmu Li, Puneet Gupta:
3PXNet: Pruned-Permuted-Packed XNOR Networks for Edge Machine Learning. ACM Trans. Embed. Comput. Syst. 19(1): 5:1-5:23 (2020) - [j46]Wei-Che Wang, Yair Yona, Yizhang Wu, Suhas N. Diggavi, Puneet Gupta:
SLATE: A Secure Lightweight Entity Authentication Hardware Primitive. IEEE Trans. Inf. Forensics Secur. 15: 276-285 (2020) - [j45]Saptadeep Pal, Daniel Petrisko, Rakesh Kumar, Puneet Gupta:
Design Space Exploration for Chiplet-Assembly-Based Processors. IEEE Trans. Very Large Scale Integr. Syst. 28(4): 1062-1073 (2020) - [c88]Wojciech Romaszkan, Tianmu Li, Tristan Melton, Sudhakar Pamarti, Puneet Gupta:
ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic Computing. DATE 2020: 768-773 - [c87]Irina Alam, Puneet Gupta:
SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge. MEMSYS 2020: 10-22 - [c86]Saptadeep Pal, Puneet Gupta:
Pathfinding for 2.5D interconnect technologies. SLIP 2020: 3 - [i4]Shurui Li, Mario Miscuglio, Volker J. Sorger, Puneet Gupta:
Channel Tiling for Improved Performance and Accuracy of Optical Neural Network Accelerators. CoRR abs/2011.07391 (2020)
2010 – 2019
- 2019
- [j44]Rajesh K. Gupta, Subhasish Mitra, Puneet Gupta:
Variability Expeditions: A Retrospective. IEEE Des. Test 36(1): 65-67 (2019) - [j43]Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David W. Nellans, Puneet Gupta:
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training. IEEE Micro 39(5): 91-101 (2019) - [j42]Clayton Schoeny, Frederic Sala, Mark Gottscho, Irina Alam, Puneet Gupta, Lara Dolecek:
Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories. IEEE Trans. Inf. Theory 65(10): 6146-6159 (2019) - [c85]Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar:
Architecting Waferscale Processors - A GPU Case Study. HPCA 2019: 250-263 - [c84]Irina Alam, Saptadeep Pal, Puneet Gupta:
Compression with multi-ECC: enhanced error resiliency for magnetic memories. MEMSYS 2019: 85-100 - [i3]Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David W. Nellans, Puneet Gupta:
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training. CoRR abs/1907.13257 (2019) - 2018
- [j41]Wei-Che Wang, Charles Zhao, Puneet Gupta:
Assessing Layout Density Benefits of Vertical Channel Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3211-3215 (2018) - [j40]Wei-Che Wang, Yair Yona, Suhas N. Diggavi, Puneet Gupta:
Design and Analysis of Stability-Guaranteed PUFs. IEEE Trans. Inf. Forensics Secur. 13(4): 978-992 (2018) - [c83]Irina Alam, Clayton Schoeny, Lara Dolecek, Puneet Gupta:
Parity++: Lightweight Error Correction for Last Level Caches. DSN Workshops 2018: 114-120 - [c82]Saptadeep Pal, Daniel Petrisko, Adeel Ahmad Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar:
A Case for Packageless Processors. HPCA 2018: 466-479 - [c81]Clayton Schoeny, Irina Alam, Mark Gottscho, Puneet Gupta, Lara Dolecek:
Error Correction and Detection for Computing Memories Using System Side Information. ITW 2018: 1-5 - [i2]Wei-Che Wang, Yair Yona, Yizhang Wu, Suhas N. Diggavi, Puneet Gupta:
Implementation and Analysis of Stable PUFs Using Gate Oxide Breakdown. CoRR abs/1808.01516 (2018) - 2017
- [j39]Mark Gottscho, Mohammed Shoaib, Sriram Govindan, Bikash Sharma, Di Wang, Puneet Gupta:
Measuring the Impact of Memory Errors on Application Performance. IEEE Comput. Archit. Lett. 16(1): 51-55 (2017) - [j38]Liangzhen Lai, Puneet Gupta:
System-Level Dynamic Variation Margining in Presence of Monitoring and Actuation. IEEE Embed. Syst. Lett. 9(3): 85-88 (2017) - [j37]Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng:
Benchmarking of Mask Fracturing Heuristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 170-183 (2017) - [j36]Liheng Zhu, Yasmine Badr, Shaodi Wang, Subramanian S. Iyer, Puneet Gupta:
Assessing Benefits of a Buried Interconnect Layer in Digital Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(2): 346-350 (2017) - [j35]Yasmine Badr, Andres Torres, Puneet Gupta:
Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for Sub-7 nm Contact/Via Holes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 913-926 (2017) - [j34]Mark Gottscho, Irina Alam, Clayton Schoeny, Lara Dolecek, Puneet Gupta:
Low-Cost Memory Fault Tolerance for IoT Devices. ACM Trans. Embed. Comput. Syst. 16(5s): 128:1-128:25 (2017) - [j33]Hochul Lee, Albert Lee, Shaodi Wang, Farbod Ebrahimi, Puneet Gupta, Pedram Khalili Amiri, Kang L. Wang:
A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2027-2034 (2017) - [c80]Wei-Che Wang, Yair Yona, Yizhang Wu, Szu-Yao Hung, Suhas N. Diggavi, Puneet Gupta:
Implementation of stable PUFs using gate oxide breakdown. AsianHOST 2017: 13-18 - [c79]Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Puneet Gupta:
Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing. DATE 2017: 1438-1443 - [c78]Saptadeep Pal, Subramanian S. Iyer, Puneet Gupta:
Advanced Packaging and Heterogeneous Integration to Reboot Computing. ICRC 2017: 1-6 - [c77]Clayton Schoeny, Frederic Sala, Mark Gottscho, Irina Alam, Puneet Gupta, Lara Dolecek:
Context-aware resiliency: Unequal message protection for random-access memories. ITW 2017: 166-170 - [i1]Wei-Che Wang, Yair Yona, Suhas N. Diggavi, Puneet Gupta:
Design and Analysis of Stability-Guaranteed PUFs. CoRR abs/1701.05637 (2017) - 2016
- [j32]Shaodi Wang, Hochul Lee, Farbod Ebrahimi, P. Khalili Amiri, Kang L. Wang, Puneet Gupta:
Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 134-145 (2016) - [j31]Wei-Che Wang, Puneet Gupta:
Efficient Layout Generation and Design Evaluation of Vertical Channel Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1449-1460 (2016) - [j30]Shaodi Wang, Henry Chaohong Hu, Hongzhong Zheng, Puneet Gupta:
MEMRES: A Fast Memory System Reliability Simulator. IEEE Trans. Reliab. 65(4): 1783-1797 (2016) - [j29]Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta:
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 192-205 (2016) - [j28]Greg Leung, Shaodi Wang, Andrew Pan, Puneet Gupta, Chi On Chui:
An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1858-1870 (2016) - [c76]Liangzhen Lai, Puneet Gupta:
Hardware Reliability margining for the dark silicon era. ASP-DAC 2016: 637-642 - [c75]Shaodi Wang, Hochul Lee, Cecile Grezes, Pedram Khalili, Kang L. Wang, Puneet Gupta:
MTJ variation monitor-assisted adaptive MRAM write. DAC 2016: 169:1-169:6 - [c74]Qixiang Zhang, Liangzhen Lai, Mark Gottscho, Puneet Gupta:
Multi-story power distribution networks for GPUs. DATE 2016: 451-456 - [c73]Mark Gottscho, Clayton Schoeny, Lara Dolecek, Puneet Gupta:
Software-Defined Error-Correcting Codes. DSN Workshops 2016: 276-282 - [c72]Wei-Che Wang, Yair Yona, Suhas N. Diggavi, Puneet Gupta:
LEDPUF: Stability-guaranteed physical unclonable functions through locally enhanced defectivity. HOST 2016: 25-30 - [c71]Mark Gottscho, Sriram Govindan, Bikash Sharma, Mohammed Shoaib, Puneet Gupta:
X-Mem: A cross-platform and extensible memory characterization tool for the cloud. ISPASS 2016: 263-273 - 2015
- [j27]Lucas Francisco Wanner, Liangzhen Lai, Abbas Rahimi, Mark Gottscho, Pietro Mercati, Chu-Hsiang Huang, Frederic Sala, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt, Puneet Gupta, Rajesh K. Gupta, Ranjit Jhala, Rakesh Kumar, Sorin Lerner, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester, Yuanyuan Zhou:
NSF expedition on variability-aware software: Recent results and contributions. it Inf. Technol. 57(3): 181-198 (2015) - [j26]Mark Gottscho, Abbas BanaiyanMofrad, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era. ACM Trans. Archit. Code Optim. 12(3): 27:1-27:26 (2015) - [j25]Mark Gottscho, Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings. IEEE Trans. Computers 64(5): 1483-1496 (2015) - [c70]Liangzhen Lai, Vikas Chandra, Puneet Gupta:
Evaluating and exploiting impacts of dynamic power management schemes on system reliability. CASES 2015: 39-48 - [c69]Yasmine Badr, Andres Torres, Puneet Gupta:
Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7nm contacts/vias. DAC 2015: 70:1-70:6 - [c68]Abde Ali Kagalwalla, Puneet Gupta:
Effective model-based mask fracturing for mask cost reduction. DAC 2015: 73:1-73:6 - [c67]Santanu Sarma, Nikil D. Dutt, Puneet Gupta, Nalini Venkatasubramanian, Alexandru Nicolau:
Cyberphysical-system-on-chip (CPSoC): a self-aware MPSoC paradigm with cross-layer virtual sensing and actuation. DATE 2015: 625-628 - 2014
- [j24]Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta:
BTI-Gater: An Aging-Resilient Clock Gating Methodology. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(2): 180-189 (2014) - [j23]Lerong Cheng, Wenyao Xu, Fengbo Ren, Fang Gong, Puneet Gupta, Lei He:
Statistical timing and power analysis of VLSI considering non-linear dependence. Integr. 47(4): 487-498 (2014) - [j22]Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta:
SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1168-1179 (2014) - [j21]Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai:
Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2117-2130 (2014) - [c66]Rani S. Ghaida, Yasmine Badr, Mukul Gupta, Ning Jin, Puneet Gupta:
Comprehensive die-level assessment of design rules and layouts. ASP-DAC 2014: 61-66 - [c65]Abde Ali Kagalwalla, Michale Lam, Kostas Adam, Puneet Gupta:
EUV-CDA: Pattern shift aware critical density analysis for EUV mask layouts. ASP-DAC 2014: 155-160 - [c64]Liangzhen Lai, Puneet Gupta:
Accurate and inexpensive performance monitoring for variability-aware systems. ASP-DAC 2014: 467-473 - [c63]Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta:
PROCEED: A pareto optimization-based circuit-level evaluator for emerging devices. ASP-DAC 2014: 818-824 - [c62]Santanu Sarma, Nikil D. Dutt, Puneet Gupta, Alexandru Nicolau, Nalini Venkatasubramanian:
On-chip self-awareness using Cyberphysical-Systems-on-Chip (CPSoC). CODES+ISSS 2014: 22:1-22:3 - [c61]Nikil D. Dutt, Puneet Gupta, Alex Nicolau, Abbas BanaiyanMofrad, Mark Gottscho, Majid Shoushtari:
Multi-Layer Memory Resiliency. DAC 2014: 48:1-48:6 - [c60]Mark Gottscho, Abbas BanaiyanMofrad, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches. DAC 2014: 100:1-100:6 - [c59]Salma Elmalaki, Mark Gottscho, Puneet Gupta, Mani B. Srivastava:
A Case for Battery Charging-Aware Power Management and Deferrable Task Scheduling in Smartphones. HotPower 2014 - [c58]Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria:
Benchmarking of mask fracturing heuristics. ICCAD 2014: 246-253 - [c57]Wei-Che Wang, Puneet Gupta:
Efficient layout generation and evaluation of vertical channel devices. ICCAD 2014: 550-556 - [c56]Rani S. Ghaida, Yasmine Badr, Puneet Gupta:
Pattern-restricted design at 10nm and beyond. ICCD 2014: 308-310 - [c55]Parag Kulkarni, Puneet Gupta, Rudy Beraha:
Minimizing clock domain crossing in Network on Chip interconnect. ISQED 2014: 292-299 - 2013
- [j20]Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester:
Underdesigned and Opportunistic Computing in Presence of Hardware Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 8-23 (2013) - [j19]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
Layout Decomposition and Legalization for Double-Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 202-215 (2013) - [j18]Lucas Francisco Wanner, Charwak Apte, Rahul Balani, Puneet Gupta, Mani B. Srivastava:
Hardware Variability-Aware Duty Cycling for Embedded Sensors. IEEE Trans. Very Large Scale Integr. Syst. 21(6): 1000-1012 (2013) - [c54]Nikil D. Dutt, Puneet Gupta, Alex Nicolau, Luis Angel D. Bathen, Mark Gottscho:
Variability-aware memory management for nanoscale computing. ASP-DAC 2013: 125-132 - [c53]Puneet Gupta:
Design for nanoscale patterning. CICC 2013: 1-52 - [c52]Lucas Francisco Wanner, Salma Elmalaki, Liangzhen Lai, Puneet Gupta, Mani B. Srivastava:
VarEMU: An emulation testbed for variability-aware software. CODES+ISSS 2013: 27:1-27:10 - [c51]Majid Namaki-Shoushtari, Abbas Rahimi, Nikil D. Dutt, Puneet Gupta, Rajesh K. Gupta:
ARGO: Aging-aware GPGPU register file allocation. CODES+ISSS 2013: 30:1-30:9 - [c50]Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn:
Reliable on-chip systems in the nano-era: lessons learnt and future trends. DAC 2013: 99:1-99:10 - [c49]Liangzhen Lai, Vikas Chandra, Robert C. Aitken, Puneet Gupta:
SlackProbe: a low overhead in situ on-line timing slack monitoring methodology. DATE 2013: 282-287 - [c48]Rani S. Ghaida, Puneet Gupta:
Role of design in multiple patterning: technology development, design enablement and process control. DATE 2013: 314-319 - [c47]Ankur Sharma, Joseph Sloan, Lucas Francisco Wanner, Salma Elmalaki, Mani B. Srivastava, Puneet Gupta:
Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardware. ICCD 2013: 435-438 - 2012
- [j17]Mark Gottscho, Abde Ali Kagalwalla, Puneet Gupta:
Power Variability in Contemporary DRAMs. IEEE Embed. Syst. Lett. 4(2): 37-40 (2012) - [j16]John Lee, Puneet Gupta:
Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment. Found. Trends Electron. Des. Autom. 6(1): 1-120 (2012) - [j15]Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald:
Design-Aware Mask Inspection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 690-702 (2012) - [j14]Rani S. Ghaida, Puneet Gupta:
DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1379-1392 (2012) - [j13]Santiago Mok, John Lee, Puneet Gupta:
Discrete sizing for leakage power optimization in physical design: A comparative study. ACM Trans. Design Autom. Electr. Syst. 18(1): 15:1-15:11 (2012) - [j12]John Lee, Puneet Gupta:
ECO cost measurement and incremental gate sizing for late process changes. ACM Trans. Design Autom. Electr. Syst. 18(1): 16:1-16:11 (2012) - [j11]Aashish Pant, Puneet Gupta, Mihaela van der Schaar:
AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1986-1996 (2012) - [c46]Luis Angel D. Bathen, Mark Gottscho, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings. CODES+ISSS 2012: 33-42 - [c45]Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
VaMV: Variability-aware Memory Virtualization. DATE 2012: 284-287 - [c44]Rani S. Ghaida, Tanaya Sahu, Parag Kulkarni, Puneet Gupta:
A methodology for the early exploration of design rules for multiple-patterning technologies. ICCAD 2012: 50-56 - [c43]John Lee, Puneet Gupta:
Impact of range and precision in technology on cell-based design. ICCAD 2012: 218-225 - [c42]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta:
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction. ICICDT 2012: 1-4 - [c41]Tuck-Boon Chan, Puneet Gupta, Andrew B. Kahng, Liangzhen Lai:
DDRO: A novel performance monitoring methodology based on design-dependent ring oscillators. ISQED 2012: 633-640 - [c40]John Lee, Puneet Gupta, Fedor Pikus:
Parametric Hierarchy Recovery in Layout Extracted Netlists. ISVLSI 2012: 332-337 - 2011
- [j10]Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac:
Trading Accuracy for Power in a Multiplier Architecture. J. Low Power Electron. 7(4): 490-501 (2011) - [j9]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 388-401 (2011) - [c39]Puneet Gupta, Rajesh K. Gupta:
Underdesigned and Opportunistic Computing. Asian Test Symposium 2011: 498-499 - [c38]Lucas Francisco Wanner, Rahul Balani, Sadaf Zahedi, Charwak Apte, Puneet Gupta, Mani B. Srivastava:
Variability-aware duty cycle scheduling in long running embedded sensing systems. DATE 2011: 131-136 - [c37]Tuck-Boon Chan, John Sartori, Puneet Gupta, Rakesh Kumar:
On the efficacy of NBTI mitigation techniques. DATE 2011: 932-937 - [c36]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
A framework for double patterning-enabled design. ICCAD 2011: 14-20 - [c35]Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac:
Trading Accuracy for Power with an Underdesigned Multiplier Architecture. VLSI Design 2011: 346-351 - 2010
- [j8]Jason Cong, Puneet Gupta, John Lee:
Evaluating Statistical Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1750-1762 (2010) - [c34]Lerong Cheng, Puneet Gupta, Lei He:
On confidence in characterization and application of variation models. ASP-DAC 2010: 751-756 - [c33]Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma:
Eyecharts: constructive benchmarking of gate sizing heuristics. DAC 2010: 597-602 - [c32]Aashish Pant, Puneet Gupta, Mihaela van der Schaar:
Software adaptation in quality sensitive applications to deal with hardware variability. ACM Great Lakes Symposium on VLSI 2010: 85-90 - [c31]Abde Ali Kagalwalla, Puneet Gupta, Christopher J. Progler, Steve McDonald:
Design-aware mask inspection. ICCAD 2010: 93-99 - [c30]Tuck-Boon Chan, Aashish Pant, Lerong Cheng, Puneet Gupta:
Design dependent process monitoring for back-end manufacturing cost reduction. ICCAD 2010: 116-122 - [c29]John Lee, Puneet Gupta:
Incremental gate sizing for late process changes. ICCD 2010: 215-221 - [c28]John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta:
Variation-aware speed binning of multi-core processors. ISQED 2010: 307-314 - [c27]Tuck-Boon Chan, Puneet Gupta:
On Electrical Modeling of Imperfect Diffusion Patterning. VLSI Design 2010: 224-229 - [c26]Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta:
Electrical Modeling of Lithographic Imperfections. VLSI Design 2010: 423-428
2000 – 2009
- 2009
- [j7]Lerong Cheng, Puneet Gupta, Lei He:
Efficient Additive Statistical Leakage Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1777-1781 (2009) - [c25]Jason Cong, Puneet Gupta, John Lee:
On the futility of statistical power optimization. ASP-DAC 2009: 167-172 - [c24]Lerong Cheng, Puneet Gupta, Lei He:
Accounting for non-linear dependence using function driven component analysis. ASP-DAC 2009: 474-479 - [c23]Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
Physically justifiable die-level modeling of spatial variation in view of systematic across wafer variability. DAC 2009: 104-109 - [c22]Rani S. Ghaida, Puneet Gupta:
A framework for early and systematic evaluation of design rules. ICCAD 2009: 615-622 - 2008
- [c21]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester:
Investigation of diffusion rounding for post-lithography analysis. ASP-DAC 2008: 480-485 - [c20]Puneet Gupta, Andrew B. Kahng:
Bounded-lifetime integrated circuits. DAC 2008: 347-348 - 2007
- [j6]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1614-1624 (2007) - [j5]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park:
Detailed Placement for Enhanced Control of Resist and Etch CDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2144-2157 (2007) - [c19]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester:
Line-End Shortening is Not Always a Failure. DAC 2007: 270-271 - 2006
- [j4]Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester:
Gate-length biasing for runtime-leakage control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1475-1485 (2006) - [j3]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu:
Wafer Topography-Aware Optical Proximity Correction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2747-2756 (2006) - [c18]Saumil Shah, Puneet Gupta, Andrew B. Kahng:
Standard cell library optimization for leakage reduction. DAC 2006: 983-986 - [c17]Puneet Gupta, Andrew B. Kahng:
Efficient Design and Analysis of Robust Power Distribution Meshes. VLSI Design 2006: 337-342 - 2005
- [j2]Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma:
Layout-aware scan chain synthesis for improved path delay fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1104-1114 (2005) - [j1]Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
Routing-aware scan chain ordering. ACM Trans. Design Autom. Electr. Syst. 10(3): 546-560 (2005) - [c16]Puneet Gupta, Andrew B. Kahng, Chul-Hong Park:
Detailed placement for improved depth of focus and CD control. ASP-DAC 2005: 343-348 - [c15]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. DAC 2005: 365-368 - [c14]Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
Performance Driven OPC for Mask Cost Reduction. ISQED 2005: 270-275 - [c13]Puneet Gupta, Andrew B. Kahng, Puneet Sharma:
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology. ISQED 2005: 421-426 - 2004
- [c12]Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
Toward a methodology for manufacturability-driven design rule exploration. DAC 2004: 311-316 - [c11]Puneet Gupta, Fook-Luen Heng:
Toward a systematic-variation aware timing methodology. DAC 2004: 321-326 - [c10]Puneet Gupta, Andrew B. Kahng, Puneet Sharma, Dennis Sylvester:
Selective gate-length biasing for cost-effective runtime leakage control. DAC 2004: 327-330 - [c9]Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Investigation of performance metrics for interconnect stack architectures. SLIP 2004: 23-29 - [c8]Puneet Gupta, Andrew B. Kahng:
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. VLSI Design 2004: 431-436 - 2003
- [c7]Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
Routing-aware scan chain ordering. ASP-DAC 2003: 857-862 - [c6]Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang:
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. DAC 2003: 16-21 - [c5]Yu Chen, Puneet Gupta, Andrew B. Kahng:
Performance-impact limited area fill synthesis. DAC 2003: 22-27 - [c4]Puneet Gupta, Andrew B. Kahng:
Manufacturing-Aware Physical Design. ICCAD 2003: 681-688 - [c3]Puneet Gupta, Andrew B. Kahng, Ion I. Mandoiu, Puneet Sharma:
Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage. ICCAD 2003: 754-759 - [c2]Puneet Gupta, Andrew B. Kahng:
Quantifying Error in Dynamic Power Estimation of CMOS Circuits. ISQED 2003: 273-278 - [c1]Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. ISQED 2003: 339-343
Coauthor Index
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