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ORCIDSwathi T. Gurumani
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2010 – 2019
- 2019
[j6]Keith A. Campbell
, David Lin, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Subhasish Mitra, Deming Chen:
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1345-1358 (2019)- 2016
- [j5]Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow, Zhiru Zhang:
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 70-77 (2016) - [j4]Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen:
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2032-2045 (2016) - [j3]Yao Chen, Swathi T. Gurumani, Yun Liang, Guofeng Li, Donghui Guo, Kyle Rupnow, Deming Chen:
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2220-2233 (2016) - [c21]Zelei Sun, Keith A. Campbell, Wei Zuo, Kyle Rupnow, Swathi T. Gurumani, Frederic Doucet, Deming Chen:
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. ASP-DAC 2016: 218-225 - [c20]Keith A. Campbell, Leon He, Liwei Yang, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. DAC 2016: 7:1-7:6 - [c19]Muhammad Teguh Satria, Swathi T. Gurumani, Wang Zheng, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow, Deming Chen:
Real-time system-level implementation of a telepresence robot using an embedded GPU platform. DATE 2016: 1445-1448 - [c18]Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
AutoSLIDE: Automatic Source-Level Instrumentation and Debugging for HLS. FCCM 2016: 127-130 - [c17]Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler. FPGA 2016: 5-14 - [c16]Xinheng Liu, Yao Chen, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
High Level Synthesis of Complex Applications: An H.264 Video Decoder. FPGA 2016: 224-233 - [c15]Liwei Yang, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only). FPGA 2016: 278 - [c14]Tan Nguyen, Yao Chen, Kyle Rupnow, Swathi T. Gurumani, Deming Chen:
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow. ISVLSI 2016: 661-666 - 2015
- [c13]Liwei Yang, Yao Chen, Wei Zuo, Tan Nguyen, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
System-level design solutions: Enabling the IoT explosion. ASICON 2015: 1-4 - [c12]Liwei Yang, Swathi T. Gurumani, Deming Chen, Kyle Rupnow:
Behavioral-level IP integration in high-level synthesis. FPT 2015: 172-175 - [c11]Liwei Yang, Magzhan Ikram, Swathi T. Gurumani, Suhaib A. Fahmy, Deming Chen, Kyle Rupnow:
JIT trace-based verification for high-level synthesis. FPT 2015: 228-231 - 2014
- [j2]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow:
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1832-1845 (2014) - [c10]Swathi T. Gurumani, Jacob Tolar, Yao Chen, Yun Liang, Kyle Rupnow, Deming Chen:
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. FCCM 2014: 21-24 - [c9]Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
Fast and effective placement and routing directed high-level synthesis for FPGAs. FPGA 2014: 1-10 - [c8]Wei Zuo, Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow, Deming Chen:
New solutions for system-level and high-level synthesis (Invited paper). ISIC 2014: 71-74 - 2013
- [c7]Swathi T. Gurumani, Hisham Cholakkal, Yun Liang, Kyle Rupnow, Deming Chen:
High-level synthesis of multiple dependent CUDA kernels on FPGA. ASP-DAC 2013: 305-312 - [c6]Hongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow:
High-level synthesis with behavioral level multi-cycle path analysis. FPL 2013: 1-8
2000 – 2009
- 2009
- [j1]Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla:
Hardware Coprocessor Synthesis from an ANSI C Specification. IEEE Des. Test Comput. 26(4): 58-67 (2009) - 2007
- [c5]Swathi Tanjore Gurumani, B. Earl Wells:
Dynamic Power Management in Power-Aware Reconfigurable System-on-Chip Architectures. ESA 2007: 177-183 - [c4]Swathi Tanjore Gurumani, B. Earl Wells:
Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures. ERSA 2007: 37-43 - 2006
- [c3]Swathi Tanjore Gurumani, Mathew M. Noel, B. Earl Wells, Thomas C. Jannett:
Performance Analysis of Coarse-Grained Parallel Particle Swarm Optimization. PDCS 2006: 197-202 - 2004
- [c2]Swathi Tanjore Gurumani, Aleksandar Milenkovic:
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++. ACM Southeast Regional Conference 2004: 261-266 - 2003
- [c1]Zexin Pan, Srikanth Venkateswaran, Swathi Tanjore Gurumani, B. Earl Wells:
Exploiting Fine-Grain Parallelism of IDEA Using Xilinx FPGA. PDCS 2003: 377-382
Coauthor Index
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