default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID10. FPGA 2002: Monterey, CA, USA
- Martine D. F. Schlag, Steve Trimberger:
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002. ACM 2002, ISBN 1-58113-452-5
Interconnect Architecture
- Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev:
Interconnect enhancements for a high-speed PLD architecture. 3-10 - Herman Schmit, Vikas Chandra:
FPGA switch block layout and evaluation. 11-18 - Guy G. Lemieux, David M. Lewis:
Circuit design of routing switches. 19-28
Arithmetic
- Radhika S. Grover, Weijia Shang, Qiang Li:
A faster distributed arithmetic architecture for FPGAs. 31-39 - Alan Daly, William P. Marnane:
Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. 40-49 - J. Dido, N. Géraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier:
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. 50-55
Physical Design
- Amit Singh, Malgorzata Marek-Sadowska:
Efficient circuit clustering for area and power reduction in FPGAs. 59-66 - Deshanand P. Singh
, Stephen Dean Brown:
Integrated retiming and placement for field programmable gate arrays. 67-76 - Jason Cong, Yizhou Lin, Wangning Long:
SPFD-based global rewiring. 77-84 - William Chow, Jonathan Rose:
EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. 85-94
Cellular and Cryptographic Applications
- Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski:
Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method. 97-105 - Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider:
FPGA implementation of neighborhood-of-four cellular automata random number generators. 106-112 - Tom Kean:
Cryptographic rights management of FPGA intellectual property cores. 113-118
Synthesis, Verification and Test
- Deshanand P. Singh, Stephen Dean Brown:
Constrained clock shifting for field programmable gate arrays. 121-126 - Ian Robertson, James Irvine, Patrick Lysaght, David Robinson:
Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series. 127-135 - Stuart McCracken, Zeljko Zilic:
FPGA test time reduction through a novel interconnect testing scheme. 136-144
Architecture Analysis and Automation
- Andy Yan, Rebecca Cheng, Steven J. E. Wilton:
On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. 147-156 - Li Shang, Alireza Kaviani, Kusuma Bathala:
Dynamic power consumption in Virtex[tm]-II FPGA family. 157-164 - Shawn Phillips, Scott Hauck:
Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. 165-173
Software for Reconfigurable Systems
- Greg Snider:
Performance-constrained pipelining of software loops onto reconfigurable hardware. 177-186 - Zhiyuan Li, Scott Hauck:
Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation. 187-195 - Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon:
Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. 196-205 - K. K. Lee, D. F. Wong:
Incremental reconfiguration of multi-FPGA systems. 206-213
Innovative Applications
- Srdjan Coric, Miriam Leeser, Eric L. Miller, Marc Trepanier:
Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. 217-226 - Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson:
A dynamically reconfigurable adaptive viterbi decoder. 227-236 - Pedro C. Diniz, Joonseok Park:
Data reorganization engines for the next generation of system-on-a-chip FPGAs. 237-244
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-23 19:49 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
