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ORCID22nd FCCM 2014: Boston, MA, USA
- 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, Boston, MA, USA, May 11-13, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-5110-9
Session 1: FPGA Synthesis and CGRAs
- Felix Winterstein, Samuel Bayliss, George A. Constantinides:
Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis. 1-8 - Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao, Peipei Zhou
:
A Fully Pipelined and Dynamically Composable Architecture of CGRA. 9-16 - Jonathon Pendlum, Miriam Leeser, Kaushik R. Chowdhury:
Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework. 17-20 - Swathi T. Gurumani, Jacob Tolar, Yao Chen, Yun Liang, Kyle Rupnow, Deming Chen:
Integrated CUDA-to-FPGA Synthesis with Network-on-Chip. 21-24 - Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martínez, Carlos Guestrin:
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. 25-28
Poster Session I
- Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv:
Using Multi-op Instructions as a Way to Generate ASIPs with Optimized Pipeline Structure. 29 - Christophe Huriaux, Olivier Sentieys, Russell Tessier:
FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions. 30 - Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Customizable Compression Architecture for Efficient Configuration in CGRAs. 31 - Dajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei:
Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures. 32 - Mansureh Shahraki Moghaddam, Kolin Paul, M. Balakrishnan:
Mapping Tasks to a Dynamically Reconfigurable Coarse Grained Array. 33 - Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima:
Better-Than-DMR Techniques for Yield Improvement. 34 - Tian Xiang, Lei Zhao, Xi Jin, Tianqi Wang, Shaoping Chu, Cong Ma, Shubin Liu, Qi An, Xue Ben:
A Multi-phase Clock Time-to-Digital Convertor Based on ISERDES Architecture. 35
Session 2: Algorithms, Architectures, and Circuits for Mathematical Computation
- Jeremy Fowers, Kalin Ovtcharov, Karin Strauss, Eric S. Chung, Greg Stitt:
A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication. 36-43 - Klaus Schneider, Adrian Willenbücher:
A New Algorithm for Carry-Free Addition of Binary Signed-Digit Numbers. 44-51 - Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
On Hard Adders and Carry Chains in FPGAs. 52-59 - Siddhartha, Nachiket Kapre:
Breaking Sequential Dependencies in FPGA-Based Sparse LU Factorization. 60-63 - Xinying Wang, Joseph Zambreno:
An Efficient Architecture for Floating-Point Eigenvalue Decomposition. 64-67 - Benjamin Humphries, Hansen Zhang, Jiayi Sheng, Raphael Landaverde, Martin C. Herbordt:
3D FFTs on a Single FPGA. 68-71
Session 3: Circuit Characterization and Debug
- Brad L. Hutchings, Jared Keeley:
Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs. 72-79 - Girish Venkataramani, Yongfeng Gu:
System-Level Retiming and Pipelining. 80-87 - Benjamin Gojman, André DeHon:
GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction. 88-95 - Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre:
Timing Fault Detection in FPGA-Based Circuits. 96-99
Poster Session II
- Pham Nam Khanh, Amit Kumar Singh, Akash Kumar, Khin Mi Mi Aung:
Design Space Exploration to Accelerate Nelder-Mead Algorithm Using FPGA. 100 - Bajaj Ronak, Suhaib A. Fahmy:
Experiments in Mapping Expressions to DSP Blocks. 101 - Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar:
Memory Optimized Re-gridding for Non-uniform Fast Fourier Transform on FPGAs. 102 - James J. Davis, Peter Y. K. Cheung:
Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. 103 - Lu He, Yan Luo, Yu Cao:
Accelerator of Stacked Convolutional Independent Subspace Analysis for Deep Learning-Based Action Recognition. 104 - Sven Hager, Frank Winkler, Björn Scheuermann, Klaus Reinhardt:
Building Optimized Packet Filters with COFFi. 105 - Yanbiao Li, Dafang Zhang, Xian Yu, Jing Long, Wei Liang:
From GPU to FPGA: A Pipelined Hierarchical Approach to Fast and Memory-Efficient NDN Name Lookup. 106 - Xiaoyin Ma, Walid A. Najjar, Amit K. Roy-Chowdhury:
High-Throughput Fixed-Point Object Detection on FPGAs. 107 - Hendrik Noll, Sebastian Siegert, Johannes Hiltscher, Wolfgang Rehm:
UTOPIA: Generic User-Level Access to the Physical Memory Address Space for IP Core Debugging and Validation on FPGA Based PCIe Extension Cards. 108
Session 4: Computing and Multi-FPGA Platforms
- Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow:
FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack. 109-116 - Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer:
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories. 117-124 - Qingshan Tang, Matthieu Tuna, Habib Mehrez:
Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom. 125-132
Session 5: Applications
- Jeffrey Cassidy, Lothar Lilge, Vaughn Betz:
Fast, Power-Efficient Biophotonic Simulations for Cancer Treatment Using FPGAs. 133-140 - Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk:
SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. 141-148 - David B. Thomas:
FPGA Gaussian Random Number Generators with Guaranteed Statistical Accuracy. 149-156 - Young Kyu Choi, Jason Cong, Di Wu:
FPGA Implementation of EM Algorithm for 3D CT Reconstruction. 157-160 - Joo-Young Kim, Scott Hauck, Doug Burger:
A Scalable Multi-engine Xpress9 Compressor with Asynchronous Data Transfer. 161-164 - Matthew Jacobsen, Pingfan Meng, Siddarth Sampangi, Ryan Kastner:
FPGA Accelerated Online Boosting for Multi-target Tracking. 165-168
Poster Session III
- Kaveh Aasaraai, Andreas Moshovos:
An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design. 169 - Gang Chen, Biao Hu, Kai Huang, Alois C. Knoll, Di Liu:
Abstract: Shared L2 Cache Management in Multicore Real-Time System. 170 - Chad D. Kersey, Sudhakar Yalamanchili, Hyojong Kim, Nimit Nigania, Hyesoon Kim:
Harmonica: An FPGA-Based Data Parallel Soft Core. 171 - Peng Li, Thomas Page, Guojie Luo, Wentai Zhang, Pei Wang, Peng Zhang, Peter Maass, Ming Jiang, Jason Cong:
FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation. 172 - Shiming Li, Miaoqing Huang, Hongyuan Ding, Sen Ma:
A Hierarchical Memory Architecture with NoC Support for MPSoC on FPGAs. 173 - Shuo Li, Ahmed Hemani:
Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver. 174 - Yu Tanabe, Tsutomu Maruyama:
FPGA Implementation of Optical Flow Algorithm Based on Cost Aggregation. 175 - Di Wu, Andreas Moshovos:
Image Signal Processors on FPGAs. 176 - Wenlai Zhao, Haohuan Fu, Guangwen Yang:
A Fully-Pipelined FPGA Design for Tree-Reweighted Message Passing Algorithm. 177
Session 6: Synthesis II
- Matthew An, J. Gregory Steffan, Vaughn Betz:
Speeding Up FPGA Placement: Parallel Algorithms and Methods. 178-185 - Marco Rabozzi, John Lillis, Marco D. Santambrogio:
Floorplanning for Partially-Reconfigurable FPGA Systems via Mixed-Integer Linear Programming. 186-193 - Muhsen Owaida, Christos D. Antonopoulos, Nikolaos Bellas:
A Grammar Induction Method for Clustering of Operations in Complex FPGA Designs. 194-201 - Kizheppatt Vipin, Suhaib A. Fahmy:
Automated Partial Reconfiguration Design for Adaptive Systems with CoPR for Zynq. 202-205 - Deheng Ye, Nachiket Kapre:
MixFX-SCORE: Heterogeneous Fixed-Point Compilation of Dataflow Computations. 206-209 - Maciej Kurek, Tobias Becker, Thomas C. P. Chau, Wayne Luk:
Automating Optimization of Reconfigurable Designs. 210-213
Session 7: Energy and Encryption
- Edin Kadric, Kunal Mahajan, André DeHon:
Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations. 214-221 - Heinrich Riebler, Tobias Kenter, Christian Plessl, Christoph Sorge:
Reconstructing AES Key Schedules from Decayed Memory with FPGAs. 222-229 - Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien, Christophe Huriaux:
Low Power Reconfigurable Controllers for Wireless Sensor Network Nodes. 230-233
Poster Session IV
- Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides:
Compiling Higher Order Functional Programs to Composable Digital Hardware. 234 - Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs. 235 - Saad Arrabi, D. Moore, L. Wang, Kevin Skadron, Benton H. Calhoun, John C. Lach, Brett H. Meyer:
Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems. 236 - Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado:
Fast and Power Efficient Heapsort IP for Image Compression Application. 237 - Roland Christian Gamom Ngounou Ewo, Andréa Pinna, Bertrand Granado, Martin Mbouenda, Hilaire Bertrand Fotsin:
A Hardware MPI Spawn for Distributed Multiprocessing Reconfigurable System on Chip (MP-RSoC). 238 - Laurent Gantel, Mohamed El Amine Benkhelifa, François Verdier, Fabrice Lemonnier:
MRAPI Implementation for Heterogeneous Reconfigurable Systems-on-Chip. 239 - Brandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So:
Scheduling Mixed-Architecture Processes in Tightly Coupled FPGA-CPU Reconfigurable Computers. 240 - Hamed Tabkhi, Majid Sabbagh, Gunar Schirner:
A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution. 241 - Fumito Yamaguchi, Hiroaki Nishi:
High-Throughput and Low-Cost Hardware Accelerator for Privacy Preserving Publishing. 242
Session 8: Reliability
- Edin Kadric, Kunal Mahajan, André DeHon:
Energy Reduction through Differential Reliability and Lightweight Checking. 243-250 - Robért Glein, Bernhard Schmidt, Florian Rittner, Jürgen Teich, Daniel Ziener:
A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor. 251-258 - Monther Abusultan, Sunil P. Khatri:
Look-up Table Design for Deep Sub-threshold through Full-Supply Operation. 259-266
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