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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 27
Volume 27, Number 1, January 2022
- Nikolaos Foivos Polychronou, Pierre-Henri Thevenon, Maxime Puys
, Vincent Beroulle:
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms. 1:1-1:35
- Sri Harsha Gade, Sujay Deb:
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures. 2:1-2:31 - Ding Han, Guohui Li, Quan Zhou, Jianjun Li, Yong Yang, Xiaofei Hu:
An Efficient Execution Framework of Two-Part Execution Scenario Analysis. 3:1-3:24 - Jingyu He, Yao Xiao, Corina Bogdan, Shahin Nazarian, Paul Bogdan:
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles. 4:1-4:20 - Lanlan Cui, Fei Wu, Xiaojian Liu, Meng Zhang, Renzhi Xiao, Changsheng Xie:
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision. 5:1-5:20 - Bo Li, Guoyong Shi:
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits. 6:1-6:24 - Sudip Poddar, Sukanta Bhattacharjee, Shao-Yun Fang, Tsung-Yi Ho, Bhargab B. Bhattacharya:
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips. 7:1-7:21 - Qiang Liu, Honghui Tang, Peiran Zhang:
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs. 8:1-8:25 - Mengke Ge, Xiaobing Ni, Qi Xu, Song Chen, Jinglei Huang, Yi Kang, Feng Wu:
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips. 9:1-9:30
Volume 27, Number 2, March 2022
- Armin Alaghi, Eva Darulova, Andreas Gerstlauer, Phillip Stanley-Marbell:
Introduction to the Special Issue on Approximate Systems. 10:1-10:2 - Tiancong Bu, Kaige Yan, Jingweijia Tan:
Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs. 11:1-11:19 - Somesh Singh, Tejas Shah, Rupesh Nasre:
ParTBC: Faster Estimation of Top-k Betweenness Centrality Vertices on GPU. 12:1-12:25 - Liu Liu, Sibren Isaacman, Ulrich Kremer:
An Adaptive Application Framework with Customizable Quality Metrics. 13:1-13:33 - Prattay Chowdhury, Benjamin Carrión Schäfer:
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control. 14:1-14:18 - Ming Han, Ye Wang, Jian Dong, Gang Qu:
Double-Shift: A Low-Power DNN Weights Storage and Access Framework based on Approximate Decomposition and Quantization. 15:1-15:16 - Zahra Ebrahimi, Dennis Klar, Mohammad Aasim Ekhtiyar, Akash Kumar:
Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider. 16:1-16:33 - Jaechul Lee, Cédric Killian, Sébastien Le Beux, Daniel Chillet:
Distance-aware Approximate Nanophotonic Interconnect. 17:1-17:30
- Shaahin Angizi, Navid Khoshavi, Andrew Marshall, Peter Dowben, Deliang Fan:
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET. 18:1-18:18 - Xiao Shi, Hao Yan, Qiancun Huang, Chengzhen Xuan, Lei He, Longxing Shi:
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation. 19:1-19:23
Volume 27, Number 3, May 2022
- Han Cai, Ji Lin, Yujun Lin, Zhijian Liu, Haotian Tang, Hanrui Wang, Ligeng Zhu, Song Han:
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications. 20:1-20:50
- S. Skandha Deepsita, Dhayala Kumar M, Sk. Noor Mahammad:
Energy Efficient Error Resilient Multiplier Using Low-power Compressors. 21:1-21:26 - Mari-Liis Oldja, Jangryul Kim, Dowhan Jeong, Soonhoi Ha:
Hierarchical Scheduling of an SDF/L Graph onto Multiple Processors. 22:1-22:23 - Si Chen, Guoqi Xie, Renfa Li, Keqin Li:
Uncertainty Theory Based Partitioning for Cyber-Physical Systems with Uncertain Reliability Analysis. 23:1-23:19 - Yukui Luo, Shijin Duan, Xiaolin Xu:
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA. 24:1-24:31 - Lang Feng, Jiayi Huang, Jeff Huang, Jiang Hu:
Toward Taming the Overhead Monster for Data-flow Integrity. 25:1-25:24 - Mahabub Hasan Mahalat, Suraj Mandal, Anindan Mondal, Bibhash Sen, Rajat Subhra Chakraborty:
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT. 26:1-26:26 - Timothy J. Baker, John P. Hayes:
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design. 27:1-27:26 - Reena Elangovan, Shubham Jain, Anand Raghunathan:
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration. 28:1-28:20
Volume 27, Number 4, July 2022
- Christian Pilato, Zhenman Fang, Yuko Hara-Azumi, Jim Hwang:
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications. 29:1-29:2 - Nadesh Ramanathan, George A. Constantinides, John Wickerson:
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis. 30:1-30:26 - Qi Sun, Tinghuan Chen, Siting Liu, Jianli Chen, Hao Yu, Bei Yu:
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. 31:1-31:27 - Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong:
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators. 32:1-32:27 - Quentin Gautier, Alric Althoff, Christopher L. Crutchfield, Ryan Kastner:
Sherlock: A Multi-Objective Design Space Exploration Framework. 33:1-33:20 - Zi Wang, Benjamin Carrion Schafer:
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs. 34:1-34:23 - Panu Sjövall, Ari Lemmetti, Jarno Vanne, Sakari Lahti, Timo D. Hämäläinen:
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications. 35:1-35:34
- Yanjiang Liu, Tongzhou Qu, Zibin Dai:
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks. 36:1-36:13 - Shanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu:
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices. 37:1-37:19 - Necati Uysal, Rickard Ewetz:
Synthesis of Clock Networks with a Mode-Reconfigurable Topology. 38:1-38:22 - Mousum Handique, Jantindra Kumar Deka, Santosh Biswas:
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits. 39:1-39:29
- Wenzhong Guo, Sihuang Lian, Chen Dong, Zhenyi Chen, Xing Huang:
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense. 40:1-40:33
Volume 27, Number 5, September 2022
- Vikas Chandra, Yiran Chen, Sungjoo Yoo:
Introduction to the Special Section on Energy-Efficient AI Chips. 41:1-41:2 - Sunjung Lee, Jaewan Choi, Wonkyung Jung, Byeongho Kim, Jaehyun Park, Hweesoo Kim, Jung Ho Ahn:
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units. 42:1-42:25 - Nihat Mert Cicek, Xipeng Shen, Ozcan Ozturk:
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse. 43:1-43:26 - Zhe Chen, Hugh T. Blair, Jason Cong:
Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction. 44:1-44:19 - Aidin Shiri, Uttej Kallakuri, Hasib-Al Rashid, Bharat Prakash, Nicholas R. Waytowich, Tim Oates, Tinoosh Mohsenin:
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning. 45:1-45:19 - Nathan Laubeuf, Jonas Doevenspeck, Ioannis A. Papistas, Michele Caselli, Stefan Cosemans, Peter Vrancx, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Francky Catthoor, Rudy Lauwereins:
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. 46:1-46:21 - Yifan Gong, Geng Yuan, Zheng Zhan, Wei Niu, Zhengang Li, Pu Zhao, Yuxuan Cai, Sijia Liu, Bin Ren, Xue Lin, Xulong Tang, Yanzhi Wang:
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration. 47:1-47:26 - Jooyeon Lee, Junsang Park, Seunghyun Lee, Jaeha Kung:
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices. 48:1-48:24 - Yue Tang, Xinyi Zhang, Peipei Zhou, Jingtong Hu:
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization. 49:1-49:36 - Chaojian Li, Wuyang Chen, Yuchen Gu, Tianlong Chen, Yonggan Fu, Zhangyang Wang, Yingyan Lin:
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference. 50:1-50:20 - Min-Kwan Kee, Gi-Ho Park:
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices. 51:1-51:13
- Chenyi Wen, Xiao Dong, Baixin Chen, Umamaheswara Rao Tida, Yiyu Shi, Cheng Zhuo:
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter. 52:1-52:23 - Monzurul Islam Dewan, Dae Hyun Kim:
Design Automation Algorithms for the NP-Separate VLSI Design Methodology. 53:1-53:20
Volume 27, Number 6, November 2022
- Irith Pomeranz:
Increasing the Fault Coverage of a Truncated Test Set. 54:1-54:16 - Jagadheesh Samala, P. Veda Bhanu, Soumya J.:
NoC Application Mapping Optimization Using Reinforcement Learning. 55:1-55:16 - Gaurav Kolhe, Tyler David Sheaves, Sai Manoj P. D., Hamid Mahmoodi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun:
Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation. 56:1-56:29 - Taozhong Li, Naifeng Jing, Jianfei Jiang, Qin Wang, Zhigang Mao, Yiran Chen:
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. 57:1-57:22 - Michaela Brunner, Alexander Hepp, Johanna Baehr, Georg Sigl:
Toward a Human-Readable State Machine Extraction. 58:1-58:31 - Xiangzhen Zhou, Yuan Feng, Sanjiang Li:
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework. 59:1-59:27 - Xin Hong, Xiangzhen Zhou, Sanjiang Li, Yuan Feng, Mingsheng Ying:
A Tensor Network based Decision Diagram for Representation of Quantum Circuits. 60:1-60:30 - Dwaipayan Choudhury, Reet Barik, Aravind Sukumaran-Rajam, Ananth Kalyanaraman, Partha Pratim Pande:
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations. 61:1-61:22 - Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng:
Efficient Layout Hotspot Detection via Neural Architecture Search. 62:1-62:16 - Inga Abel, Helmut Graeb:
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition. 63:1-63:27 - Zhibing Sha, Jun Li, Zhigang Cai, Min Huang, Jianwei Liao, François Trahay:
Degraded Mode-benefited I/O Scheduling to Ensure I/O Responsiveness in RAID-enabled SSDs. 64:1-64:24 - Yunkai Bai, Andrew Stern, Jungmin Park, Mark M. Tehranipoor, Domenic Forte:
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems. 65:1-65:25
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