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ORCIDISSCC 2018: San Francisco, CA, USA
- 2018 IEEE International Solid-State Circuits Conference, ISSCC 2018, San Francisco, CA, USA, February 11-15, 2018. IEEE 2018, ISBN 978-1-5090-4940-0
- Vincent Roche:
Semiconductor innovation: Is the party over, or just getting started? 8-11 - Barbara De Salvo:
Brain-Inspired technologies: Towards chips that think? 12-18 - Yukihiro Kato:
Future mobility-enhanced society enabled by semiconductor technology. 21-26 - David A. Patterson:
50 Years of computer architecture: From the mainframe CPU to the domain-specific tpu and the open RISC-V instruction set. 27-31 - Thomas Burd, Muhammad M. Khellah, Byeong-Gyu Nam:
Session 2 overview: Processors: Digital architectures and systems subcommittee. 32-33 - Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang:
SkyLake-SP: A 14nm 28-Core xeon® processor. 34-36 - Christopher J. Berry, James D. Warnock, John Isakson, John Badar, Brian Bell, Frank Malgioglio, Guenter Mayer, Dina Hamid, Jesse Surprise, David Wolpert, Ofer Geva, Bill Huott, Leon J. Sigal, Sean M. Carey, Richard F. Rizzolo, Ricardo Nigaglioni, Mark Cichanowski, Dureseti Chidambarrao, Christian Jacobi, Anthony Saporito, Arthur O'neill, Robert J. Sonnelitter, Christian G. Zoellin, Michael H. Wood, José Neves:
IBM z14™: 14nm microprocessor for the next-generation mainframe. 36-38 - Pascal Meinerzhagen, Carlos Tokunaga
, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. 38-40 - Noah Beck, Sean White, Milam Paraschou, Samuel Naffziger:
'Zeppelin': An SoC for multichip architectures. 40-42 - Utsav Banerjee, Chiraag Juvekar, Andrew Wright, Arvind, Anantha P. Chandrakasan:
An energy-efficient reconfigurable DTLS cryptographic engine for End-to-End security in iot applications. 42-44 - Longyang Lin, Saurabh Jain, Massimo Alioto:
A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing. 44-46 - Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De:
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. 46-48 - Youngcheol Chae, Mahdi Kashmiri, Kofi A. A. Makinwa:
Session 3 overview: Analog techniques: Analog subcommittee. 48-49 - Thije Rooijers, Johan H. Huijsing, Kofi A. A. Makinwa:
A quiet digitally assisted auto-zero-stabilized voltage buffer with 0.6pA input current and offset. 50-52 - Ka-Meng Lei, Pui-In Mak, Man-Kay Law, Rui Paulo Martins:
A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state power. 52-54 - Cagri Gurleyuk, Lorenzo Pedala, Fabio Sebastiano, Kofi A. A. Makinwa:
A CMOS Dual-RC frequency reference with ±250ppm inaccuracy from -45°C to 85°C. 54-56 - Eric Cope, Julian Aschieri, Tony Lai, Franklin Zhao, Walter Grandfield, Michael Clifford, Pete Rathfelder, Qiyuan Liu, Siddartha Kavilipati, Aaron Vandergriff, Gerald Miaille:
A 2×20W 0.0013% THD+N Class-D audio amplifier with consistent performance up to maximum power level. 56-58 - Wen-Chieh Wang, Yu-Hsin Lin:
A 0.0004% (-108dB) THD+N, 112dB-SNR, 3.15W fully differential Class-D audio amplifier with Gm noise cancellation and negative output-common-mode injection techniques. 58-60 - Shih-Hsiung Chien, Yi-Wen Chen, Tai-Haur Kuo:
A 0.96mA quiescent current, 0.0032% THD+N, 1.45W Class-D audio amplifier with area-efficient PWM-residual-aliasing reduction. 60-62 - Shinwoong Park, Dongseok Shin, Kwang-Jin Koh, Sanjay Raman:
A low-power 3.25GS/s 4th-order programmable analog FIR filter using split-CDAC coefficient multipliers for wideband analog signal processing. 62-64 - Chun-Huat Heng, David McLaurin, Stefano Pellerano:
Session 4 overview: mm-Wave radios for 5G and beyond: Wireless subcommittee. 64-65 - Tirdad Sowlati, Saikat Sarkar, Bevin G. Perumana, Wei Liat Chan, Bagher Afshar, Michael Boers, Donghyup Shin, Timothy Mercer, Wei-Hong Chen, Anna Papio Toda, Alfred Grau Besoli, Seunghwan Yoon, Sissy Kyriazidou, Phil Yang, Vipin Aggarwal, Nooshin Vakilian, Dmitriy Rozenblit, Masoud Kahrizi, Joy Zhang, Alan Wang, Padmanava Sen, David Murphy, Mohyee Mikhemar, Ali Sajjadi, Alireza Tarighat Mehrabani, Brima Ibrahim, Bo Pan, Kevin Juan, Shelley Xu, Claire Guan, Guy Geshvindman, Khim Low, Namik Kocaman, Hans Eberhart, Koji Kimura, Igor Elgorriaga, Vincent Roussel, Hongyu Xie, Leo Shi, Venkat Kodavati:
A 60GHz 144-element phased-array transceiver with 51dBm maximum EIRP and ±60° beam steering for backhaul application. 66-68 - Min-Yu Huang, Taiyun Chi, Fei Wang, Tso-Wei Li, Hua Wang:
A 23-to-30GHz hybrid beamforming MIMO receiver array with closed-loop multistage front-end beamformers for full-FoV dynamic and autonomous unknown signal tracking and blocker rejection. 68-70 - Jeremy D. Dunworth, Aliakbar Homayoun, Bon-Hyun Ku, Yu-Chin Ou, Kaushik Chakraborty, Gang Liu, Tony Segoria, Jongrit Lerdworatawee, Joung Won Park, Hyun-Chul Park, Hajir Hedayati, David Lu, Paul Monat, Keith Douglas, Vladimir Aparin:
A 28GHz Bulk-CMOS dual-polarization phased-array transceiver with 24 channels for 5G user and basestation equipment. 70-72 - Susnata Mondal, Rahul Singh, Jeyanandh Paramesh:
A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation. 72-74 - Shahriar Shahramian, Mike Holyoak, Amit Singh, Bahar Jalali Farahani, Yves Baeyens:
A fully integrated scalable W-band phased-array module with integrated antennas, self-alignment and self-test. 74-76 - Taiyun Chi, Jong Seok Park, Sensen Li, Hua Wang:
A 64GHz full-duplex transceiver front-end with an on-chip multifeed self-interference-canceling antenna and an all-passive canceler supporting 4Gb/s modulation in one antenna footprint. 76-78 - Hayato Wakabayashi, Makoto Ikeda:
Session 5 overview: Image sensors: IMMD subcommittee. 78-79 - Masaki Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, Katsumi Honda, Hidekazu Kikuchi, Takuya Wada, Yasunobu Kamikubo, Tsukasa Miura, Masahiko Nakamizo, Naoki Jyo, Ryo Hayashibara, Yohei Furukawa, Shinya Miyata, Satoshi Yamamoto, Yoshiyuki Ota, Hirotsugu Takahashi, Tadayuki Taura, Yusuke Oike, Keiji Tatani, Takashi Nagano, Takayuki Ezaki, Teruo Hirayama:
A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC. 80-82 - Kazuko Nishimura, Sanshiro Shishido, Yasuo Miyake, Masaaki Yanagida, Yoshiaki Satou, Makoto Shouho, Hidenari Kanehara, Ryota Sakaida, Yoshihiro Sato, Junji Hirase, Yuko Tomekawa, Yutaka Abe, Hiroshi Fujinaka, Yoshiyuki Matsunaga, Masashi Murakami, Mitsuru Harada, Yasunori Inoue:
An 8K4K-resolution 60fps 450ke--saturation-signal organic-photoconductive-film global-shutter CMOS image sensor with in-pixel noise canceller. 82-84 - Yitae Kim, Wonchul Choi, Donghyuk Park, Heegeun Jeoung, Bumsuk Kim, Youngsun Oh, Sunghoon Oh, Byungjun Park, Euiyeol Kim, Yunki Lee, Taesub Jung, Yongwoon Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang:
A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation. 84-86 - Oichi Kumagai, Atsumi Niwa, Katsuhiko Hanzawa, Hidetaka Kato, Shinichiro Futami, Toshio Ohyama, Tsutomu Imoto, Masahiko Nakamizo, Hirotaka Murakami, Tatsuki Nishino, Anas Bostamam, Takahiro Iinuma, Naoki Kuzuya, Kensuke Hatsukawa, Frederick T. Brady, William Bidermann, Toshifumi Wakano, Takashi Nagano, Hayato Wakabayashi, Yoshikazu Nitta:
A 1/4-inch 3.9Mpixel low-power event-driven back-illuminated stacked CMOS image sensor. 86-88 - Po-Sheng Chou, Chin-Hao Chang, Manoj M. Mhala, Charles Chih-Min Liu, Calvin Yi-Ping Chao, Chiao-Yi Huang, Honyih Tu, Thomas Meng-Hsiu Wu, Shang-Fu Yeh, Seiji Takahashi, Yi-Min Huang:
A 1.1μm-Pitch 13.5Mpixel 3D-stacked CMOS image sensor featuring 230fps full-high-definition and 514fps high-definition videos by reading 2 or 3 rows simultaneously using a column-switching matrix. 88-90 - Toshio Yasue, Kohei Tomioka, Ryohei Funatsu, Tomohiro Nakamura, Takahiro Yamasaki, Hiroshi Shimamoto, Tomohiko Kosugi, Sung-Wook Jun, Takashi Watanabe, Masanori Nagase, Toshiaki Kitajima, Satoshi Aoyama, Shoji Kawahito:
A 33Mpixel CMOS imager with multi-functional 3-stage pipeline ADC for 480fps high-speed mode and 120fps low-noise mode. 90-92 - Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiro Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto:
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. 92-94 - Cyrus S. Bamji, Swati Mehta, Barry Thompson, Tamer A. Elkhatib, Stefan Wurster, Onur Can Akkaya, Andrew D. Payne, John P. Godbaz, Mike Fenton, Vijay Rajasekaran, Larry Prather, Satya Nagaraja, Vishali Mogallapu, Dane Snow, Rich McCauley, Mustansir Mukadam, Iskender Agi, Shaun McCarthy, Zhanping Xu, Travis Perry, William Qian, Vei-Han Chan, Prabhu Adepu, Gazi Ali, Muneeb Ahmed, Aditya Mukherjee, Sheethal Nayak, Dave Gampell, Sunil Acharya, Lou Kordus, Patrick O'Connor:
IMpixel 65nm BSI 320MHz demodulated TOF Image sensor with 3μm global shutter pixels and analog binning. 94-96 - Augusto Ronchini Ximenes, Preethi Padmanabhan, Myung-Jae Lee, Yuichiro Yamashita, Dun-Nian Yaung, Edoardo Charbon:
A 256×256 45/65nm 3D-stacked SPAD-based direct TOF image sensor for LiDAR applications with optical polar modulation for up to 18.6dB interference suppression. 96-98 - Leonardo Gasparini, Majid Zarghami, Hesong Xu, Luca Parmesan, Manuel Moreno Garcia, Manuel Unternährer, Bänz Bessire, André Stefanov, David Stoppa, Matteo Perenzoni:
A 32×32-pixel time-resolved single-photon image sensor with 44.64μm pitch and 19.48% fill-factor with on-chip row/frame skipping features reaching 800kHz observation rate for quantum physics applications. 98-100 - Mounir Meghelli, Hyeon-Min Bae, Frank O'Mahony:
Session 6 overview: Ultra-high-speed wireline: Wireline subcommittee. 100-101 - Jihwan Kim, Ajay Balankutty, Rajeev K. Dokania, Amr Elshazly, Hyung Seok Kim, Sandipan Kundu, Skyler Weaver, Kai Yu, Frank O'Mahony:
A 112Gb/s PAM-4 transmitter with 3-Tap FFE in 10nm CMOS. 102-104 - Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Alessandro Cevrero, Marcel A. Kossel, Lukas Kull, Danny Luu, Ilter Özkaya, Thomas Toifl:
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. 104-106 - Mohammad Sadegh Jalali, Mohammad Hossein Taghavi, Angus McLaren, Jennifer Pham, Kamran Farzan, Dominic DiClemente, Marcus van Ierssel, William Song, Saman Asgaran, Chris D. Holdenried, Saman Sadr:
A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support. 106-108 - Parag Upadhyaya, Chi Fung Poon, Siok-Wei Lim, Junho Cho, Arianne Roldan, Wenfeng Zhang, Jin Namkoong, Toan Pham, Bruce Xu, Winson Lin, Hongtao Zhang, Nakul Narang, Kee Hian Tan, Geoff Zhang, Yohan Frans, Ken Chang:
A fully adaptive 19-to-56Gb/s PAM-4 wireline transceiver with a configurable ADC in 16nm FinFET. 108-110 - Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, Anthony Chan Carusone:
A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET. 110-112 - Emanuele Depaoli, Enrico Monaco, Giovanni Steffan, Marco Mazzini, Hongyang Zhang, Walter Audoglio, Oscar Belotti, Augusto Andrea Rossi, Guido Albasini, Massimo Pozzoni, Simone Erba, Andrea Mazzanti:
A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS. 112-114 - Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He:
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. 114-116 - Youngmin Shin, Phillip J. Restle, Edith Beigné:
Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. 116-117 - Shiheng Yang, Jun Yin, Pui-In Mak, Rui Paulo Martins:
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. 118-120 - Kangyeop Choo, Hyunik Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hyung Jong Ko:
A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology. 120-122 - Minseob Lee, Shinwoong Kim, Hwasuk Cho, Jahyun Koo, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC. 122-124 - Anvesha Amaravati, Saad Bin Nasir, Sivaram Thangadurai, Insik Yoon, Arijit Raychowdhury:
A 55nm time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robots. 124-126 - Wen-Hau Yang, Li-Cheng Chu, Shang-Hsien Yang, Yan-Jiun Lai, Shao-Qi Chen, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
An enhanced-security buck DC-DC converter with true-random-number-based pseudo hysteresis controller for internet-of-everything (IoE) Devices. 126-128 - Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai:
A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD. 128-130 - Meng-Yi Wu, Tsao-Hsin Yang, Lun-Chun Chen, Chi-Chang Lin, Hao-Chun Hu, Fang-Ying Su, Chih-Min Wang, James Po-Hao Huang, Hsin-Ming Chen, Chris Chun-Hung Lu, Evans Ching-Song Yang, Rick Shih-Jye Shen:
A PUF scheme using competing oxide rupture with bit error rate approaching zero. 130-132 - Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee:
A 445F2 leakage-based physically unclonable Function with Lossless Stabilization Through Remapping for IoT Security. 132-134 - Yuan Gao, Zhiliang Hong, Axel Thomsen:
Session 8 overview: Wireless power and harvesting: Power management subcommittee. 134-135 - Kamala Raghavan Sadagopan, Jian Kang, Yogesh Ramadass, Arun Natarajan:
A 960pW Co-Integrated-Antenna Wireless Energy Harvester for WiFi Backchannel Wireless Powering. 136-138 - Che-Hao Yeh, Yen-Ting Lin, Chun-Chieh Kuo, Chao-Jen Huang, Cheng-Yu Xie, Shen-Fu Lu, Wen-Hau Yang, Ke-Horng Chen, Kuo-Chi Liu, Ying-Hsi Lin:
A 70W and 90% GaN-based class-E wireless-power-transfer system with automatic-matching-point-search control for zero-voltage switching and zero-voltage-derivative switching. 138-140 - Fangyu Mao, Yan Lu, Seng-Pan U., Rui Paulo Martins:
A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency. 140-142 - Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, Chuanjin Richard Shi:
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. 142-144 - Sally Safwat Amin, Patrick P. Mercier:
MISIMO: A multi-input single-inductor multi-output energy harvester employing event-driven MPPT control to achieve 89% peak efficiency and a 60, 000x dynamic range in 28nm FDSOI. 144-146 - Inho Park, Junyoung Maeng, Dongju Lim, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A 4.5-to-16μW integrated triboelectric energy-harvesting system based on high-voltage dual-input buck converter with MPPT and 70V maximum input voltage. 146-148 - Yifeng Cai, Yiannos Manoli:
A piezoelectric energy-harvesting interface circuit with fully autonomous conjugate impedance matching, 156% extended bandwidth, and 0.38μW power consumption. 148-150 - Anthony Quelen, Adrien Morel, Pierre Gasnier, Romain Grezaud, Stéphane Monfray, Gaël Pillonnet:
A 30nA quiescent 80nW-to-14mW power-range shock-optimized SECE-based piezoelectric harvesting interface with 420% harvested-energy improvement. 150-152 - Sijun Du, Ashwin A. Seshia:
A fully integrated split-electrode synchronized-switch-harvesting-on-capacitors (SE-SSHC) rectifier for piezoelectric energy harvesting with between 358% and 821% power-extraction enhancement. 152-154 - Se-un Shin, Minseong Choi, Seok-Tae Koh, Yu-Jin Yang, Seungchul Jung, Young-Hoon Sohn, Se-Hong Park, Yong-Min Ju, Youngsin Jo, Yeunhee Huh, Sung-Won Choi, Sang Joon Kim, Gyu-Hyeong Cho:
A 13.56MHz time-interleaved resonant-voltage-mode wireless-power receiver with isolated resonator and quasi-resonant boost converter for implantable systems. 154-156 - Alan Wong, Xin He, Stefano Pellerano:
Session 9 overview: Wireless transceivers and techniques: Wireless subcommittee. 156-157 - Brian P. Ginsburg, Karthik Subburaj, Sreekiran Samala, Karthik Ramasubramanian, Jasbir Singh, Sumeer Bhatara, Sriram Murali, Dan Breen, Meysam Moallem, Krishnanshu Dandu, Saket Jalan, Neeraj P. Nayak, Rittu Sachdev, Indu Prathapan, Karan Bhatia, Tim Davis, Eunyoung Seok, Harikrishna Parthasarathy, Rohit Chatterjee, Venkatesh Srinivasan, Vito Giannini, Anil Kumar, Ross Kulak, Shankar Ram, Pankaj Gupta, Zahir Parkar, Sachin Bhardwaj, Y. C. Rakesh, K. A. Rajagopal, Arun Shrimali, Vijay Rentala:
A multimode 76-to-81GHz automotive radar transceiver with autonomous monitoring. 158-160 - Liheng Lou, Kai Tang, Bo Chen, Ting Guo, Yisheng Wang, Wensong Wang, Zhongyuan Fang, Zhe Liu, Yuanjin Zheng:
A 253mW/channel 4TX/4RX pulsed chirping phased-array radar TRX in 65nm CMOS for X-band synthetic-aperture radar imaging. 160-162 - David J. McLaurin, Kevin G. Gard, Richard P. Schubert, Manish J. Manglani, Haiyang Zhu, David Alldred, Zhao Li, Steven R. Bal, Jianxun Fan, Oliver E. Gysel, Christopher M. Mayer, Tony Montalvo:
A highly reconfigurable 65nm CMOS RF-to-bits transceiver for full-band multicarrier TDD/FDD 2G/3G/4G/5G macro basestations. 162-164 - Shinwon Kang, Chintan Thakkar, Nathan Narevsky, Kaushik Dasgupta, Saeid Daneshgar, James E. Jaussi, Bryan Casper:
A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO. 164-166 - Saeid Daneshgar, Kaushik Dasgupta, Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper:
A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO. 166-168 - Korkut Kaan Tokgoz, Shotaro Maki, Jian Pang, Noriaki Nagashima, Ibrahim Abdo, Seitaro Kawai, Takuya Fujimura, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa:
A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. 168-170 - Kun-Da Chu, Mohamad Katanbaf, Tong Zhang, Chenxin Su, Jacques Christophe Rudell:
A broadband and deep-TX self-interference cancellation technique for full-duplex and frequency-domain-duplex transceiver applications. 170-172 - Qing Liu, Dae Hyun Kwon, Quang-Diep Bui, Jeong-Hyun Choi, Jaehun Lee, Sanghyun Baek, Seungchan Heo, Thomas Byunghak Cho:
A 1.4-to-2.7GHz high-efficiency RF transmitter with an automatic 3FLO-suppression tracking-notch-filter mixer supporting HPUE in 14nm FinFET CMOS. 172-174 - Bagher Rabet, James F. Buckwalter:
A high-efficiency 28GHz outphasing PA with 23dBm output power using a triaxial balun combiner. 174-176 - Michael Kraft, Masayuki Miyamoto, Makoto Ikeda:
Session 10 overview: Sensor systems: IMMD subcommittee. 176-177 - Burak Eminoglu, Bernhard E. Boser:
Chopped rate-to-digital FM gyroscope with 40ppm scale factor accuracy and 1.2dph bias. 178-180 - Qingbo Guo, William Deng, Ozkan Bebek, Murat Cenk Cavusoglu, Carlos H. Mastrangelo, Darrin J. Young:
Personal inertial navigation system employing MEMS wearable ground reaction sensor array and interface ASIC achieving a position accuracy of 5.5m over 3km walking distance without GPS. 180-182 - Jae-Sung An, Sang-Hyun Han, Kyeong-Bin Park, Ju Eon Kim, Jae-Hun Ye, Seung-Hwan Lee, Ji-Yong Jeong, Jung Soo Kim, Kwang-Hyun Baek, Ki-Seok Chung, Seong-Kwan Hong, Oh-Kyong Kwon:
Multi-way interactive capacitive touch system with palm rejection of active stylus for 86" touch screen panels. 182-184 - Kyung-Hoon Lee, Sang-Pil Nam, Jung-Ho Lee, Michael Choi, Hyung-Jong Ko, San-Ho Byun, Jin-chul Lee, Yong-Hoon Lee, Yeong-Cheol Rhee, Yoon-Kyung Choi, Byunghoon Kang, Changbyung Park, Sungsoo Park, Taesung Kim:
A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active styluses. 184-186 - Chao Chen, Zhao Chen, Deep Bera, Emile Noothout, Zu-yao Chang, Mingliang Tan, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs:
A 0.91mW/element pitch-matched front-end ASIC with integrated subarray beamforming ADC for miniature 3D ultrasound probes. 186-188 - Gwangrok Jung, M. Wasequr Rashid, Thomas M. Carpenter, Coskun Tekes, David M. J. Cowell, Steven Freear, F. Levent Degertekin, Maysam Ghovanloo:
Single-chip reduced-wire active catheter system with programmable transmit beamforming and receive time-division multiplexing for intracardiac echocardiography. 188-190 - Constantine Sideris, Parham Porsandeh Khial, Bill Ling, Ali Hajimiri:
A 0.3ppm dual-resonance transformer-based drift-cancelling reference-free magnetic sensor for biosensing applications. 190-192 - Kiduk Kim, Seunghyun Park, Kye-Seok Yoon, Gyeong-Gu Kang, Hyun-Ki Han, Ji-Su Choi, Min-Woo Ko, Jeong-Hyun Cho, Sangjin Lim, Hyung-Min Lee, Hyunsik Kim, Kwyro Lee, Gyu-Hyeong Cho:
A 100mK-NETD 100ms-startup-time 80×60 micro-bolometer CMOS thermal imager integrated with a 0.234mm2 1.89μVrms noise 12b biasing DAC. 192-194 - Jonathan Chang, Chun Shiah, Leland Chang:
Session 11 overview: SRAM: Memory subcommittee. 194-195 - Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl:
A 23.6Mb/mm2 SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications. 196-198 - Taejoong Song, Jonghoon Jung, Woojin Rim, Hoonki Kim, Yongho Kim, Changnam Park, Jeongho Do, Sunghyun Park, Sungwee Cho, Hyuntaek Jung, Bongjae Kwon, Hyun-Su Choi, Jaeseung Choi, Jong Shik Yoon:
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. 198-200 - Michael Clinton, Rajinder Singh, Marty Tsai, Shayan Zhang, Bryan Sheffield, Jonathan Chang:
A 5GHz 7nm L1 cache memory compiler for high-speed computing and mobile applications. 200-201 - Seung-Jun Bae, Wolfgang Spirkl, Leland Chang:
Session 12 overview: DRAM: Memory subcommittee. 202-203 - Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, ChanYong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. 204-206 - Ki Chul Chun, Yonggyu Chu, Jin-Seok Heo, Tae-Sung Kim, Soohwan Kim, Hui-Kap Yang, Mi-Jo Kim, Chang-Kyo Lee, Ju-Hwan Kim, Hyunchul Yoon, Chang-Ho Shin, Sang-uhn Cha, Hyung-Jin Kim, Young-Sik Kim, Kyungryun Kim, Young-Ju Kim, Won-Jun Choi, Daesik Yim, Inkyu Moon, Young-Ju Kim, Junha Lee, Young Choi, Yongmin Kwon, Sung-Won Choi, Jung-Wook Kim, Yoon-Suk Park, Woongdae Kang, Jinil Chung, Seunghyun Kim, Yesin Ryu, Seong-Jin Cho, Hoon Shin, Hangyun Jung, Sanghyuk Kwon, Kyuchang Kang, Jongmyung Lee, Yujung Song, Youngjae Kim, Eun-Ah Kim, Kyung-Soo Ha, Kyoung-Ho Kim, Seok-Hun Hyun, Seung-Bum Ko, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. 206-208 - Jin-Hee Cho, Jihwan Kim, Wooyoung Lee, Dong-Uk Lee, Tae-Kyun Kim, Heat Bit Park, Chunseok Jeong, Myeong-Jae Park, Seung Geun Baek, Seokwoo Choi, Byung Kuk Yoon, Young Jae Choi, Kyo Yun Lee, Daeyong Shim, Jonghoon Oh, Jinkook Kim, Seok-Hee Lee:
A 1.2V 64Gb 341GB/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control. 208-210 - Kyu-Dong Hwang, Boram Kim, Sang-Yeon Byeon, Kyu-Young Kim, Dae-Han Kwon, Hyun-Bae Lee, Geun-Il Lee, Sang-Sic Yoon, Jin-Youp Cha, Soo-Young Jang, Seung-Hun Lee, Yongsuk Joo, Gang-Sik Lee, Sung-Soo Xi, Soo-Bin Lim, Kyung-Ho Chu, Joohwan Cho, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee:
A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications. 210-212 - Seokbo Shim, Sungho Kim, Jooyoung Bae, Keunsik Ko, Eunryeong Lee, Kwidong Kim, Kyeongtae Kim, Sangho Lee, Jinhoon Hyun, Insung Koh, Joonhong Park, Minjeong Kim, Sunhye Shin, Dongha Lee, Yunyoung Lee, Sangah Hyun, Wonjohn Choi, Dain Im, Dongheon Lee, Jieun Jang, Sangho Lee, Junhyun Chun, Jonghoon Oh, Jinkook Kim, Seok Hee Lee:
A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy. 212-214 - Dejan Markovic, Masato Motomura, Byeong-Gyu Nam:
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee. 214-215