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ORCIDCheng-Wen Wu
Person information
- affiliation: Southern Taiwan University of Science and Technology, Tainan, Taiwan
- affiliation (1988 - 2023): National Tsing Hua University, Hsinchu, Taiwan
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2020 – today
- 2024
[c164]Cheng-Wen Wu, Shi-Yu Huang:
Keynote 2 - Sustainability and the Outlook of Semiconductor Industry. ETS 2024: 1-2- 2023
- [j88]Pai-Yu Tan
, Cheng-Wen Wu:
A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 1994-2007 (2023) - [c163]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Slimane Boutobza, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC 2023: 1-6 - [c162]Pai-Yu Tan, Cheng-Wen Wu:
A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks. ASP-DAC 2023: 651-656 - [c161]Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS 2023: 1-6 - 2022
- [j87]Wei-Han Chen, Yang-Chih Feng, Ming-Chia Yeh, Hsi-Pin Ma, Chiang Liu, Cheng-Wen Wu:
Impact Position Estimation for Baseball Batting with a Force-Irrelevant Vibration Feature. Sensors 22(4): 1553 (2022) - [j86]Cheng-Wen Wu, Ming-Der Shieh, Jenn-Jier James Lien, Jar-Ferr Yang, Wei-Ta Chu, Tsang-Hai Huang, Han-Chuan Hsieh, Hung-Ta Chiu, Kuo-Cheng Tu, Yen-Ting Chen, Shian-Yu Lin, Jia-Jun Hu, Chen-Huan Lin, Cheng-Siang Jheng:
Enhancing Fan Engagement in a 5G Stadium With AI-Based Technologies and Live Streaming. IEEE Syst. J. 16(4): 6590-6601 (2022) - [c160]Kuan-Hsun Duh, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen, Ming-Yan Fan:
Aging Impact of Power MOSFETs in Charger with Different Operation Frequency. ATS 2022: 54-59 - [c159]Yu-You Chou, Cheng-Wen Wu, Ming-Der Shieh, Chao-Hsun Chen:
Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration. ATS 2022: 66-71 - [c158]Kuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu, Juin-Ming Lu:
Fault Modeling and Testing of Memristor-Based Spiking Neural Networks. ITC 2022: 92-99 - [c157]Ya-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao:
Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method. ITC 2022: 601-608 - [c156]Ya-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao:
A Decision Tree-Based Screening Method for Improving Test Quality of Memory Chips. ITC-Asia 2022: 19-24 - [c155]Shian-Yu Lin, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao:
Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability. ITC-Asia 2022: 25-30 - [c154]Pai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao:
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. VLSI-DAT 2022: 1-4 - [c153]Hong-Hao Wang, Po-Yao Chuang, Cheng-Wen Wu:
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime. VLSI-DAT 2022: 1-4 - 2021
- [j85]Yu-Rong Jian, Ferenc Fodor, Cheng-Wen Wu, Erik Jan Marinissen:
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization. IEEE Des. Test 38(5): 82-89 (2021) - [c152]Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu:
An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. DATE 2021: 575-580 - 2020
- [c151]Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu:
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. DAC 2020: 1-6 - [c150]Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen:
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. ETS 2020: 1-6 - [c149]Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang:
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC 2020: 1-9 - [c148]Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang:
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia 2020: 13-18 - [i2]Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu:
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. CoRR abs/2003.06310 (2020)
2010 – 2019
- 2019
- [j84]Cheng-Wen Wu:
The Last Byte: Baseball and Testing. IEEE Des. Test 36(6): 88 (2019) - [c147]Michiko Inoue, Xiaowei Li, Cheng-Wen Wu:
Asian Test Symposium - Past, Present and Future -. ITC 2019: 1-4 - 2018
- [c146]Ying-Cih Kao, Cheng-Wen Wu:
A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning. ACSSC 2018: 2060-2064 - [c145]Meng-Chi Chen, Tsung-Hsuan Wu, Cheng-Wen Wu:
A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit. ATS 2018: 19-24 - [c144]Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen:
Covering hard-to-detect defects by thermal quorum sensing. ETS 2018: 1-2 - [c143]Su-Fu Kuo, Cheng-Wen Wu:
Symbiotic Controller Design Using a Memory-Based FSM Model. ISIE 2018: 874-879 - [c142]Erik Jan Marinissen, Ferenc Fodor, Arnita Podpod, Michele Stucchi, Yu-Rong Jian, Cheng-Wen Wu:
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits. ITC 2018: 1-10 - [c141]Jia-Yun Hu, Kuan-Wei Hou, Chih-Yen Lo, Yung-Fa Chou, Cheng-Wen Wu:
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction. ITC-Asia 2018: 19-24 - 2017
- [j83]Zhi-Yong Liu, Hsiu-Chuan Shih, Bing-Yang Lin, Cheng-Wen Wu:
Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. IEEE Des. Test 34(2): 69-78 (2017) - [j82]Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test 34(3): 50-58 (2017) - [j81]Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers 66(8): 1293-1301 (2017) - [c140]Pok Man Preston Law, Cheng-Wen Wu, Long-Yi Lin, Hao-Chiao Hong:
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. ATS 2017: 5-10 - [c139]Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu:
Highly reliable and low-cost symbiotic IOT devices and systems. ITC 2017: 1-10 - [c138]Po-Yao Chuang, Cheng-Wen Wu, Harry H. Chen:
Cell-aware test generation time reduction by using switch-level ATPG. ITC-Asia 2017: 27-32 - [c137]Cheng-Wen Wu, Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen:
Symbiotic system models for efficient IGT system design and test. ITC-Asia 2017: 71-76 - [c136]Cheng-Wen Wu:
Can IOT make semiconductor great again? VLSI-DAT 2017: 1 - 2016
- [j80]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test 33(2): 30-39 (2016) - [j79]Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers 65(3): 770-780 (2016) - [c135]Hsuan-Wei Liu, Bing-Yang Lin, Cheng-Wen Wu:
Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. ATS 2016: 156-160 - [c134]Harry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu:
Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation. ATS 2016: 197-202 - [c133]Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC 2016: 58:1-58:6 - [c132]Sin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu:
A fast sweep-line-based failure pattern extractor for memory diagnosis. ETS 2016: 1-6 - [c131]Cheng-Wen Wu:
Is IoT coming to the rescue of semiconductor? ETS 2016: 1 - 2015
- [j78]Wei-Chung Cheng, I-Fang Chung, Cheng-Fong Tsai, Tse-Shun Huang, Chen-Yang Chen, Shao-Chuan Wang, Ting-Yu Chang, Hsing-Jen Sun, Jeffrey Yung-Chuan Chao, Cheng-Chung Cheng, Cheng-Wen Wu, Hsei-Wei Wang:
YM500v2: a small RNA sequencing (smRNA-seq) database for human cancer miRNome research. Nucleic Acids Res. 43(Database-Issue): 862-867 (2015) - [c130]Bing-Yang Lin, Cheng-Wen Wu, Harry H. Chen:
System-level test coverage prediction by structural stress test data mining. VLSI-DAT 2015: 1-4 - [c129]Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu:
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC 2015: 186- - 2014
- [j77]Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng:
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test 31(4): 16-26 (2014) - [j76]Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, Cheng-Wen Wu:
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1356-1369 (2014) - [j75]Yen-Lin Peng, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 207-219 (2014) - [j74]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2388-2401 (2014) - [c128]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - [c127]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang:
Redundancy architectures for channel-based 3D DRAM yield improvement. ITC 2014: 1-7 - 2013
- [j73]Po-Yuan Chen, Chin-Lung Su, Chao-Hsun Chen, Cheng-Wen Wu:
Generalization of an Enhanced ECC Methodology for Low Power PSRAM. IEEE Trans. Computers 62(7): 1318-1331 (2013) - [j72]Yung-Fa Chou, Ding-Ming Kwai, Ming-Der Shieh, Cheng-Wen Wu:
Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(9): 2343-2351 (2013) - [j71]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Ching-Cheng Tien, Chi-Hu Wang, Cheng-Wen Wu:
AC-Plus Scan Methodology for Small Delay Testing and Characterization. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 329-341 (2013) - [j70]Jhih-Wei You, Shi-Yu Huang, Yu-Hsiang Lin, Meng-Hsiu Tsai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 443-453 (2013) - [j69]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting Cheng, Cheng-Wen Wu:
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 465-474 (2013) - [j68]Ching-Yi Chen, Sheng-Hung Wang, Cheng-Wen Wu:
Write Current Self-Configuration Scheme for MRAM Yield Improvement. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1260-1270 (2013) - [c126]Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, Jen-Chieh Yeh, Cheng-Wen Wu:
Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs. ASP-DAC 2013: 429-434 - [c125]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu:
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium 2013: 1-6 - [c124]Hsiu-Chuan Shih, Cheng-Wen Wu:
An enhanced double-TSV scheme for defect tolerance in 3D-IC. DATE 2013: 1486-1489 - [c123]Cheng-Wen Wu:
Holistic approach to low-power system design. ISLPED 2013: 2 - [c122]Yuriy Shiyanovskii, Christos A. Papachristou, Cheng-Wen Wu:
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs. ISQED 2013: 24-29 - [c121]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c120]Chih-Sheng Hou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
An FPGA-based test platform for analyzing data retention time distribution of DRAMs. VLSI-DAT 2013: 1-4 - [c119]Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin:
3D-IC interconnect test, diagnosis, and repair. VTS 2013: 1-6 - [c118]Jin-Fu Li, Cheng-Wen Wu, Masahiro Aoyagi, Meng-Fan Marvin Chang, Ding-Ming Kwai:
Special session 4C: Hot topic 3D-IC design and test. VTS 2013: 1 - [c117]Yun-Chao You, Chih-Sheng Hou, Li-Jung Chang, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs. VTS 2013: 1-6 - 2012
- [c116]Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li:
On test and repair of 3D random access memory. ASP-DAC 2012: 744-749 - [c115]Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang:
A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC 2012: 1-9 - [c114]Yun-Chao You, Che-Wei Chou, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for 3D RAMs. ITC 2012: 1-9 - [c113]Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin:
3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT 2012: 1-4 - [c112]Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu:
Cost modeling and analysis for interposer-based three-dimensional IC. VTS 2012: 108-113 - [c111]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu:
A Memory Failure Pattern Analyzer for memory diagnosis and repair. VTS 2012: 234-239 - 2011
- [j67]Mincent Lee, Li-Ming Denq, Cheng-Wen Wu:
A Memory Built-In Self-Repair Scheme Based on Configurable Spares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 919-929 (2011) - [j66]Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu:
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1346-1356 (2011) - [j65]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu:
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2184-2194 (2011) - [c110]Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu:
A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718 - [c109]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. Asian Test Symposium 2011: 451-456 - [c108]Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776 - [c107]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
DfT Architecture for 3D-SICs with Multiple Towers. ETS 2011: 51-56 - [c106]Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. ITC 2011: 1-10 - [c105]Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25 - [c104]Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu:
Training-based forming process for RRAM yield improvement. VTS 2011: 146-151 - [c103]Cheng-Wen Wu:
Special session: Hot topic design and test of 3D and emerging memories. VTS 2011: 328 - 2010
- [j64]Yu-Tsao Hsing, Li-Ming Denq, Chao-Hsun Chen, Cheng-Wen Wu:
Economic Analysis of the HOY Wireless Test Methodology. IEEE Des. Test Comput. 27(3): 20-30 (2010) - [j63]Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu:
Built-In Self-Repair Schemes for Flash Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1243-1256 (2010) - [j62]Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Denq, Cheng-Wen Wu:
SOC Test Architecture and Method for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1645-1649 (2010) - [j61]Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu:
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 184-193 (2010) - [j60]Mao-Yin Wang, Chih-Pin Su, Chia-Lung Horng, Cheng-Wen Wu, Chih-Tsun Huang:
Single- and Multi-core Configurable AES Architectures for Flexible Security. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 541-552 (2010) - [j59]Chen-Hsing Wang, Chieh-Lin Chuang, Cheng-Wen Wu:
An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 553-563 (2010) - [j58]Mao-Yin Wang, Cheng-Wen Wu:
A Mesh-Structured Scalable IPsec Processor. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 725-731 (2010) - [j57]Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao:
Diagnosis of MRAM Write Disturbance Fault. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1762-1766 (2010) - [c102]Jin-Fu Li, Cheng-Wen Wu:
Is 3D integration an opportunity or just a hype? ASP-DAC 2010: 541-543 - [c101]Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium 2010: 377-382 - [c100]Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. Asian Test Symposium 2010: 389-394 - [c99]Hsiu-Ming Chang, Jiun-Lang Huang, Ding-Ming Kwai, Kwang-Ting (Tim) Cheng, Cheng-Wen Wu:
An error tolerance scheme for 3D CMOS imagers. DAC 2010: 917-922 - [c98]Sheng-Hung Wang, Ching-Yi Chen, Cheng-Wen Wu:
Fast identification of operating current for toggle MRAM by spiral search. DAC 2010: 923-928 - [c97]Ching-Yi Chen, Cheng-Wen Wu:
An adaptive code rate EDAC scheme for random access memory. DATE 2010: 735-740 - [c96]Tsung-Yeh Li, Shi-Yu Huang, Hsuan-Jung Hsu, Chao-Wen Tzeng, Chih-Tsun Huang, Jing-Jia Liou, Hsi-Pin Ma, Po-Chiun Huang, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Mike Wang:
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects. DFT 2010: 340-348 - [c95]Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li:
A low-cost and scalable test architecture for multi-core chips. ETS 2010: 30-35 - [c94]Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai:
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding. VTS 2010: 263-268
2000 – 2009
- 2009
- [j56]Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu:
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. IEEE Des. Test Comput. 26(2): 64-73 (2009) - [c93]Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu:
Test Integration for SOC Supporting Very Low-Cost Testers. Asian Test Symposium 2009: 287-292 - [c92]Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai:
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification. Asian Test Symposium 2009: 450-455 - [c91]Te-Hsuan Chen, Yu-Ying Hsiao, Yu-Tsao Hsing, Cheng-Wen Wu:
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. VTS 2009: 53-58 - 2008
- [j55]