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ORCIDMTDT 2005: Taipei, Taiwan
- 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan. IEEE Computer Society 2005, ISBN 0-7695-2313-7
Invited Talks
- Bruce McGaughy, S. Wünsche, K. K. Hung:
Advanced simulation technology and its application in memory design and verification. xv-xx - Serguei Okhonin, Pierre Fazan, Mark-Eric Jones:
Zero capacitor embedded memory technology for system on chip. xxi-xxv
Session T1: Nonvolatile Memory
- Kung-Hong Lee, Shih-Chen Wang, Ya-Chin King:
Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory. 3-8 - Matthew J. Breitwisch, Chung Hon Lam, Jeffrey B. Johnson, Steven W. Mittl, Jian W. Zhu:
A novel CMOS compatible embedded nonvolatile memory with zero process adder. 9-12 - Ching-Yuan Lin, Chung-Hung Lin, Chien-Hung Ho, Wei-Wu Liao, Shu-Yueh Lee, Ming-Chou Ho, Shih-Chen Wang, Shih-Chan Huang, Yuan-Tai Lin, Charles Ching-Hsiang Hsu:
Embedded OTP fuse in CMOS logic process. 13-15 - Meng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai:
Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique. 16-21 - Star Sung, Thomas Chang, Juei Lung Chen:
A nor-type MLC ROM with novel sensing scheme for embedded applications. 22-25
Session T2: New Memory Device
- Simon C. Li, J. P. Su, T.-H. Wu, J. M. Lee, M. F. Shu:
Dielectric tunnel parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM applications. 29-34 - Meng-Yi Wu, Shin-Chang Feng, Ya-Chin King:
A novel single poly-silicon EEPROM using trench floating gate. 35-37 - Kamlesh R. Raiter, Bruce F. Cockburn:
An investigation into three-level ferroelectric memory. 38-43
Session T3: Design and Test of DRAM
- Valerie Lines, Robert McKenzie, Hakjune Oh, Hong-Beom Pyeon, Matthew Dunn, Susan Palapar, Susan Coleman, Peter Nyasulu, Tony Mai, Seanna Pike, John McCready, Jody Defazio, Jin-Ki Kim, Robert Penchuk, Zvika Greenfield, Fredy Lange, Alberto Mandler, Eric C. Jones, Matthew Silverstein:
A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability. 47-51 - Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee:
A high speed BIST architecture for DDR-SDRAM testing. 52-57 - Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
A programmable built-in self-test for embedded DRAMs. 58-63
Session T4: Built-In Self-Test
- Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy:
Full-speed field programmable memory BIST supporting multi-level looping. 67-71 - Po-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang:
FSM-based programmable memory BIST with macro command. 72-77 - Yang-Han Lee, Yih-Guang Jan, Jei-Jung Shen, Shian-Wei Tzeng, Ming-Hsueh Chuang, Jheng-Yao Lin:
DFT architecture for a dynamic fault model of the embedded mask ROM of SOC. 78-82 - Wei-Lun Wang, Kuen-Jong Lee:
A complete memory address generator for scan based March algorithms. 83-88 - Amandeep Singh, Debashish Bose, Sandeep Darisala:
Software based in-system memory test for highly available systems. 89-94
Session T5: Memory Test and Repair
- Jen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu
, Chih-Tsun Huang, Chao-Hsun Chen:
A systematic approach to reducing semiconductor memory test time in mass production. 97-102 - Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, Rob Wadsworth:
Impact of stresses on the fault coverage of memory tests. 103-108 - Keiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama:
DFT techniques for memory macro with built-in ECC. 109-114 - Jin-Fu Li, Yu-Jane Huang:
An error detection and correction scheme for RAMs with partial-write function. 115-120 - Shyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang:
A BIRA algorithm for embedded memories with 2D redundancy. 121-126
Session T6: SRAM Design and Characterization
- Chung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang:
Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM. 129-134 - Shin-Pao Cheng, Shi-Yu Huang:
A low-power SRAM design using quiet-bitline architecture. 135-139 - Ching-Hua Hsiao, Ding-Ming Kwai:
Measurement and characterization of 6T SRAM cell current. 140-145 - Chin-Long Wey, Meng-Yao Liu, Shaolei Quan:
Reliability enhancement of CMOS SRAMs. 146-151
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