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ORCID41st VTS 2023: San Diego, CA, USA
- 41st IEEE VLSI Test Symposium, VTS 2023, San Diego, CA, USA, April 24-26, 2023. IEEE 2023, ISBN 979-8-3503-4630-5
- Irith Pomeranz:
Expanding a Pool of Functional Test Sequences to Support Test Compaction. 1-7 - Fabio Pavanello, Elena-Ioana Vatajelu, Alberto Bosio, Thomas Van Vaerenbergh, Peter Bienstman, Benoît Charbonnier, Alessio Carpegna, Stefano Di Carlo, Alessandro Savino
:
Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies. 1-10 - Leon Li, Alex Orailoglu:
Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation. 1-6 - Saidapet Ramesh, Kristofor Dickson, Akshay Jaiswal, Robert Marchese, Kiran Sunny Thota:
Targeted Custom High-Voltage Stress Patterns on Automotive Designs. 1-4 - Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet:
An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware. 1-7 - Ahmet Enis Çetin, Hongyi Pan:
Hybrid Binary Neural Networks: A Tutorial Review. 1-12 - Mingye Li, Yunkun Lin, Sandeep Gupta:
Design for testability (DFT) for RSFQ circuits. 1-7 - Subashini Gopalsamy, Irith Pomeranz:
Fully Deterministic Storage Based Logic Built-In Self-Test. 1-7 - Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos:
Silent Data Errors: Sources, Detection, and Modeling. 1-12 - Gooyoung Kim, Youngseon Moon, Jongmin Kim, Jaeyong Jeong, Eun-Kyoung Kim, Sunghoi Hur:
Kernel Smoothing Technique Based on Multiple-Coordinate System for Screening Potential Failures in NAND Flash Memory. 1-7 - Arjun Chaudhuri, Ching-Yuan Chen, Jonti Talukdar, Krishnendu Chakrabarty:
Functional Test Generation for AI Accelerators using Bayesian Optimization∗. 1-6 - Keqing Ouyang, Minqiang Peng, Yunnong Zhu, Kang Qi, Grigor Tshagharyan, Arun Kumar, Gurgen Harutyunyan, Isaac Wang:
An Efficient External Memory Test Solution: Case Study for HPC Application. 1-4 - Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao:
Outlier Detection for Analog Tests Using Deep Learning Techniques. 1-7 - Fei Su, Eric Zhang, Arjun Chaudhuri, Michael Paulitsch:
Innovation Practices Track: Testability and Dependability of AI Hardware and Autonomous Systems. 1 - V. A. Niranjan, Deepika Neethirajan, Constantinos Xanthopoulos, D. Webster, Amit Nahar, Yiorgos Makris:
Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC Testing. 1-7 - Po-Yao Chuang, Francesco Lorenzelli, Sreejit Chakravarty, Cheng-Wen Wu, Georges G. E. Gielen, Erik Jan Marinissen:
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. 1-6 - Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg:
Refreshing the JTAG Family. 1-7 - Yu-Min Li, Cheng-Yun Hsieh, Yen-Wei Li, James Chien-Mo Li:
Diagnosis of Quantum Circuits in the NISQ Era. 1-7 - Gauri Koli, Liam Nguyen, Jennifer Kitchen:
Architectural Radiation Hardening of CMOS Power Management Circuits through Bias Tuning. 1-8 - Gurumurti Kailaschandra Avhad, Shitin Sahu, Navaneeth Kumar:
Auxiliary State Machine Controlled Autonomous Design Verification Framework. 1-5 - Yu-Teng Nien, Chen-Hong Li, Pei-Yin Wu, Yung-Jheng Wang, Kai-Chiang Wu, Mango C.-T. Chao:
Test Generation for Defect-Based Faults of Scan Flip-Flops. 1-7 - Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri:
Special Session: Approximation and Fault Resiliency of DNN Accelerators. 1-10 - Chun Chen, Jeng-Yu Liao, James Chien-Mo Li, Harry H. Chen, Eric Jia-Wei Fang:
Vmin Prediction Using Nondestructive Stress Test. 1-7 - Judy Amanor-Badu, Ritchie Rice, Azizi Shuma, Rishik Bazaz, Horthense Tamdem:
Pre and post silicon server platform transient performance using trans-inductor voltage regulator. 1-5 - Javad Bahrami, Mohammad Ebrahimabadi, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi:
Special Session: Security Verification & Testing for SR-Latch TRNGs. 1-10 - Fei Su, Meirav Nitzan, Ankush Sethi, Vaibhav Kumar, Dan Alexandrescu:
Innovation Practices Track: VLSI Functional Safety. 1 - Fei Su, Xiankun Robert Jin, Nilanjan Mukherjee, Yervant Zorian:
Innovation Practices Track: Silicon Lifecycle Management Challenges and Opportunities. 1 - Mikail Yayla, Simon Thomann, Md. Mazharul Islam, Ming-Liang Wei, Shu-Yin Ho, Ahmedullah Aziz, Chia-Lin Yang, Jian-Jia Chen, Hussam Amrouch:
Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories. 1-10 - Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs *. 1-4 - Surendra Hemaram, Soyed Tuhin Ahmed, Mahta Mayahinia, Christopher Münch, Mehdi B. Tahoori:
A Low Overhead Checksum Technique for Error Correction in Memristive Crossbar for Deep Learning Applications. 1-7 - Irith Pomeranz:
Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs. 1-7 - Vinay Kumar, Bhrugurajsinh Chudasama, Bin B. W. Wang, Manish Arora, Bharath Shankaranarayanan:
Allocating Physically Aware Embedded Memory Test & Repair Processor using Floorplan Info at the RTL Design Level. 1-4 - Mridha Md Mashahedur Rahman, M. Sazadur Rahman, Rasheed Kibria, Mike Borza, Bandy Reddy, Adam Cron, Fahim Rahman, Mark Tehranipoor, Farimah Farahmandi:
CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme. 1-8 - Lilas Alrahis, Ozgur Sinanoglu:
Graph Neural Networks for Hardware Vulnerability Analysis - Can you Trust your GNN? 1-4 - Mohammad Ershad Shaik, Abhishek Kumar Mishra, Yonghyun Kim:
Predicting the Silent Data Error Prone Devices Using Machine Learning. 1-4 - Francesco Angione, Paolo Bernardi, Nicola Di Gruttola Giardino, Davide Appello, Claudia Bertani, Vincenzo Tancorre:
A guided debugger-based fault injection methodology for assessing functional test programs. 1-7 - Sohrab Aftabjahani, Mark Tehranipoor, Farimah Farahmandi, Bulbul Ahmed, Ryan Kastner, Francesco Restuccia, Andres Meza, Kaki Ryan, Nicole Fern, Jasper Van Woudenberg, Rajesh Velegalati, Cees-Bart Breunesse, Cynthia Sturton, Calvin Deutschbein:
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance. 1-10 - Bapi Vinnakota, Jaber Derakhshandeh, Eric Beyne, Erik Jan Marinissen, Sreejit Chakravarty:
IP Session on Chiplet: Design, Assembly, and Test. 1 - Fei Su, Marc Hunter, Chen He, Sashi Obilisetty:
Innovation Practices Track: Innovation on Telemetry Monitoring. 1 - Daniel Tille, Leon Klimasch, Sebastian Huhn:
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin. 1-6 - Artur Ghukasyan, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era. 1-4 - Ian Hill, André Ivanov:
Gerabaldi: A Temporal Simulator for Probabilistic IC Degradation and Failure Processes. 1-7
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