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Shih-Arn Hwang
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2020 – today
- 2024
- [c4]Chien-Yu Lu, Bo-Jr Huang, Min-Chieh Chen, Ollie Tsai, Alfred Tsai, Eric Jia-Wei Fang, Yuju Cho, Harry H. Chen, Ping Kao, Ericbill Wang, Hugh Mair, Shih-Arn Hwang:
14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU. ISSCC 2024: 260-262 - 2023
- [c3]Bo-Jr Huang, Alfred Tsai, Lear Hsieh, Kathleen Chang, C.-J. Tsai, Jia-Ming Chen, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Jack Ciao, Barry Chen, Chuck Chang, Ping Kao, Ericbill Wang, Harry H. Chen, Hugh Mair, Shih-Arn Hwang:
A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. ISSCC 2023: 40-41 - 2022
- [c2]Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang:
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. ISSCC 2022: 50-52 - 2021
- [c1]Bo-Jr Huang, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Rory Huang, Angus Lin, Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, Y. S. Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang:
35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC. ISSCC 2021: 490-492
2000 – 2009
- 2001
- [j3]Shih-Arn Hwang, Cheng-Wen Wu
:
Unified VLSI systolic array design for LZ data compression. IEEE Trans. Very Large Scale Integr. Syst. 9(4): 489-499 (2001)
1990 – 1999
- 1999
- [j2]Shih-Arn Hwang, Cheng-Wen Wu:
Test Energy Minimization for C-Testable ILAs. J. Inf. Sci. Eng. 15(6): 899-911 (1999) - 1998
- [j1]Shih-Arn Hwang, Jin-Hua Hong, Cheng-Wen Wu
:
Sequential circuit fault simulation using logic emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 724-736 (1998)
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