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ITC 2004: Charlotte, NC, USA
- Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA. IEEE Computer Society 2003, ISBN 0-7803-8581-0
Cover
- International Test Conference - Cover.
- International Test Conference - Title Page. i
- International Test Conference - Copyright. ii
Introduction
- Welcoming Message. 1
- Steering Committee and Subcommittees. 2-3
- Ned Kornfield Memorial. 4
- 2003 Paper Awards. 5
- Technical Program Committee. 6-8
- ITC Technical Paper Evaluation and Selection Process. 10
- 2005 Call for Papers. 11
- TTTC: Test Technology Technical Council. 14-16
- Technical Paper Reviewers. 17-22
Session 1: Plenary
- Bernd Koenemann:
Test In the Era of "What You see Is NOT What You Get". 12 - Robert Madge:
New Test Paradigms for Yield and Manufacturability. 13
Session 2: Microprocessor Test
- Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono:
AC IO Loopback Design for High Speed µProcessor IO Test. 23-30 - Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham:
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. 31-37 - David M. Wu, Mike Lin, Madhukar Reddy, Talal Jaber, Anil Sabbavarapu, Larry Thatcher:
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor. 38-47
Session 3: Logic BIST
- Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers:
Efficient Pattern Mapping for Deterministic Logic BIST. 48-56 - Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng:
Logic BIST with Scan Chain Segmentation. 57-66 - Omar I. Khan, Michael L. Bushnell:
Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing. 67-76
Session 4: BIST for Jitter
- Takahiro J. Yamaguchi, Masahiro Ishida, Kiyotaka Ichiyama, Mani Soma, Christian Krawinkel, Katsuaki Ohsawa, Masao Sugai:
A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems. 77-84 - Karen Taylor, Bryan Nelson, Alan Chong, Hieu Nguyen, Henry C. Lin, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz:
Experimental Results for High-Speed Jitter Measurement Technique. 85-94 - Stephen K. Sunter, Aubin Roy, Jean-Francois Cote:
An Automated, Complete, Structural Test Solution for SERDES. 95-104
Session 5: Memory Testing
- Benjamin M. Mauck, Vishnumohan Ravichandran, Usman Azeez Mughal:
A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis. 105-113 - Ad J. van de Goor, Said Hamdioui, Rob Wadsworth:
Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. 114-123 - Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu:
MRAM Defect Analysis and Fault Modeli. 124-133
Session 6: Failure Characterization Methods for IC Diagnosis
- Stas Polonsky, Keith A. Jenkins, Alan J. Weger, Shinho Cho:
CMOS IC diagnostics using the luminescence of OFF-state leakage currents. 134-139 - Peilin Song, Franco Stellari, Alan J. Weger, Tian Xia:
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current. 140-147 - Vijay Reddy, John M. Carulli, Anand T. Krishnan, William Bosch, Brendan Burgess:
Impact of Negative Bias Temperature Instability on Product Parametric Drift. 148-155
Session 7: Board and System Test: At-Speed and Bounce-Free
- Heon C. Kim, Hong Shin Jun, Xinli Gu, Sung Soo Chung:
At-Speed Interconnect Test and Diagnosis of External Memories on a System. 156-162 - Kendrick Baker, Mehrdad Nourani:
Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors. 163-172 - Hong Shin Jun, Sung Soo Chung, Sang H. Baeg:
Removing JTAG Bottlenecks in System Interconnect Test. 173-180
Session 8: Methods and Strategies for Optimal Test
- Manu Rehani, David Abercrombie, Robert Madge, Jim Teisher, Jason Saw:
ATE Data Collection - A comprehensive requirements proposal to maximize ROI of test. 181-189 - Jonathan Hops, Brian Swing, Brian Phelps, Bruce Sudweeks, John Pane, James Kinslow:
Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions. 190-196 - Peter Patten:
Divide and Conquer based Fast Shmoo algorithms. 197-202 - Robert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler:
In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost. 203-212
Session 9: In Search of Small Delay Defects
- Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger:
On Hazard-free Patterns for Fine-delay Fault Testing. 213-222 - Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran:
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. 223-231 - Saravanan Padmanaban, Spyros Tragoudas:
A Critical Path Selection Method for Delay Testing. 232-241 - Haihua Yan, Adit D. Singh:
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. 242-251
Session 10: Mixed-Signal BIST and DFT
- Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee:
Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. 252-261 - Abhishek Singh, Chintan Patel, Jim Plusquellic:
On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing. 262-270 - Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi:
Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. 271-280 - Geert Seuren, Tom Waayers:
Extending the Digital Core-based Test Methodology to Support Mixed-Signal. 281-289
Session 11: Advances in Testing for Defects
- Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede:
Systematic Defects in Deep Sub-Micron Technologies. 290-299 - Chris Schuermyer, Jens Ruffler, W. Robert Daasch:
Minimum Testing Requirements to Screen Temperature Dependent Defects. 300-308 - Phil Nigh, Anne E. Gattiker:
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions. 309-318 - Chintan Patel, Abhishek Singh, Jim Plusquellic:
Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. 319-328
Session 12: Advances in DFT
- Matthew L. King, Kewal K. Saluja:
Testing Micropipelined Asynchronous Circuits. 329-338 - Bo Yang, Kaijie Wu, Ramesh Karri
:
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. 339-344 - C. P. Ravikumar, Graham Hetherington:
A Holistic Parallel and Hierarchical Approach towards Design-For-Test. 345-354 - Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington:
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. 355-364
Session 13: Board and System Test: Board Test Effectiveness
- Kenneth P. Parker:
A New Probing Technique for High-Speed/High-Density Printed Circuit Boards. 365-374 - Rodger Schuttert, D. C. L. (Erik) van Geest, A. Kumar:
On-Chip Mixed-Signal Test Structures Re-used for Board Test. 375-383 - Carlos Michel, Rosa D. Reinosa:
Test Strategy Cost Model Innovations. 384-392 - Amit Verma, Charles Robinson, Steve Butkovich:
Production Test Effectiveness of Combined Automated Inspection and ICT Test Strategies. 393-402
Session 14: Developments in ATE Software Standards
- Rochit Rajsuman, Masuda Noriyuki:
Open Architecture Test System: System Architecture and Design. 403-412 - Ankan K. Pramanick, Ramachandran Krishnaswamy, Mark Elston, Toshiaki Adachi, Harsanjeet Singh, Bruce R. Parnas:
Test Programming Environment in a Modular, Open Architecture Test System. 413-422 - David Dowding, Ernie Wahl, Don Organ:
Extending STIL 1450 Standard for Test Program Flow. 423-431
Session 15: Handling of Unknowns
- Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher:
X-Tolerant Signature Analysis. 432-441 - Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage. 442-451 - Vivek Chickermane, Brian Foutz, Brion L. Keller:
Channel Masking Synthesis for Efficient On-Chip Test Compression. 452-461
Session 16: Emerging Technologies Fault Modeling and Tolerance
- Jason G. Brown, R. D. (Shawn) Blanton:
CAEN-BIST: Testing the NanoFabric. 462-471 - Wenjing Rao, Alex Orailoglu, Ramesh Karri
:
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems. 472-478 - Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi:
Routability and Fault Tolerance of FPGA Interconnect Architectures. 479-488
Session 17: Advances in Diagnosis
- Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. 489-497 - Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski:
Fault Diagnosis in Designs with Convolutional Compactors. 498-507 - Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary:
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. 508-517
Session 18: Test Economics
- Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane:
An Economic Analysis and ROI Model for Nanometer Test. 518-524 - Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski:
Realizing High Test Quality Goals with Smart Test Resource Usage. 525-533 - Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley:
Low Overhead Delay Testing of ASICS. 534-542
Session 19: Board and System Test: Extending Boundary-Scan to RF and HS Serial Testing
- Saghir A. Shaikh:
IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver. 543-550 - Juha Häkkinen, Pekka Syri, Juha-Veikko Voutilainen, Markku Moilanen:
A Frequency Mixing and Sub-Sampling Based RF-Measurement Apparatus for IEEE 1149.4. 551-559 - Jeff Rearick, Sylvia Patterson, Krista Dorner:
Integrating Boundary Scan into Multi-GHz I/O Circuitry. 560-566
Session 20: Squeezing the Picoseconds
- Masashi Shimanouchi:
Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE. 567-576 - Ahmed Rashid Syed:
Automatic Delay Calibration Method for Multi-channel CMOS Formatter. 577-586 - A. T. Sivaram, Pascal Pierra, Shida Sheibani, Nancy Wang-Lee, Jorge E. Solorzano, Lily Tran:
Active Tester Interface Unit Design For Data Collection. 587-596
Session 21: ATPG/FAULT Simulation Specialties
- Feng Shi, Yiorgos Makris:
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits. 597-606 - Kameshwar Chandrasekar, Michael S. Hsiao:
Decision Selection and Learning for an All-Solutions ATPG Engine. 607-616 - Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal:
On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. 617-626
Session 22: Interconnect Testing and Fault Diagnosis in FPGAS
- Dave Mark, Jenny Fan:
Localizing Open Interconnect Defects using Targeted Routing in FPGA's. 627-634 - Mehdi Baradaran Tahoori, Subhasish Mitra:
Interconnect Delay Testing of Designs on Programmable Logic Devices. 635-644 - Mehdi Baradaran Tahoori:
Application-Dependent Diagnosis of FPGAs. 645-654
Session 23: Industry Case Studies in Testing
- A. Cabbibo, J. Conder, M. Jacobs:
Feed Forward Test Methodology Utilizing Device Identification. 655-660 - Leendert M. Huisman, Maroun Kassab, Leah Pastel:
Data Mining Integrated Circuit Fails with Fail Commonalities. 661-668 - M. Enamul Amyeen, Srikanth Venkataraman, Ajay Ojha, Sangbong Lee:
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor. 669-678
Session 24: Lecture Series - Test Trends and Challenges
- Sandip Kundu, T. M. Mak, Rajesh Galivanche:
Trends in manufacturing test methods and their implications. 679-687 - Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge:
Trends in Testing Integrated Circuits. 688-697 - Alfred L. Crouch:
Future Trends in Test: The Adoption and Use of Low Cost Structural Testers. 698-703
Session 25: Board and System Test: System and Field Test
- Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau:
Simulation Based System Level Fault Insertion Using Co-verification Tools. 704-710 - Chen-Huan Chiang, Paul J. Wheatley, Kenneth Y. Ho, Ken L. Cheung:
Testing and Remote Field Update of Distributed Base Stations in a Wireless Network. 711-718 - Yujun Zhang, Zhongcheng Li:
IPV6 Conformance Testing: Theory and Practice. 719-727
Session 26: ATE for the Fastest Devices
- Mohamed M. Hafed, Antonio H. Chan, Geoffrey D. Duerden, Bardia Pishdad, Clarence Tam, Sébastien Laberge, Gordon W. Roberts:
A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing. 728-737 - A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson:
Tester Architecture For The Source Synchronous Bus. 738-747 - David C. Keezer
, Dany Minier, F. Binette:
Modular Extension of ATE to 5 Gbps. 748-757
Session 27: SoC: Mixed Signals, Size and Speed
- Hans T. Heineken, Jitendra Khare:
Test Strategies For a 40Gbps Framer SoC. 758-763 - Bernd Laquai:
A Model-based Test Approach for Testing High-Speed PLLs and Phase Regulation Circuitry in SOC Devices. 764-772 - K. Nikila, Rubin A. Parekhji:
DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device. 773-782
Session 28: RF Testing
- Erkan Acar, Sule Ozev:
Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis. 783-792 - Dana Brown, John Ferrario, Randy Wolf, Jing Li, Jayendra Bhagat:
RF Testing on a Mixed Signal Tester. 793-800 - Soumendu Bhattacharya, Abhijit Chatterjee:
Use of Embedded Sensors for Built-In-Test of RF Circuits. 801-809
Session 29: State Space Exploration and Test Generation
- Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra:
Formal Verification of a System-on-Chip Using Computation Slicing. 810-819 - Qingwei Wu, Michael S. Hsiao:
State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation. 820-829 - Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou, Chun-Yao Wang:
Verification on Port Connections. 830-836
Session 30: SoC Test Case Studies
- Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris:
Built-In Self-Test for System-on-Chip: A Case Study. 837-846 - Jeff Remmers, Moe Villalba, Richard Fisette:
Hierarchical DFT Methodology - A Case Study. 847-856
Session 31: Board and System Test: Board and System-Level BIST Techniques
- C. J. Clark, Mike Ricchetti:
A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and Systems. 857-866 - Liviu Miclea, Szilárd Enyedi
, Gavril Toderean, Alfredo Benso, Paolo Prinetto:
Towards Microagent based DBIST/DBISR. 867-874 - David Resnick:
Embedded Test for a new Memory-Card Architecture. 875-882
Session 32: Test of Digital, Analog and MEMS C
- Fei Su, Krishnendu Chakrabarty:
Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays. 883-892 - Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski:
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. 893-902 - Ali Muhtaroglu, Benoit Provost, Tawfik Rahal-Arabi, Greg Taylor:
I/O Self-Leakage Test. 903-906 - Sreejit Chakravarty, Eric W. Savage, Eric N. Tran:
Defect Coverage Analysis of Partitioned Testing. 907-915
Session 33: Test Compression
- Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai:
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction. 916-925 - Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand:
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. 926-935 - Kedarnath J. Balakrishnan, Nur A. Touba:
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. 936-944 - Baris Arslan, Alex Orailoglu:
Test Cost Reduction Through A Reconfigurable Scan Architecture. 945-952
Session 34: Mixed-Signal Test Techniques
- Christopher S. Taillefer, Gordon W. Roberts:
Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment without Increasing Test Time. 953-962