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ORCID"Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache."
Zhi-Yong Liu et al. (2017)
- Zhi-Yong Liu
, Hsiu-Chuan Shih, Bing-Yang Lin, Cheng-Wen Wu:
Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. IEEE Des. Test 34(2): 69-78 (2017)
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