default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID6th Asian Test Symposium 1997: Akita, Japan
- 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan. IEEE Computer Society 1997, ISBN 0-8186-8209-4
Keynote Address
- Vinod K. Agarwal:
Embedded Test and Measurement Critical for Deep Submicron Technology. 2
Test Generation I
- Irith Pomeranz, Sudhakar M. Reddy:
On the Compaction of Test Sets Produced by Genetic Optimization. 4-9 - Seiji Kajihara, Tsutomu Sasao:
On the Adders with Minimum Tests. 10-15 - Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki:
Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL. 16-21 - Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita:
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits. 22-
Design for Testability I
- Silvia Chiusano
, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
Guaranteeing Testability in Re-encoding for Low Power. 30-35 - Marc Perbost, Ludovic Le Lan, Christian Landrault:
Automatic Testability Analysis of Boards and MCMs at Chip Level. 36-41 - Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu:
Design of C-Testable Multipliers Based on the Modified Booth Algorithm. 42-47 - Shiyi Xu, Peter Waignjo, Percy G. Dias, Bole Shi:
Testability Prediction for Sequential Circuits Using Neural Network. 48-
Test Generation II
- Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero:
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. 56-61 - Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
Sequential Test Generation Based on Circuit Pseudo-Transformation. 62-67 - Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. 68-73 - Irith Pomeranz, Sudhakar M. Reddy:
TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. 74-
Fault Tolerance
- Joseph C. W. Pang, Mike W. T. Wong, Yim-Shu Lee:
Design and Implementation of Strongly Code-Disjoint CMOS Built-in Intermediate Voltage Sensor for Totally Self-Checking Circuits. 82-87 - Takehiro Ito, Itsuo Takanami:
On fault injection approaches for fault tolerance of feedforward neural networks. 88-93 - Masahiro Tsunoyama, Masahiko Uenoyama, Tatsuya Kabasawa:
A concurrent fault-detection scheme for FFT processors. 94-99 - Hendrik Hartje, Michael Gössel, Egor S. Sogomonyan:
Code-Disjoint Circuits for Parity Circuits. 100-
Case Studies for DFT Techniques in Japanese Industry
- Junji Mori, Ben Mathew, Dave Burns, Yeuk-Hai Mok:
Testability Features of R10000 Microprocessor. 108-111 - Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto:
Application of a Design for Delay Testability Approach to High Speed Logic LSIs. 112-115 - Takaki Yoshida, Reisuke Shimoda, Takashi Mizokawa, Katsuhiro Hirayama:
An effective fault simulation method for core based LSI. 116-121 - Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida:
Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs. 122-125 - Michiaki Emori, Junko Kumagai, Koichi Itaya, Takashi Aikyo, Tomoko Anan, Junichi Niimi:
ATREX : Design for Testability System for Mega Gate LSIs. 126-
Test Technologies
- Cheng-Wen Wu:
On energy efficiency of VLSI testing. 132-137 - Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel:
ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs. 138-142 - Vinay Dabholkar, Sreejit Chakravarty:
Computing stress tests for interconnect defects. 143-148 - Josep Altet, Antonio Rubio, Hideo Tamamoto:
Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits. 149-154 - Zahari M. Darus, Iftekhar Ahmed, Liakot Ali:
A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register. 155-
Beam Testing of VLSI Circuits in Japan
- Katsuyoshi Miura, Kohei Nakata, Koji Nakamae, Hiromu Fujioka:
Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data. 162-167 - Koji Yamazaki, Teruhiko Yamada:
An approach to diagnose logical faults in partially observable sequential circuits. 168-173 - Norio Kuji:
Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits. 174-
Mixed-Signal Test
- Naim Ben-Hamida, Khaled Saab, David Marche, Bozena Kaminska:
A perturbation based fault modeling and simulation for mixed-signal circuits. 182-187 - Takahiro J. Yamaguchi:
Static Testing of ADCs Using Wavelet Transforms. 188-193 - Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen:
Analog signal metrology for mixed signal ICs. 194-
Novel Beam Testing Techniques in Japan
- F. Komatsu, H. Motoki, M. Miyoshi:
A New Auto-Focus Method in Critical Dimension Measurement SEM. 202-207 - Kazuyuki Ozaki, Hidenori Sekiguchi, Shinichi Wakana, Yoshiro Goto, Yasutoshi Umehara, Jun Matsumoto:
Novel Optical Probing System for Quarter-micron VLSI Circuits. 208-213 - Kiyoshi Nikawa, Shoji Inoue:
New Capabilities of OBIRCH Method for Fault Localization and Defect Detection. 214-
Decision Diagrams and Logic Optimization
- Hideyuki Ichihara, Kozo Kinoshita:
On Acceleration of Logic Circuits Optimization Using Implication Relations. 222-227 - MoonBae Song, Hoon Chang:
A variable reordering method for fast optimization of binary decision diagrams. 228-233 - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On Decomposition of Kleene TDDs. 234-
FPGA Test
- Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara:
Testing for the programming circuit of LUT-based FPGAs. 242-247 - Wei-Kang Huang, M. Y. Zhang, Fred J. Meyer, Fabrizio Lombardi:
A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs. 248-253 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. 254-
Software Test
- Cheer-Sun D. Yang, Lori L. Pollock:
An Algorithm for All-du-path Testing Coverage of Shared Memory Parallel Programs. 263-268 - Osamu Mizuno, Shinji Kusumoto, Tohru Kikuno, Yasunari Takagi, Keishi Sakamoto:
Estimating the Number of Faults using Simulator based on Generalized Stochastic Petri-Net Model. 269-
Diagnosis
- Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara:
On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs. 276-281 - Xiaoqing Wen:
Fault Diagnosis for Static CMOS Circuits. 282-287 - Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen:
Fault diagnosis of odd-even sorting networks. 288-
Design for Testability II
- Jacob Savir:
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. 296-299 - Sandeep Bhatia, Prab Varma:
Test Compaction in a Parallel Access Scan Environment. 300-305 - Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu:
A Partial Scan Design Method Based on n-Fold Line-up Structures. 306-
Delay Test
- Sreejit Chakravarty:
On the capability of delay tests to detect bridges and opens. 314-319 - Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga:
A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. 320-325 - Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min:
Memory Efficient ATPG for Path Delay Faults. 326-331 - Xiaoming Yu, Yinghua Min:
Design of delay-verifiable combinational logic by adding extra inputs. 332-
Built-in Self-Test I
- Kowen Lai, Christos A. Papachristou, Mikhail Baklashov:
BIST testability enhancement using high level test synthesis for behavioral and structural designs. 338-342 - Jacob Savir:
On Chip Weighted Random Patterns. 343-352 - Hiroshi Yokoyama, Xiaoqing Wen, Hideo Tamamoto:
Random Pattern Testable Design with Partial Circuit Duplication. 353-358 - Michinobu Nakao, Kazumi Hatayama, Isao Higashi:
Accelerated Test Points Selection Method for Scan-Based BIST. 359-
Current Testing
- Maneesha Dalmia, André Ivanov, Sassan Tabatabaei:
Power supply current monitoring techniques for testing PLLs. 366-371 - Masaki Hashizume, Toshimasa Kuchii, Takeomi Tamesada:
Supply Current Test for Unit-to-unit Variations of Electrical Characteristics in Gates. 372-377 - Yinghua Min, Zhuxing Zhao, Zhongcheng Li:
IDDT Testing. 378-383 - Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee:
Built-in current sensor designs based on the bulk-driven technique. 384-
Built-in Self-Test II
- René David:
Test Length for Random Testing of Sequential Machines Application to RAMs. 392-397 - Yuejian Wu, Sanjay Gupta:
Built-In Self-Test for Multi-Port RAMs. 398-403 - Gang-Min Park, Hoon Chang:
An extended march test algorithm for embedded memories. 404-409 - Dariusz Badura, Andrzej Hlawiczka:
Low Cost Bist for Edac Circuits. 410-415
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-07 21:20 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
