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ORCIDVTS 2011: Dana Point, CA, USA
- 29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA. IEEE Computer Society 2011, ISBN 978-1-61284-657-6
- Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang
, LeRoy Winemberg, Magdy S. Abadir:
Understanding customer returns from a test perspective. 2-7 - Mohammad Hossein Neishaburi, Zeljko Zilic:
A distributed AXI-based platform for post-silicon validation. 8-13 - Kanad Basu, Prabhat Mishra:
Efficient trace data compression using statically selected dictionary. 14-19 - Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. 20-25 - Shreepad Panth, Sung Kyu Lim:
Scan chain and power delivery network synthesis for pre-bond test of 3D ICs. 26-31 - Eshan Singh:
Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs. 32-37 - Saghir Shaikh:
Test and characterization of high-speed circuits. 38 - Samah Mohamed Saeed, Ozgur Sinanoglu:
Expedited response compaction for scan power reduction. 40-45 - Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma:
Leakage power profiling and leakage power reduction using DFT hardware. 46-51 - Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker:
Levelized low cost delay test compaction considering IR-drop induced power supply noise. 52-57 - Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
Automatic test stimulus generation for accurate diagnosis of RF systems using transient response signatures. 58-63 - Suraj Sindia, Vishwani D. Agrawal, Virendra Singh:
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. 64-69 - Takushi Hashida, Yuuki Araga, Makoto Nagata:
A diagnosis testbench of analog IP cores against on-chip environmental disturbances. 70-75 - Ke Peng, Fang Bao, Geoff Shofner, LeRoy Winemberg, Mohammad Tehranipoor:
Case Study: Efficient SDD test generation for very large integrated circuits. 78-83 - Irith Pomeranz:
Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. 84-89 - Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham:
Efficient and product-representative timing model validation. 90-95 - Yasuo Sato:
Special session: Multifaceted approaches for field reliability. 96 - Mike Laisne:
Advanced methods for leveraging new test standards. 97 - Siddharth Garg, Diana Marculescu:
Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions. 99 - Kurt Rosenfeld, Ramesh Karri:
Security-aware SoC test access mechanisms. 100-104 - Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri:
Design and analysis of ring oscillator based Design-for-Trust technique. 105-110 - Suriyaprakash Natarajan, Arani Sinha:
The buck stops with wafer test: Dream or reality? 111 - Kee Sup Kim, Rob Roy:
Apprentice - VTS edition: Season 4. 113 - Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg:
Special session 5B: Panel How much toggle activity should we be testing with? 114 - Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou:
A Novel mechanism for speed characterization during delay test. 116-121 - Seongmoon Wang:
An efficient method to screen resistive opens under presence of process variation. 122-127 - Irith Pomeranz:
On clustering of undetectable transition faults in standard-scan circuits. 128-133 - Rudrajit Datta, Nur A. Touba:
Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories. 134-139 - Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme:
Programmable extended SEC-DED codes for memory errors. 140-145 - Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu:
Training-based forming process for RRAM yield improvement. 146-151 - Arani Sinha, Suriyaprakash Natarajan:
The bang for the buck with resiliency: Yield or field? 152 - Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal:
Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. 154-159 - Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty:
Power-safe test application using an effective gating approach considering current limits. 160-165 - Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor:
Power-aware test generation with guaranteed launch safety for at-speed scan testing. 166-171 - Wing Chiu Tam, Ronald D. Blanton:
SLIDER: A fast and accurate defect simulation framework. 172-177 - Ender Yilmaz, Anne Meixner, Sule Ozev:
An industrial case study of analog fault modeling. 178-183 - Jesús Moreno, Víctor H. Champac, Michel Renovell:
A new methodology for realistic open defect detection probability evaluation under process variations. 184-189 - Julien Guilhemsang, Olivier Héron, Nicolas Ventroux, Olivier Goncalves, Alain Giulieri:
Impact of the application activity on intermittent faults in embedded systems. 191-196 - Sreenivas Gangadhar, Spyros Tragoudas:
An analytical method for estimating SET propagation. 197-202 - Celestino V. Martins, Jorge Semião, Julio César Vázquez, Víctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira:
Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. 203-208 - Jeffrey F. Wheeldon:
Calibrated high-efficiency testing and modelling methodologies for concentrated multi-junction solar cells. 209 - Shobha Vasudevan:
Coverage closure in SoC verification: Are we chasing a mirage? 211 - Kyoung Youn Cho, Rajagopalan Srinivasan:
A scan cell architecture for inter-clock at-speed delay testing. 213-218 - Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu:
Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. 219-224 - Dilip K. Bhavsar:
Harmony Widget for X-free scan testing. 225-228 - Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux:
Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure. 229-234 - Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer:
Exponent monitoring for low-cost concurrent error detection in FPU control logic. 235-240 - Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Enhancing online error detection through area-efficient multi-site implications. 241-246 - Priyadharshini Shanmugasundaram, Vishwani D. Agrawal:
Dynamic scan clock control for test time reduction maintaining peak power limit. 248-253 - Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick:
Structural tests of slave clock gating in low-power flip-flop. 254-259 - Nader Alawadhi, Ozgur Sinanoglu:
Revival of partial scan: Test cube analysis driven conversion of flip-flops. 260-265 - Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy:
Memory-based embedded digital ATE. 266-271 - Songwei Pei, Huawei Li, Xiaowei Li:
A unified test architecture for on-line and off-line delay fault detections. 272-277 - Ujjwal Guin, Chen-Huan Chiang:
Design for Bit Error Rate estimation of high speed serial links. 278-283 - Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal:
An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. 285-290 - Kameshwar Chandrasekar, Surendra Bommu, Sanjay Sengupta:
Low Coverage Analysis using dynamic un-testability debug in ATPG. 291-296 - Jia Li, Yu Huang, Dong Xiang:
Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes. 297-302 - Yasuhiro Takahashi, Akinori Maeda:
Multi Domain Test: Novel test strategy to reduce the Cost of Test. 303-308 - Junxia Ma, Nisar Ahmed, Mohammad Tehranipoor:
Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures. 309-314 - W.-A. Lin, C.-C. Lee, J.-L. Huang:
Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs. 315-320 - Hideo Okawara:
Practical signal processing at mixed signal test venues - Trend removal, noise reduction, wideband signal capturing -. 322 - LeRoy Winemberg, Mohammad Tehranipoor:
Special session: Hot topic: Smart silicon. 323 - Anne Gattiker:
Invited paper: Yin and Yang of embedded sensors for post-scaling-era. 324-327 - Cheng-Wen Wu:
Special session: Hot topic design and test of 3D and emerging memories. 328
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